Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
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Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
◆ RTC_DR_DT_MASK
#define RTC_DR_DT_MASK (0x3) |
◆ RTC_DR_DT_SHIFT
#define RTC_DR_DT_SHIFT (4) |
◆ RTC_DR_DU_MASK
#define RTC_DR_DU_MASK (0xf) |
◆ RTC_DR_DU_SHIFT
#define RTC_DR_DU_SHIFT (0) |
◆ RTC_DR_MT_MASK
#define RTC_DR_MT_MASK (1) |
◆ RTC_DR_MT_SHIFT
#define RTC_DR_MT_SHIFT (12) |
◆ RTC_DR_MU_MASK
#define RTC_DR_MU_MASK (0xf) |
◆ RTC_DR_MU_SHIFT
#define RTC_DR_MU_SHIFT (8) |
◆ RTC_DR_WDU_MASK
#define RTC_DR_WDU_MASK (0x7) |
◆ RTC_DR_WDU_SHIFT
#define RTC_DR_WDU_SHIFT (13) |
◆ RTC_DR_YT_MASK
#define RTC_DR_YT_MASK (0xf) |
◆ RTC_DR_YT_SHIFT
#define RTC_DR_YT_SHIFT (20) |
◆ RTC_DR_YU_MASK
#define RTC_DR_YU_MASK (0xf) |
◆ RTC_DR_YU_SHIFT
#define RTC_DR_YU_SHIFT (16) |