Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
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Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
◆ RTC_TR_HT_MASK
#define RTC_TR_HT_MASK (0x3) |
◆ RTC_TR_HT_SHIFT
#define RTC_TR_HT_SHIFT (20) |
◆ RTC_TR_HU_MASK
#define RTC_TR_HU_MASK (0xf) |
◆ RTC_TR_HU_SHIFT
#define RTC_TR_HU_SHIFT (16) |
◆ RTC_TR_MNT_MASK
#define RTC_TR_MNT_MASK (0x7) |
◆ RTC_TR_MNT_SHIFT
#define RTC_TR_MNT_SHIFT (12) |
◆ RTC_TR_MNU_MASK
#define RTC_TR_MNU_MASK (0xf) |
◆ RTC_TR_MNU_SHIFT
#define RTC_TR_MNU_SHIFT (8) |
◆ RTC_TR_PM
#define RTC_TR_PM (1 << 22) |
◆ RTC_TR_ST_MASK
#define RTC_TR_ST_MASK (0x7) |
◆ RTC_TR_ST_SHIFT
#define RTC_TR_ST_SHIFT (4) |
◆ RTC_TR_SU_MASK
#define RTC_TR_SU_MASK (0xf) |
◆ RTC_TR_SU_SHIFT
#define RTC_TR_SU_SHIFT (0) |