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| #define | USART1 USART1_BASE |
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| #define | USART2 USART2_BASE |
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| #define | USART3 USART3_BASE |
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| #define | UART4 UART4_BASE |
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| #define | UART5 UART5_BASE |
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| #define | USART_SR(usart_base) MMIO32((usart_base) + 0x00) |
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| #define | USART1_SR USART_SR(USART1_BASE) |
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| #define | USART2_SR USART_SR(USART2_BASE) |
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| #define | USART3_SR USART_SR(USART3_BASE) |
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| #define | UART4_SR USART_SR(UART4_BASE) |
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| #define | UART5_SR USART_SR(UART5_BASE) |
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| #define | USART_DR(usart_base) MMIO32((usart_base) + 0x04) |
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| #define | USART1_DR USART_DR(USART1_BASE) |
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| #define | USART2_DR USART_DR(USART2_BASE) |
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| #define | USART3_DR USART_DR(USART3_BASE) |
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| #define | UART4_DR USART_DR(UART4_BASE) |
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| #define | UART5_DR USART_DR(UART5_BASE) |
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| #define | USART_BRR(usart_base) MMIO32((usart_base) + 0x08) |
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| #define | USART1_BRR USART_BRR(USART1_BASE) |
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| #define | USART2_BRR USART_BRR(USART2_BASE) |
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| #define | USART3_BRR USART_BRR(USART3_BASE) |
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| #define | UART4_BRR USART_BRR(UART4_BASE) |
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| #define | UART5_BRR USART_BRR(UART5_BASE) |
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| #define | USART_CR1(usart_base) MMIO32((usart_base) + 0x0c) |
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| #define | USART1_CR1 USART_CR1(USART1_BASE) |
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| #define | USART2_CR1 USART_CR1(USART2_BASE) |
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| #define | USART3_CR1 USART_CR1(USART3_BASE) |
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| #define | UART4_CR1 USART_CR1(UART4_BASE) |
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| #define | UART5_CR1 USART_CR1(UART5_BASE) |
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| #define | USART_CR2(usart_base) MMIO32((usart_base) + 0x10) |
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| #define | USART1_CR2 USART_CR2(USART1_BASE) |
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| #define | USART2_CR2 USART_CR2(USART2_BASE) |
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| #define | USART3_CR2 USART_CR2(USART3_BASE) |
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| #define | UART4_CR2 USART_CR2(UART4_BASE) |
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| #define | UART5_CR2 USART_CR2(UART5_BASE) |
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| #define | USART_CR3(usart_base) MMIO32((usart_base) + 0x14) |
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| #define | USART1_CR3 USART_CR3(USART1_BASE) |
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| #define | USART2_CR3 USART_CR3(USART2_BASE) |
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| #define | USART3_CR3 USART_CR3(USART3_BASE) |
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| #define | UART4_CR3 USART_CR3(UART4_BASE) |
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| #define | UART5_CR3 USART_CR3(UART5_BASE) |
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| #define | USART_GTPR(usart_base) MMIO32((usart_base) + 0x18) |
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| #define | USART1_GTPR USART_GTPR(USART1_BASE) |
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| #define | USART2_GTPR USART_GTPR(USART2_BASE) |
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| #define | USART3_GTPR USART_GTPR(USART3_BASE) |
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| #define | UART4_GTPR USART_GTPR(UART4_BASE) |
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| #define | UART5_GTPR USART_GTPR(UART5_BASE) |
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| #define | USART_FLAG_PE USART_SR_PE |
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| #define | USART_FLAG_FE USART_SR_FE |
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| #define | USART_FLAG_NF USART_SR_NF |
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| #define | USART_FLAG_ORE USART_SR_ORE |
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| #define | USART_FLAG_IDLE USART_SR_IDLE |
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| #define | USART_FLAG_RXNE USART_SR_RXNE |
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| #define | USART_FLAG_TC USART_SR_TC |
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| #define | USART_FLAG_TXE USART_SR_TXE |
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| #define | USART_SR_CTS (1 << 9) |
| | CTS: CTS flag. More...
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| #define | USART_SR_LBD (1 << 8) |
| | LBD: LIN break detection flag. More...
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| #define | USART_SR_TXE (1 << 7) |
| | TXE: Transmit data buffer empty. More...
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| #define | USART_SR_TC (1 << 6) |
| | TC: Transmission complete. More...
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| #define | USART_SR_RXNE (1 << 5) |
| | RXNE: Read data register not empty. More...
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| #define | USART_SR_IDLE (1 << 4) |
| | IDLE: Idle line detected. More...
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| #define | USART_SR_ORE (1 << 3) |
| | ORE: Overrun error. More...
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| #define | USART_SR_NE (1 << 2) |
| | NE: Noise error flag. More...
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| #define | USART_SR_FE (1 << 1) |
| | FE: Framing error. More...
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| #define | USART_SR_PE (1 << 0) |
| | PE: Parity error. More...
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| #define | USART_DR_MASK 0x1FF |
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| #define | USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) |
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| #define | USART_BRR_DIV_FRACTION_MASK 0xF |
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| #define | USART_CR1_UE (1 << 13) |
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| #define | USART_CR1_M (1 << 12) |
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| #define | USART_CR1_WAKE (1 << 11) |
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| #define | USART_CR1_PCE (1 << 10) |
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| #define | USART_CR1_PS (1 << 9) |
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| #define | USART_CR1_PEIE (1 << 8) |
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| #define | USART_CR1_TXEIE (1 << 7) |
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| #define | USART_CR1_TCIE (1 << 6) |
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| #define | USART_CR1_RXNEIE (1 << 5) |
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| #define | USART_CR1_IDLEIE (1 << 4) |
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| #define | USART_CR1_TE (1 << 3) |
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| #define | USART_CR1_RE (1 << 2) |
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| #define | USART_CR1_RWU (1 << 1) |
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| #define | USART_CR1_SBK (1 << 0) |
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| #define | USART_CR2_LINEN (1 << 14) |
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| #define | USART_CR2_CLKEN (1 << 11) |
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| #define | USART_CR2_CPOL (1 << 10) |
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| #define | USART_CR2_CPHA (1 << 9) |
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| #define | USART_CR2_LBCL (1 << 8) |
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| #define | USART_CR2_LBDIE (1 << 6) |
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| #define | USART_CR2_LBDL (1 << 5) |
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| #define | USART_CR2_ADD_MASK 0xF |
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| #define | USART_CR3_CTSIE (1 << 10) |
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| #define | USART_CR3_CTSE (1 << 9) |
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| #define | USART_CR3_RTSE (1 << 8) |
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| #define | USART_CR3_DMAT (1 << 7) |
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| #define | USART_CR3_DMAR (1 << 6) |
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| #define | USART_CR3_SCEN (1 << 5) |
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| #define | USART_CR3_NACK (1 << 4) |
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| #define | USART_CR3_HDSEL (1 << 3) |
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| #define | USART_CR3_IRLP (1 << 2) |
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| #define | USART_CR3_IREN (1 << 1) |
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| #define | USART_CR3_EIE (1 << 0) |
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| #define | USART_GTPR_GT_MASK (0xFF << 8) |
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| #define | USART_GTPR_PSC_MASK 0xFF |
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