#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
Macro Definition Documentation
◆ ADC1_BASE
| #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) |
Definition at line 78 of file stm32/f2/memorymap.h.
◆ ADC2_BASE
| #define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) |
Definition at line 79 of file stm32/f2/memorymap.h.
◆ ADC3_BASE
| #define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) |
Definition at line 80 of file stm32/f2/memorymap.h.
◆ BKPSRAM_BASE
| #define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) |
Definition at line 108 of file stm32/f2/memorymap.h.
◆ BX_CAN1_BASE
| #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) |
Definition at line 64 of file stm32/f2/memorymap.h.
◆ BX_CAN2_BASE
| #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) |
Definition at line 65 of file stm32/f2/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) |
Definition at line 104 of file stm32/f2/memorymap.h.
◆ CRYP_BASE
| #define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) |
Definition at line 123 of file stm32/f2/memorymap.h.
◆ DAC_BASE
| #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) |
Definition at line 68 of file stm32/f2/memorymap.h.
◆ DBGMCU_BASE
| #define DBGMCU_BASE (PPBI_BASE + 0x00042000) |
Definition at line 132 of file stm32/f2/memorymap.h.
◆ DCMI_BASE
| #define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) |
Definition at line 121 of file stm32/f2/memorymap.h.
◆ DESIG_FLASH_SIZE_BASE
| #define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) |
Definition at line 135 of file stm32/f2/memorymap.h.
◆ DESIG_UNIQUE_ID0
| #define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) |
Definition at line 137 of file stm32/f2/memorymap.h.
◆ DESIG_UNIQUE_ID1
| #define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) |
Definition at line 138 of file stm32/f2/memorymap.h.
◆ DESIG_UNIQUE_ID2
| #define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) |
Definition at line 139 of file stm32/f2/memorymap.h.
◆ DESIG_UNIQUE_ID_BASE
| #define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) |
Definition at line 136 of file stm32/f2/memorymap.h.
◆ DMA1_BASE
| #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) |
Definition at line 110 of file stm32/f2/memorymap.h.
◆ DMA2_BASE
| #define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) |
Definition at line 111 of file stm32/f2/memorymap.h.
◆ ETHERNET_BASE
| #define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) |
Definition at line 113 of file stm32/f2/memorymap.h.
◆ EXTI_BASE
| #define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) |
Definition at line 87 of file stm32/f2/memorymap.h.
◆ FLASH_BASE
| #define FLASH_BASE (0x08000000U) |
Definition at line 28 of file stm32/f2/memorymap.h.
◆ FLASH_MEM_INTERFACE_BASE
| #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) |
Definition at line 107 of file stm32/f2/memorymap.h.
◆ FSMC_BASE
| #define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) |
Definition at line 129 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_A_BASE
| #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) |
Definition at line 94 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_B_BASE
| #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) |
Definition at line 95 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_C_BASE
| #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) |
Definition at line 96 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_D_BASE
| #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) |
Definition at line 97 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_E_BASE
| #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) |
Definition at line 98 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_F_BASE
| #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) |
Definition at line 99 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_G_BASE
| #define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) |
Definition at line 100 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_H_BASE
| #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) |
Definition at line 101 of file stm32/f2/memorymap.h.
◆ GPIO_PORT_I_BASE
| #define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) |
Definition at line 102 of file stm32/f2/memorymap.h.
◆ HASH_BASE
| #define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) |
Definition at line 124 of file stm32/f2/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) |
Definition at line 60 of file stm32/f2/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) |
Definition at line 61 of file stm32/f2/memorymap.h.
◆ I2C3_BASE
| #define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) |
Definition at line 62 of file stm32/f2/memorymap.h.
◆ IWDG_BASE
| #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) |
Definition at line 51 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE
| #define PERIPH_BASE (0x40000000U) |
Definition at line 29 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE_AHB1
| #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) |
Definition at line 32 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE_AHB2
| #define PERIPH_BASE_AHB2 (0x50000000U) |
Definition at line 33 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE_AHB3
| #define PERIPH_BASE_AHB3 (0x60000000U) |
Definition at line 34 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE_APB1
| #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) |
Definition at line 30 of file stm32/f2/memorymap.h.
◆ PERIPH_BASE_APB2
| #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) |
Definition at line 31 of file stm32/f2/memorymap.h.
◆ POWER_CONTROL_BASE
| #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) |
Definition at line 67 of file stm32/f2/memorymap.h.
◆ RCC_BASE
| #define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) |
Definition at line 106 of file stm32/f2/memorymap.h.
◆ RNG_BASE
| #define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) |
Definition at line 125 of file stm32/f2/memorymap.h.
◆ RTC_BASE
| #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) |
Definition at line 49 of file stm32/f2/memorymap.h.
◆ SDIO_BASE
| #define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) |
Definition at line 82 of file stm32/f2/memorymap.h.
◆ SPI1_BASE
| #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) |
Definition at line 84 of file stm32/f2/memorymap.h.
◆ SPI2_BASE
| #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) |
Definition at line 53 of file stm32/f2/memorymap.h.
◆ SPI3_BASE
| #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) |
Definition at line 54 of file stm32/f2/memorymap.h.
◆ SYSCFG_BASE
| #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) |
Definition at line 86 of file stm32/f2/memorymap.h.
◆ TIM10_BASE
| #define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) |
Definition at line 89 of file stm32/f2/memorymap.h.
◆ TIM11_BASE
| #define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) |
Definition at line 90 of file stm32/f2/memorymap.h.
◆ TIM12_BASE
| #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) |
Definition at line 45 of file stm32/f2/memorymap.h.
◆ TIM13_BASE
| #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) |
Definition at line 46 of file stm32/f2/memorymap.h.
◆ TIM14_BASE
| #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) |
Definition at line 47 of file stm32/f2/memorymap.h.
◆ TIM1_BASE
| #define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) |
Definition at line 72 of file stm32/f2/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) |
Definition at line 39 of file stm32/f2/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) |
Definition at line 40 of file stm32/f2/memorymap.h.
◆ TIM4_BASE
| #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) |
Definition at line 41 of file stm32/f2/memorymap.h.
◆ TIM5_BASE
| #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) |
Definition at line 42 of file stm32/f2/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) |
Definition at line 43 of file stm32/f2/memorymap.h.
◆ TIM7_BASE
| #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) |
Definition at line 44 of file stm32/f2/memorymap.h.
◆ TIM8_BASE
| #define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) |
Definition at line 73 of file stm32/f2/memorymap.h.
◆ TIM9_BASE
| #define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) |
Definition at line 88 of file stm32/f2/memorymap.h.
◆ UART4_BASE
| #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) |
Definition at line 58 of file stm32/f2/memorymap.h.
◆ UART5_BASE
| #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) |
Definition at line 59 of file stm32/f2/memorymap.h.
◆ USART1_BASE
| #define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) |
Definition at line 75 of file stm32/f2/memorymap.h.
◆ USART2_BASE
| #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) |
Definition at line 56 of file stm32/f2/memorymap.h.
◆ USART3_BASE
| #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) |
Definition at line 57 of file stm32/f2/memorymap.h.
◆ USART6_BASE
| #define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) |
Definition at line 76 of file stm32/f2/memorymap.h.
◆ USB_OTG_FS_BASE
| #define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) |
Definition at line 119 of file stm32/f2/memorymap.h.
◆ USB_OTG_HS_BASE
| #define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) |
Definition at line 115 of file stm32/f2/memorymap.h.
◆ WWDG_BASE
| #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) |
Definition at line 50 of file stm32/f2/memorymap.h.
