libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
f4/rcc.h
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1 /** @defgroup rcc_defines RCC Defines
2  *
3  * @brief <b>Defined Constants and Types for the STM32F4xx Reset and Clock
4  * Control</b>
5  *
6  * @ingroup STM32F4xx_defines
7  *
8  * @version 1.0.0
9  *
10  * @author @htmlonly &copy; @endhtmlonly 2009
11  * Federico Ruiz-Ugalde <memeruiz at gmail dot com>
12  * @author @htmlonly &copy; @endhtmlonly 2009
13  * Uwe Hermann <uwe@hermann-uwe.de>
14  * @author @htmlonly &copy; @endhtmlonly 2011
15  * Fergus Noble <fergusnoble@gmail.com>
16  * @author @htmlonly &copy; @endhtmlonly 2011
17  * Stephen Caudle <scaudle@doceme.com>
18  *
19  * @date 18 August 2012
20  *
21  * LGPL License Terms @ref lgpl_license
22  */
23 /*
24  * This file is part of the libopencm3 project.
25  *
26  * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
27  * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
28  * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
29  * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
30  *
31  * This library is free software: you can redistribute it and/or modify
32  * it under the terms of the GNU Lesser General Public License as published by
33  * the Free Software Foundation, either version 3 of the License, or
34  * (at your option) any later version.
35  *
36  * This library is distributed in the hope that it will be useful,
37  * but WITHOUT ANY WARRANTY; without even the implied warranty of
38  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39  * GNU Lesser General Public License for more details.
40  *
41  * You should have received a copy of the GNU Lesser General Public License
42  * along with this library. If not, see <http://www.gnu.org/licenses/>.
43  */
44 /**@{*/
45 
46 #ifndef LIBOPENCM3_RCC_H
47 #define LIBOPENCM3_RCC_H
48 
49 #include <libopencm3/stm32/pwr.h>
50 
51 /** @defgroup rcc_registers RCC Registers
52  * @brief Reset / Clock Control Registers
53 @{*/
54 /** Clock control register */
55 #define RCC_CR MMIO32(RCC_BASE + 0x00)
56 /** PLL Configuration register */
57 #define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)
58 /** Clock Configuration register */
59 #define RCC_CFGR MMIO32(RCC_BASE + 0x08)
60 /** Clock interrupt register */
61 #define RCC_CIR MMIO32(RCC_BASE + 0x0c)
62 /** AHB1 peripheral reset register */
63 #define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
64 /** AHB2 peripheral reset register */
65 #define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
66 /** AHB3 peripheral reset register */
67 #define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
68 /* RCC_BASE + 0x1c Reserved */
69 /** APB1 peripheral reset register */
70 #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
71 /** APB2 peripheral reset register */
72 #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
73 /* RCC_BASE + 0x28 Reserved */
74 /* RCC_BASE + 0x2c Reserved */
75 /** AHB1 peripheral enable register */
76 #define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
77 /** AHB2 peripheral enable register */
78 #define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
79 /** AHB3 peripheral enable register */
80 #define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
81 /* RCC_BASE + 0x3c Reserved */
82 /** APB1 peripheral enable register */
83 #define RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
84 /** APB2 peripheral enable register */
85 #define RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
86 /* RCC_BASE + 0x48 Reserved */
87 /* RCC_BASE + 0x4c Reserved */
88 /** AHB1 peripheral enable in low power register */
89 #define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
90 /** AHB2 peripheral enable in low power register */
91 #define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
92 /** AHB3 peripheral enable in low power register */
93 #define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
94 /* RCC_BASE + 0x5c Reserved */
95 /** APB1 peripheral enable in low power register */
96 #define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
97 /** APB2 peripheral enable in low power register */
98 #define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
99 /* RCC_BASE + 0x68 Reserved */
100 /* RCC_BASE + 0x6c Reserved */
101 /** Backup Domain control register */
102 #define RCC_BDCR MMIO32(RCC_BASE + 0x70)
103 /** Clock control and status register */
104 #define RCC_CSR MMIO32(RCC_BASE + 0x74)
105 /* RCC_BASE + 0x78 Reserved */
106 /* RCC_BASE + 0x7c Reserved */
107 /** Spread spectrum clock generation register */
108 #define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
109 /** PLLI2S configuration register */
110 #define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
111 /** PLLSAI configuration register */
112 #define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)
113 /** Dedicated clocks configuration register */
114 #define RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)
115 /** RCC clocks gated enable register */
116 #define RCC_CKGATENR MMIO32(RCC_BASE + 0x90)
117 /** RCC Dedicated Clocks Configuration Register 2 */
118 #define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94)
119 /**@}*/
120 
121 /** @defgroup rcc_cr_values RCC_CR values
122  * @ingroup rcc_registers
123  * @brief Clock Control register values
124 @{*/
125 #define RCC_CR_PLLSAIRDY (1 << 29)
126 #define RCC_CR_PLLSAION (1 << 28)
127 #define RCC_CR_PLLI2SRDY (1 << 27)
128 #define RCC_CR_PLLI2SON (1 << 26)
129 #define RCC_CR_PLLRDY (1 << 25)
130 #define RCC_CR_PLLON (1 << 24)
131 #define RCC_CR_CSSON (1 << 19)
132 #define RCC_CR_HSEBYP (1 << 18)
133 #define RCC_CR_HSERDY (1 << 17)
134 #define RCC_CR_HSEON (1 << 16)
135 /* HSICAL: [15:8] */
136 /* HSITRIM: [7:3] */
137 #define RCC_CR_HSITRIM_SHIFT 3
138 #define RCC_CR_HSITRIM_MASK 0x1f
139 #define RCC_CR_HSIRDY (1 << 1)
140 #define RCC_CR_HSION (1 << 0)
141 /**@}*/
142 
143 /** @defgroup rcc_pllcfgr_values RCC_PLLCFGR values
144  * @ingroup rcc_registers
145  * @brief PLL Configuration register values
146 @{*/
147 /* PLLR: [30:28] */
148 #define RCC_PLLCFGR_PLLR_SHIFT 28
149 #define RCC_PLLCFGR_PLLR_MASK 0x7
150 /* PLLQ: [27:24] */
151 #define RCC_PLLCFGR_PLLQ_SHIFT 24
152 #define RCC_PLLCFGR_PLLQ_MASK 0xf
153 #define RCC_PLLCFGR_PLLSRC (1 << 22)
154 /* PLLP: [17:16] */
155 #define RCC_PLLCFGR_PLLP_SHIFT 16
156 #define RCC_PLLCFGR_PLLP_MASK 0x3
157 /* PLLN: [14:6] */
158 #define RCC_PLLCFGR_PLLN_SHIFT 6
159 #define RCC_PLLCFGR_PLLN_MASK 0x1ff
160 /* PLLM: [5:0] */
161 #define RCC_PLLCFGR_PLLM_SHIFT 0
162 #define RCC_PLLCFGR_PLLM_MASK 0x3f
163 /**@}*/
164 
165 /** @defgroup rcc_cfgr_values RCC_CFGR values
166  * @ingroup rcc_registers
167  * @brief Clock Configuration register values
168 @{*/
169 /* MCO2: Microcontroller clock output 2 */
170 #define RCC_CFGR_MCO2_SHIFT 30
171 #define RCC_CFGR_MCO2_MASK 0x3
172 #define RCC_CFGR_MCO2_SYSCLK 0x0
173 #define RCC_CFGR_MCO2_PLLI2S 0x1
174 #define RCC_CFGR_MCO2_HSE 0x2
175 #define RCC_CFGR_MCO2_PLL 0x3
176 
177 /* MCO1/2PRE: MCO Prescalers */
178 #define RCC_CFGR_MCO2PRE_SHIFT 27
179 #define RCC_CFGR_MCO2PRE_MASK 0x7
180 #define RCC_CFGR_MCO1PRE_SHIFT 24
181 #define RCC_CFGR_MCO1PRE_MASK 0x7
182 #define RCC_CFGR_MCOPRE_DIV_NONE 0x0
183 #define RCC_CFGR_MCOPRE_DIV_2 0x4
184 #define RCC_CFGR_MCOPRE_DIV_3 0x5
185 #define RCC_CFGR_MCOPRE_DIV_4 0x6
186 #define RCC_CFGR_MCOPRE_DIV_5 0x7
187 
188 /* PLLSRC: PLL entry clock source */
189 #define RCC_CFGR_PLLSRC_HSI_CLK 0x0
190 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1
191 
192 /* I2SSRC: I2S clock selection */
193 #define RCC_CFGR_I2SSRC (1 << 23)
194 
195 /* MCO1: Microcontroller clock output 1 */
196 #define RCC_CFGR_MCO1_SHIFT 21
197 #define RCC_CFGR_MCO1_MASK 0x3
198 #define RCC_CFGR_MCO1_HSI 0x0
199 #define RCC_CFGR_MCO1_LSE 0x1
200 #define RCC_CFGR_MCO1_HSE 0x2
201 #define RCC_CFGR_MCO1_PLL 0x3
202 #define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT
203 #define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK
204 
205 /* RTCPRE: HSE division factor for RTC clock */
206 #define RCC_CFGR_RTCPRE_SHIFT 16
207 #define RCC_CFGR_RTCPRE_MASK 0x1f
208 
209 #define RCC_CFGR_PPRE2_SHIFT 13
210 #define RCC_CFGR_PPRE2_MASK 0x7
211 #define RCC_CFGR_PPRE1_SHIFT 10
212 #define RCC_CFGR_PPRE1_MASK 0x7
213 /** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors
214  * These can be used for both APB1 and APB2 prescaling
215  * @{
216  */
217 #define RCC_CFGR_PPRE_NODIV 0x0
218 #define RCC_CFGR_PPRE_DIV2 0x4
219 #define RCC_CFGR_PPRE_DIV4 0x5
220 #define RCC_CFGR_PPRE_DIV8 0x6
221 #define RCC_CFGR_PPRE_DIV16 0x7
222 /**@}*/
223 
224 #define RCC_CFGR_HPRE_SHIFT 4
225 #define RCC_CFGR_HPRE_MASK 0xf
226 /** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors
227 @{*/
228 #define RCC_CFGR_HPRE_NODIV 0x0
229 #define RCC_CFGR_HPRE_DIV2 (0x8 + 0)
230 #define RCC_CFGR_HPRE_DIV4 (0x8 + 1)
231 #define RCC_CFGR_HPRE_DIV8 (0x8 + 2)
232 #define RCC_CFGR_HPRE_DIV16 (0x8 + 3)
233 #define RCC_CFGR_HPRE_DIV64 (0x8 + 4)
234 #define RCC_CFGR_HPRE_DIV128 (0x8 + 5)
235 #define RCC_CFGR_HPRE_DIV256 (0x8 + 6)
236 #define RCC_CFGR_HPRE_DIV512 (0x8 + 7)
237 /**@}*/
238 
239 /* SWS: System clock switch status */
240 #define RCC_CFGR_SWS_SHIFT 2
241 #define RCC_CFGR_SWS_MASK 0x3
242 #define RCC_CFGR_SWS_HSI 0x0
243 #define RCC_CFGR_SWS_HSE 0x1
244 #define RCC_CFGR_SWS_PLL 0x2
245 
246 /* SW: System clock switch */
247 #define RCC_CFGR_SW_SHIFT 0
248 #define RCC_CFGR_SW_HSI 0x0
249 #define RCC_CFGR_SW_HSE 0x1
250 #define RCC_CFGR_SW_PLL 0x2
251 /**@}*/
252 
253 /** Older compatible definitions to ease migration
254  * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers
255  * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families
256  * @{
257  */
258 #define RCC_CFGR_PPRE_DIV_NONE 0x0
259 #define RCC_CFGR_PPRE_DIV_2 0x4
260 #define RCC_CFGR_PPRE_DIV_4 0x5
261 #define RCC_CFGR_PPRE_DIV_8 0x6
262 #define RCC_CFGR_PPRE_DIV_16 0x7
263 
264 #define RCC_CFGR_HPRE_DIV_NONE 0x0
265 #define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
266 #define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
267 #define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
268 #define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
269 #define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
270 #define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
271 #define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
272 #define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
273 /**@}*/
274 
275 /** @defgroup rcc_cir_values RCC_CIR values
276  * @ingroup rcc_registers
277  * @brief Clock Interrupt register values
278 @{*/
279 /* Clock security system interrupt clear bit */
280 #define RCC_CIR_CSSC (1 << 23)
281 
282 /* OSC ready interrupt clear bits */
283 #define RCC_CIR_PLLSAIRDYC (1 << 22)
284 #define RCC_CIR_PLLI2SRDYC (1 << 21)
285 #define RCC_CIR_PLLRDYC (1 << 20)
286 #define RCC_CIR_HSERDYC (1 << 19)
287 #define RCC_CIR_HSIRDYC (1 << 18)
288 #define RCC_CIR_LSERDYC (1 << 17)
289 #define RCC_CIR_LSIRDYC (1 << 16)
290 
291 /* OSC ready interrupt enable bits */
292 #define RCC_CIR_PLLSAIRDYIE (1 << 14)
293 #define RCC_CIR_PLLI2SRDYIE (1 << 13)
294 #define RCC_CIR_PLLRDYIE (1 << 12)
295 #define RCC_CIR_HSERDYIE (1 << 11)
296 #define RCC_CIR_HSIRDYIE (1 << 10)
297 #define RCC_CIR_LSERDYIE (1 << 9)
298 #define RCC_CIR_LSIRDYIE (1 << 8)
299 
300 /* Clock security system interrupt flag bit */
301 #define RCC_CIR_CSSF (1 << 7)
302 
303 /* OSC ready interrupt flag bits */
304 #define RCC_CIR_PLLSAIRDYF (1 << 6)
305 #define RCC_CIR_PLLI2SRDYF (1 << 5)
306 #define RCC_CIR_PLLRDYF (1 << 4)
307 #define RCC_CIR_HSERDYF (1 << 3)
308 #define RCC_CIR_HSIRDYF (1 << 2)
309 #define RCC_CIR_LSERDYF (1 << 1)
310 #define RCC_CIR_LSIRDYF (1 << 0)
311 /**@}*/
312 
313 /** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set)
314 @{*/
315 /** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values
316 @{*/
317 #define RCC_AHB1RSTR_OTGHSRST (1 << 29)
318 #define RCC_AHB1RSTR_ETHMACRST (1 << 25)
319 #define RCC_AHB1RSTR_DMA2DRST (1 << 23)
320 #define RCC_AHB1RSTR_DMA2RST (1 << 22)
321 #define RCC_AHB1RSTR_DMA1RST (1 << 21)
322 #define RCC_AHB1RSTR_CRCRST (1 << 12)
323 #define RCC_AHB1RSTR_GPIOKRST (1 << 10)
324 #define RCC_AHB1RSTR_GPIOJRST (1 << 9)
325 #define RCC_AHB1RSTR_GPIOIRST (1 << 8)
326 #define RCC_AHB1RSTR_GPIOHRST (1 << 7)
327 #define RCC_AHB1RSTR_GPIOGRST (1 << 6)
328 #define RCC_AHB1RSTR_GPIOFRST (1 << 5)
329 #define RCC_AHB1RSTR_GPIOERST (1 << 4)
330 #define RCC_AHB1RSTR_GPIODRST (1 << 3)
331 #define RCC_AHB1RSTR_GPIOCRST (1 << 2)
332 #define RCC_AHB1RSTR_GPIOBRST (1 << 1)
333 #define RCC_AHB1RSTR_GPIOARST (1 << 0)
334 /**@}*/
335 
336 /** @addtogroup deprecated_201802_rcc Deprecated 2018
337  * @deprecated replace zzz_IOPxRST with zzz_GPIOxRST
338  * @{
339  */
340 #define RCC_AHB1RSTR_IOPKRST RCC_AHB1RSTR_GPIOKRST
341 #define RCC_AHB1RSTR_IOPJRST RCC_AHB1RSTR_GPIOJRST
342 #define RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST
343 #define RCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRST
344 #define RCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRST
345 #define RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRST
346 #define RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERST
347 #define RCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRST
348 #define RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRST
349 #define RCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRST
350 #define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST
351 /**@}*/
352 
353 /** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values
354 @{*/
355 #define RCC_AHB2RSTR_OTGFSRST (1 << 7)
356 #define RCC_AHB2RSTR_RNGRST (1 << 6)
357 #define RCC_AHB2RSTR_HASHRST (1 << 5)
358 #define RCC_AHB2RSTR_CRYPRST (1 << 4)
359 #define RCC_AHB2RSTR_DCMIRST (1 << 0)
360 /**@}*/
361 
362 /** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values
363 @{*/
364 #define RCC_AHB3RSTR_QSPIRST (1 << 1)
365 #define RCC_AHB3RSTR_FSMCRST (1 << 0)
366 /**@}*/
367 /**@}*/
368 
369 /** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
370 @{*/
371 #define RCC_APB1RSTR_UART8RST (1 << 31)
372 #define RCC_APB1RSTR_UART7RST (1 << 30)
373 #define RCC_APB1RSTR_DACRST (1 << 29)
374 #define RCC_APB1RSTR_PWRRST (1 << 28)
375 #define RCC_APB1RSTR_CAN2RST (1 << 26)
376 #define RCC_APB1RSTR_CAN1RST (1 << 25)
377 #define RCC_APB1RSTR_I2C3RST (1 << 23)
378 #define RCC_APB1RSTR_I2C2RST (1 << 22)
379 #define RCC_APB1RSTR_I2C1RST (1 << 21)
380 #define RCC_APB1RSTR_UART5RST (1 << 20)
381 #define RCC_APB1RSTR_UART4RST (1 << 19)
382 #define RCC_APB1RSTR_USART3RST (1 << 18)
383 #define RCC_APB1RSTR_USART2RST (1 << 17)
384 #define RCC_APB1RSTR_SPI3RST (1 << 15)
385 #define RCC_APB1RSTR_SPI2RST (1 << 14)
386 #define RCC_APB1RSTR_WWDGRST (1 << 11)
387 #define RCC_APB1RSTR_TIM14RST (1 << 8)
388 #define RCC_APB1RSTR_TIM13RST (1 << 7)
389 #define RCC_APB1RSTR_TIM12RST (1 << 6)
390 #define RCC_APB1RSTR_TIM7RST (1 << 5)
391 #define RCC_APB1RSTR_TIM6RST (1 << 4)
392 #define RCC_APB1RSTR_TIM5RST (1 << 3)
393 #define RCC_APB1RSTR_TIM4RST (1 << 2)
394 #define RCC_APB1RSTR_TIM3RST (1 << 1)
395 #define RCC_APB1RSTR_TIM2RST (1 << 0)
396 /**@}*/
397 
398 /** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
399 @{*/
400 #define RCC_APB2RSTR_DSIRST (1 << 27)
401 #define RCC_APB2RSTR_LTDCRST (1 << 26)
402 #define RCC_APB2RSTR_SAI1RST (1 << 22)
403 #define RCC_APB2RSTR_SPI6RST (1 << 21)
404 #define RCC_APB2RSTR_SPI5RST (1 << 20)
405 #define RCC_APB2RSTR_TIM11RST (1 << 18)
406 #define RCC_APB2RSTR_TIM10RST (1 << 17)
407 #define RCC_APB2RSTR_TIM9RST (1 << 16)
408 #define RCC_APB2RSTR_SYSCFGRST (1 << 14)
409 #define RCC_APB2RSTR_SPI4RST (1 << 13)
410 #define RCC_APB2RSTR_SPI1RST (1 << 12)
411 #define RCC_APB2RSTR_SDIORST (1 << 11)
412 #define RCC_APB2RSTR_ADCRST (1 << 8)
413 #define RCC_APB2RSTR_USART6RST (1 << 5)
414 #define RCC_APB2RSTR_USART1RST (1 << 4)
415 #define RCC_APB2RSTR_TIM8RST (1 << 1)
416 #define RCC_APB2RSTR_TIM1RST (1 << 0)
417 /**@}*/
418 
419 /** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set)
420 @{*/
421 /** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values
422 @{*/
423 #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30)
424 #define RCC_AHB1ENR_OTGHSEN (1 << 29)
425 #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28)
426 #define RCC_AHB1ENR_ETHMACRXEN (1 << 27)
427 #define RCC_AHB1ENR_ETHMACTXEN (1 << 26)
428 #define RCC_AHB1ENR_ETHMACEN (1 << 25)
429 #define RCC_AHB1ENR_DMA2DEN (1 << 23)
430 #define RCC_AHB1ENR_DMA2EN (1 << 22)
431 #define RCC_AHB1ENR_DMA1EN (1 << 21)
432 #define RCC_AHB1ENR_CCMDATARAMEN (1 << 20)
433 #define RCC_AHB1ENR_BKPSRAMEN (1 << 18)
434 #define RCC_AHB1ENR_CRCEN (1 << 12)
435 #define RCC_AHB1ENR_GPIOKEN (1 << 10)
436 #define RCC_AHB1ENR_GPIOJEN (1 << 9)
437 #define RCC_AHB1ENR_GPIOIEN (1 << 8)
438 #define RCC_AHB1ENR_GPIOHEN (1 << 7)
439 #define RCC_AHB1ENR_GPIOGEN (1 << 6)
440 #define RCC_AHB1ENR_GPIOFEN (1 << 5)
441 #define RCC_AHB1ENR_GPIOEEN (1 << 4)
442 #define RCC_AHB1ENR_GPIODEN (1 << 3)
443 #define RCC_AHB1ENR_GPIOCEN (1 << 2)
444 #define RCC_AHB1ENR_GPIOBEN (1 << 1)
445 #define RCC_AHB1ENR_GPIOAEN (1 << 0)
446 /**@}*/
447 
448 /** @addtogroup deprecated_201802_rcc Deprecated 2018
449  * @deprecated replace zzz_IOPxEN with zzz_GPIOxEN
450  * @{
451  */
452 #define RCC_AHB1ENR_IOPKEN RCC_AHB1ENR_GPIOKEN
453 #define RCC_AHB1ENR_IOPJEN RCC_AHB1ENR_GPIOJEN
454 #define RCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIEN
455 #define RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHEN
456 #define RCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGEN
457 #define RCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFEN
458 #define RCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEEN
459 #define RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODEN
460 #define RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCEN
461 #define RCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBEN
462 #define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN
463 /**@}*/
464 
465 /** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values
466 @{*/
467 #define RCC_AHB2ENR_OTGFSEN (1 << 7)
468 #define RCC_AHB2ENR_RNGEN (1 << 6)
469 #define RCC_AHB2ENR_HASHEN (1 << 5)
470 #define RCC_AHB2ENR_CRYPEN (1 << 4)
471 #define RCC_AHB2ENR_DCMIEN (1 << 0)
472 /**@}*/
473 
474 /** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values
475 @{*/
476 #define RCC_AHB3ENR_QSPIEN (1 << 1)
477 #define RCC_AHB3ENR_FSMCEN (1 << 0)
478 /* Alternate now that F429 has DRAM controller as well */
479 #define RCC_AHB3ENR_FMCEN (1 << 0)
480 /**@}*/
481 /**@}*/
482 
483 /** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
484 @{*/
485 #define RCC_APB1ENR_UART8EN (1 << 31)
486 #define RCC_APB1ENR_UART7EN (1 << 30)
487 #define RCC_APB1ENR_DACEN (1 << 29)
488 #define RCC_APB1ENR_PWREN (1 << 28)
489 #define RCC_APB1ENR_CAN2EN (1 << 26)
490 #define RCC_APB1ENR_CAN1EN (1 << 25)
491 #define RCC_APB1ENR_I2C3EN (1 << 23)
492 #define RCC_APB1ENR_I2C2EN (1 << 22)
493 #define RCC_APB1ENR_I2C1EN (1 << 21)
494 #define RCC_APB1ENR_UART5EN (1 << 20)
495 #define RCC_APB1ENR_UART4EN (1 << 19)
496 #define RCC_APB1ENR_USART3EN (1 << 18)
497 #define RCC_APB1ENR_USART2EN (1 << 17)
498 #define RCC_APB1ENR_SPI3EN (1 << 15)
499 #define RCC_APB1ENR_SPI2EN (1 << 14)
500 #define RCC_APB1ENR_WWDGEN (1 << 11)
501 #define RCC_APB1ENR_TIM14EN (1 << 8)
502 #define RCC_APB1ENR_TIM13EN (1 << 7)
503 #define RCC_APB1ENR_TIM12EN (1 << 6)
504 #define RCC_APB1ENR_TIM7EN (1 << 5)
505 #define RCC_APB1ENR_TIM6EN (1 << 4)
506 #define RCC_APB1ENR_TIM5EN (1 << 3)
507 #define RCC_APB1ENR_TIM4EN (1 << 2)
508 #define RCC_APB1ENR_TIM3EN (1 << 1)
509 #define RCC_APB1ENR_TIM2EN (1 << 0)
510 /**@}*/
511 
512 /** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
513 @{*/
514 #define RCC_APB2ENR_DSIEN (1 << 27)
515 #define RCC_APB2ENR_LTDCEN (1 << 26)
516 #define RCC_APB2ENR_SAI1EN (1 << 22)
517 #define RCC_APB2ENR_SPI6EN (1 << 21)
518 #define RCC_APB2ENR_SPI5EN (1 << 20)
519 #define RCC_APB2ENR_TIM11EN (1 << 18)
520 #define RCC_APB2ENR_TIM10EN (1 << 17)
521 #define RCC_APB2ENR_TIM9EN (1 << 16)
522 #define RCC_APB2ENR_SYSCFGEN (1 << 14)
523 #define RCC_APB2ENR_SPI4EN (1 << 13)
524 #define RCC_APB2ENR_SPI1EN (1 << 12)
525 #define RCC_APB2ENR_SDIOEN (1 << 11)
526 #define RCC_APB2ENR_ADC3EN (1 << 10)
527 #define RCC_APB2ENR_ADC2EN (1 << 9)
528 #define RCC_APB2ENR_ADC1EN (1 << 8)
529 #define RCC_APB2ENR_USART6EN (1 << 5)
530 #define RCC_APB2ENR_USART1EN (1 << 4)
531 #define RCC_APB2ENR_TIM8EN (1 << 1)
532 #define RCC_APB2ENR_TIM1EN (1 << 0)
533 /**@}*/
534 
535 /* --- RCC_AHB1LPENR values ------------------------------------------------- */
536 
537 #define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)
538 #define RCC_AHB1LPENR_OTGHSLPEN (1 << 29)
539 #define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)
540 #define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)
541 #define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)
542 #define RCC_AHB1LPENR_ETHMACLPEN (1 << 25)
543 #define RCC_AHB1LPENR_DMA2DLPEN (1 << 23)
544 #define RCC_AHB1LPENR_DMA2LPEN (1 << 22)
545 #define RCC_AHB1LPENR_DMA1LPEN (1 << 21)
546 #define RCC_AHB1LPENR_SRAM3LPEN (1 << 19)
547 #define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)
548 #define RCC_AHB1LPENR_SRAM2LPEN (1 << 17)
549 #define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
550 #define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
551 #define RCC_AHB1LPENR_CRCLPEN (1 << 12)
552 #define RCC_AHB1LPENR_GPIOKLPEN (1 << 10)
553 #define RCC_AHB1LPENR_GPIOJLPEN (1 << 9)
554 #define RCC_AHB1LPENR_GPIOILPEN (1 << 8)
555 #define RCC_AHB1LPENR_GPIOHLPEN (1 << 7)
556 #define RCC_AHB1LPENR_GPIOGLPEN (1 << 6)
557 #define RCC_AHB1LPENR_GPIOFLPEN (1 << 5)
558 #define RCC_AHB1LPENR_GPIOELPEN (1 << 4)
559 #define RCC_AHB1LPENR_GPIODLPEN (1 << 3)
560 #define RCC_AHB1LPENR_GPIOCLPEN (1 << 2)
561 #define RCC_AHB1LPENR_GPIOBLPEN (1 << 1)
562 #define RCC_AHB1LPENR_GPIOALPEN (1 << 0)
563 
564 /** @addtogroup deprecated_201802_rcc Deprecated 2018
565  * @deprecated replace zzz_IOPxLPEN with zzz_GPIOxLPEN
566  * @{
567  */
568 #define RCC_AHB1LPENR_IOPKLPEN RCC_AHB1LPENR_GPIOKLPEN
569 #define RCC_AHB1LPENR_IOPJLPEN RCC_AHB1LPENR_GPIOJLPEN
570 #define RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPEN
571 #define RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPEN
572 #define RCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN
573 #define RCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN
574 #define RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPEN
575 #define RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPEN
576 #define RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPEN
577 #define RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPEN
578 #define RCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPEN
579 /**@}*/
580 
581 /* --- RCC_AHB2LPENR values ------------------------------------------------- */
582 
583 #define RCC_AHB2LPENR_OTGFSLPEN (1 << 7)
584 #define RCC_AHB2LPENR_RNGLPEN (1 << 6)
585 #define RCC_AHB2LPENR_HASHLPEN (1 << 5)
586 #define RCC_AHB2LPENR_CRYPLPEN (1 << 4)
587 #define RCC_AHB2LPENR_DCMILPEN (1 << 0)
588 
589 /* --- RCC_AHB3LPENR values ------------------------------------------------- */
590 
591 #define RCC_AHB3LPENR_QSPIEN (1 << 1)
592 #define RCC_AHB3LPENR_FSMCLPEN (1 << 0)
593 #define RCC_AHB3LPENR_FMCLPEN (1 << 0)
594 
595 /* --- RCC_APB1LPENR values ------------------------------------------------- */
596 
597 /** @defgroup rcc_apblpenr_en RCC_APBxLPENR enable values (full set)
598 @{*/
599 #define RCC_APB1LPENR_UART8EN (1 << 31)
600 #define RCC_APB1LPENR_UART7EN (1 << 30)
601 #define RCC_APB1LPENR_DACLPEN (1 << 29)
602 #define RCC_APB1LPENR_PWRLPEN (1 << 28)
603 #define RCC_APB1LPENR_CAN2LPEN (1 << 26)
604 #define RCC_APB1LPENR_CAN1LPEN (1 << 25)
605 #define RCC_APB1LPENR_I2C3LPEN (1 << 23)
606 #define RCC_APB1LPENR_I2C2LPEN (1 << 22)
607 #define RCC_APB1LPENR_I2C1LPEN (1 << 21)
608 #define RCC_APB1LPENR_UART5LPEN (1 << 20)
609 #define RCC_APB1LPENR_UART4LPEN (1 << 19)
610 #define RCC_APB1LPENR_USART3LPEN (1 << 18)
611 #define RCC_APB1LPENR_USART2LPEN (1 << 17)
612 #define RCC_APB1LPENR_SPI3LPEN (1 << 15)
613 #define RCC_APB1LPENR_SPI2LPEN (1 << 14)
614 #define RCC_APB1LPENR_WWDGLPEN (1 << 11)
615 #define RCC_APB1LPENR_TIM14LPEN (1 << 8)
616 #define RCC_APB1LPENR_TIM13LPEN (1 << 7)
617 #define RCC_APB1LPENR_TIM12LPEN (1 << 6)
618 #define RCC_APB1LPENR_TIM7LPEN (1 << 5)
619 #define RCC_APB1LPENR_TIM6LPEN (1 << 4)
620 #define RCC_APB1LPENR_TIM5LPEN (1 << 3)
621 #define RCC_APB1LPENR_TIM4LPEN (1 << 2)
622 #define RCC_APB1LPENR_TIM3LPEN (1 << 1)
623 #define RCC_APB1LPENR_TIM2LPEN (1 << 0)
624 
625 /* --- RCC_APB2LPENR values ------------------------------------------------- */
626 
627 #define RCC_APB2LPENR_DSILPEN (1 << 27)
628 #define RCC_APB2LPENR_LTDCLPEN (1 << 26)
629 #define RCC_APB2LPENR_SAI1LPEN (1 << 22)
630 #define RCC_APB2LPENR_SPI6LPEN (1 << 21)
631 #define RCC_APB2LPENR_SPI5LPEN (1 << 20)
632 #define RCC_APB2LPENR_TIM11LPEN (1 << 18)
633 #define RCC_APB2LPENR_TIM10LPEN (1 << 17)
634 #define RCC_APB2LPENR_TIM9LPEN (1 << 16)
635 #define RCC_APB2LPENR_SYSCFGLPEN (1 << 14)
636 #define RCC_APB2LPENR_SPI1LPEN (1 << 12)
637 #define RCC_APB2LPENR_SDIOLPEN (1 << 11)
638 #define RCC_APB2LPENR_ADC3LPEN (1 << 10)
639 #define RCC_APB2LPENR_ADC2LPEN (1 << 9)
640 #define RCC_APB2LPENR_ADC1LPEN (1 << 8)
641 #define RCC_APB2LPENR_USART6LPEN (1 << 5)
642 #define RCC_APB2LPENR_USART1LPEN (1 << 4)
643 #define RCC_APB2LPENR_TIM8LPEN (1 << 1)
644 #define RCC_APB2LPENR_TIM1LPEN (1 << 0)
645 /**@}*/
646 
647 /** @defgroup rcc_bdcr_values RCC_BDCR values
648  * @ingroup rcc_registers
649  * @brief Backup Domain control register values
650 @{*/
651 #define RCC_BDCR_BDRST (1 << 16)
652 #define RCC_BDCR_RTCEN (1 << 15)
653 /* RCC_BDCR[9:8]: RTCSEL */
654 #define RCC_BDCR_RTCSEL_SHIFT 8
655 #define RCC_BDCR_RTCSEL_MASK 0x3
656 #define RCC_BDCR_RTCSEL_NONE 0
657 #define RCC_BDCR_RTCSEL_LSE 1
658 #define RCC_BDCR_RTCSEL_LSI 2
659 #define RCC_BDCR_RTCSEL_HSE 3
660 #define RCC_BDCR_LSEMOD (1 << 3)
661 #define RCC_BDCR_LSEBYP (1 << 2)
662 #define RCC_BDCR_LSERDY (1 << 1)
663 #define RCC_BDCR_LSEON (1 << 0)
664 /**@}*/
665 
666 /** @defgroup rcc_csr_values RCC_CSR values
667  * @ingroup rcc_registers
668  * @brief Clock control and status register values
669 @{*/
670 #define RCC_CSR_LPWRRSTF (1 << 31)
671 #define RCC_CSR_WWDGRSTF (1 << 30)
672 #define RCC_CSR_IWDGRSTF (1 << 29)
673 #define RCC_CSR_SFTRSTF (1 << 28)
674 #define RCC_CSR_PORRSTF (1 << 27)
675 #define RCC_CSR_PINRSTF (1 << 26)
676 #define RCC_CSR_BORRSTF (1 << 25)
677 #define RCC_CSR_RMVF (1 << 24)
678 #define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
679  RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
680  RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)
681 #define RCC_CSR_LSIRDY (1 << 1)
682 #define RCC_CSR_LSION (1 << 0)
683 /**@}*/
684 
685 /** @defgroup rcc_sscgr_values RCC_SSCGR values
686  * @ingroup rcc_registers
687  * @brief Spread spectrum clock generation register values
688 @{*/
689 /* PLL spread spectrum clock generation documented in Datasheet. */
690 
691 #define RCC_SSCGR_SSCGEN (1 << 31)
692 #define RCC_SSCGR_SPREADSEL (1 << 30)
693 /* RCC_SSCGR[27:13]: INCSTEP */
694 #define RCC_SSCGR_INCSTEP_SHIFT 13
695 #define RCC_SSCGR_INCSTEP_MASK 0x7fff
696 /* RCC_SSCGR[15:0]: MODPER */
697 #define RCC_SSCGR_MODPER_SHIFT 0
698 #define RCC_SSCGR_MODPER_MASK 0x1fff
699 /**@}*/
700 
701 /** @defgroup rcc_pllded_values RCC_PLLxxx/DCKy values
702  * @ingroup rcc_registers
703  * @brief PLL and other dedicated clock register values
704 @{*/
705 /* --- RCC_PLLI2SCFGR values ----------------------------------------------- */
706 
707 /* RCC_PLLI2SCFGR[30:28]: PLLI2SR */
708 #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28
709 #define RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7
710 /* RCC_PLLI2SCFGR[27:24] PLLI2SQ */
711 #define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24
712 #define RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf
713 /* RCC_PLLI2SCFGR[14:6]: PLLI2SN */
714 #define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
715 #define RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff
716 
717 /* --- RCC_PLLSAICFGR values ----------------------------------------------- */
718 
719 /* RCC_PLLSAICFGR[30:28]: PLLSAIR */
720 #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
721 #define RCC_PLLSAICFGR_PLLSAIR_MASK 0x7
722 
723 /* RCC_PLLSAICFGR[27:24]: PLLSAIQ */
724 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
725 #define RCC_PLLSAICFGR_PLLSAIQ_MASK 0xF
726 
727 /* RCC_PLLSAICFGR[18:16]: PLLSAIP */
728 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
729 #define RCC_PLLSAICFGR_PLLSAIP_MASK 0x3
730 /** @defgroup rcc_pllsaicfgr_pllsaip PLLSAICFGR PLLSAIP values
731 @ingroup rcc_defines
732 @{*/
733 #define RCC_PLLSAICFGR_PLLSAIP_DIV2 0x0
734 #define RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1
735 #define RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2
736 #define RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3
737 /**@}*/
738 
739 /* RCC_PLLSAICFGR[14:6]: PLLSAIN */
740 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
741 #define RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF
742 
743 
744 /* --- RCC_DCKCFGR values -------------------------------------------------- */
745 #define RCC_DCKCFGR_DSISEL (1 << 29)
746 #define RCC_DCKCFGR_SDMMCSEL (1 << 28)
747 #define RCC_DCKCFGR_48MSEL (1 << 27)
748 #define RCC_DCKCFGR_TIMPRE (1 << 24)
749 
750 #define RCC_DCKCFGR_SAI1BSRC_SHIFT 22
751 #define RCC_DCKCFGR_SAI1BSRC_MASK 0x3
752 
753 #define RCC_DCKCFGR_SAI1ASRC_SHIFT 20
754 #define RCC_DCKCFGR_SAI1ASRC_MASK 0x3
755 
756 /* Values for the BSRC and ASRC fields */
757 #define RCC_DCKCFGR_SAI1SRC_SAIQ 0x0
758 #define RCC_DCKCFGR_SAI1SRC_I2SQ 0x1
759 #define RCC_DCKCFGR_SAI1SRC_ALT 0x2
760 #define RCC_DCKCFGR_SAI1SRC_ERROR 0x3
761 
762 #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
763 #define RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3
764 #define RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0
765 #define RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1
766 #define RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2
767 #define RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3
768 
769 #define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8
770 #define RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f
771 
772 #define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0
773 #define RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f
774 /**@}*/
775 
776 /** @defgroup rcc_ckgatenr_values RCC_CKGATENR bits
777  * @ingroup rcc_registers
778  * @brief Allows to enable or disable the clock gating for the specified IPs.
779 @{*/
780 #define RCC_CKGATENR_EVTCL_CKEN (1<<7)
781 #define RCC_CKGATENR_RCC_CKEN (1<<6)
782 #define RCC_CKGATENR_FLITF_CKEN (1<<5)
783 #define RCC_CKGATENR_SRAM_CKEN (1<<4)
784 #define RCC_CKGATENR_SPARE_CKEN (1<<3)
785 #define RCC_CKGATENR_CM4DBG_CKEN (1<<2)
786 #define RCC_CKGATENR_AHB2APB2_CKEN (1<<1)
787 #define RCC_CKGATENR_AHB2APB1_CKEN (1<<0)
788 /**@}*/
789 
790 /* --- Variable definitions ------------------------------------------------ */
791 extern uint32_t rcc_ahb_frequency;
792 extern uint32_t rcc_apb1_frequency;
793 extern uint32_t rcc_apb2_frequency;
794 
795 /* --- Function prototypes ------------------------------------------------- */
796 
802 };
803 
805  uint8_t pllm;
806  uint16_t plln;
807  uint8_t pllp;
808  uint8_t pllq;
809  uint8_t pllr;
810  uint8_t pll_source;
811  uint32_t flash_config;
812  uint8_t hpre;
813  uint8_t ppre1;
814  uint8_t ppre2;
816  uint32_t ahb_frequency;
817  uint32_t apb1_frequency;
818  uint32_t apb2_frequency;
819 };
820 
826 
827 enum rcc_osc {
834  RCC_LSI
835 };
836 
837 #define _REG_BIT(base, bit) (((base) << 5) + (bit))
838 
840  /* AHB1 peripherals*/
841  RCC_GPIOA = _REG_BIT(0x30, 0),
842  RCC_GPIOB = _REG_BIT(0x30, 1),
843  RCC_GPIOC = _REG_BIT(0x30, 2),
844  RCC_GPIOD = _REG_BIT(0x30, 3),
845  RCC_GPIOE = _REG_BIT(0x30, 4),
846  RCC_GPIOF = _REG_BIT(0x30, 5),
847  RCC_GPIOG = _REG_BIT(0x30, 6),
848  RCC_GPIOH = _REG_BIT(0x30, 7),
849  RCC_GPIOI = _REG_BIT(0x30, 8),
850  RCC_GPIOJ = _REG_BIT(0x30, 9),
851  RCC_GPIOK = _REG_BIT(0x30, 10),
852  RCC_CRC = _REG_BIT(0x30, 12),
853  RCC_BKPSRAM = _REG_BIT(0x30, 18),
855  RCC_DMA1 = _REG_BIT(0x30, 21),
856  RCC_DMA2 = _REG_BIT(0x30, 22),
857  RCC_DMA2D = _REG_BIT(0x30, 23),
858  RCC_ETHMAC = _REG_BIT(0x30, 25),
859  RCC_ETHMACTX = _REG_BIT(0x30, 26),
860  RCC_ETHMACRX = _REG_BIT(0x30, 27),
861  RCC_ETHMACPTP = _REG_BIT(0x30, 28),
862  RCC_OTGHS = _REG_BIT(0x30, 29),
863  RCC_OTGHSULPI = _REG_BIT(0x30, 30),
864 
865  /* AHB2 peripherals */
866  RCC_DCMI = _REG_BIT(0x34, 0),
867  RCC_CRYP = _REG_BIT(0x34, 4),
868  RCC_HASH = _REG_BIT(0x34, 5),
869  RCC_RNG = _REG_BIT(0x34, 6),
870  RCC_OTGFS = _REG_BIT(0x34, 7),
871 
872  /* AHB3 peripherals */
873  RCC_FSMC = _REG_BIT(0x38, 0),
874  RCC_FMC = _REG_BIT(0x38, 0),
875  RCC_QUADSPI = _REG_BIT(0x38, 1),
876 
877  /* APB1 peripherals*/
878  RCC_TIM2 = _REG_BIT(0x40, 0),
879  RCC_TIM3 = _REG_BIT(0x40, 1),
880  RCC_TIM4 = _REG_BIT(0x40, 2),
881  RCC_TIM5 = _REG_BIT(0x40, 3),
882  RCC_TIM6 = _REG_BIT(0x40, 4),
883  RCC_TIM7 = _REG_BIT(0x40, 5),
884  RCC_TIM12 = _REG_BIT(0x40, 6),
885  RCC_TIM13 = _REG_BIT(0x40, 7),
886  RCC_TIM14 = _REG_BIT(0x40, 8),
887  RCC_WWDG = _REG_BIT(0x40, 11),
888  RCC_SPI2 = _REG_BIT(0x40, 14),
889  RCC_SPI3 = _REG_BIT(0x40, 15),
890  RCC_USART2 = _REG_BIT(0x40, 17),
891  RCC_USART3 = _REG_BIT(0x40, 18),
892  RCC_UART4 = _REG_BIT(0x40, 19),
893  RCC_UART5 = _REG_BIT(0x40, 20),
894  RCC_I2C1 = _REG_BIT(0x40, 21),
895  RCC_I2C2 = _REG_BIT(0x40, 22),
896  RCC_I2C3 = _REG_BIT(0x40, 23),
897  RCC_CAN1 = _REG_BIT(0x40, 25),
898  RCC_CAN2 = _REG_BIT(0x40, 26),
899  RCC_PWR = _REG_BIT(0x40, 28),
900  RCC_DAC = _REG_BIT(0x40, 29),
901  RCC_UART7 = _REG_BIT(0x40, 30),/* F2xx, F3xx */
902  RCC_UART8 = _REG_BIT(0x40, 31),/* F2xx, F3xx */
903 
904  /* APB2 peripherals */
905  RCC_TIM1 = _REG_BIT(0x44, 0),
906  RCC_TIM8 = _REG_BIT(0x44, 1),
907  RCC_USART1 = _REG_BIT(0x44, 4),
908  RCC_USART6 = _REG_BIT(0x44, 5),
909  RCC_ADC1 = _REG_BIT(0x44, 8),
910  RCC_ADC2 = _REG_BIT(0x44, 9),
911  RCC_ADC3 = _REG_BIT(0x44, 10),
912  RCC_SDIO = _REG_BIT(0x44, 11),
913  RCC_SPI1 = _REG_BIT(0x44, 12),
914  RCC_SPI4 = _REG_BIT(0x44, 13),/* F2xx, F3xx */
915  RCC_SYSCFG = _REG_BIT(0x44, 14),
916  RCC_TIM9 = _REG_BIT(0x44, 16),
917  RCC_TIM10 = _REG_BIT(0x44, 17),
918  RCC_TIM11 = _REG_BIT(0x44, 18),
919  RCC_SPI5 = _REG_BIT(0x44, 20),/* F2xx, F3xx */
920  RCC_SPI6 = _REG_BIT(0x44, 21),/* F2xx, F3xx */
921  RCC_SAI1EN = _REG_BIT(0x44, 22),/* F42x, F43x */
922  RCC_LTDC = _REG_BIT(0x44, 26),/* F42x, F43x */
923  RCC_DSI = _REG_BIT(0x44, 27),/* F4x9, F4x9 */
924 
925 
926  /* BDCR */
927  RCC_RTC = _REG_BIT(0x70, 15),
928 
929  /* AHB1 peripherals*/
930  SCC_GPIOA = _REG_BIT(0x50, 0),
931  SCC_GPIOB = _REG_BIT(0x50, 1),
932  SCC_GPIOC = _REG_BIT(0x50, 2),
933  SCC_GPIOD = _REG_BIT(0x50, 3),
934  SCC_GPIOE = _REG_BIT(0x50, 4),
935  SCC_GPIOF = _REG_BIT(0x50, 5),
936  SCC_GPIOG = _REG_BIT(0x50, 6),
937  SCC_GPIOH = _REG_BIT(0x50, 7),
938  SCC_GPIOI = _REG_BIT(0x50, 8),
939  SCC_GPIOJ = _REG_BIT(0x50, 9),
940  SCC_GPIOK = _REG_BIT(0x50, 10),
941  SCC_CRC = _REG_BIT(0x50, 12),
942  SCC_FLTIF = _REG_BIT(0x50, 15),
943  SCC_SRAM1 = _REG_BIT(0x50, 16),
944  SCC_SRAM2 = _REG_BIT(0x50, 17),
945  SCC_BKPSRAM = _REG_BIT(0x50, 18),
946  SCC_SRAM3 = _REG_BIT(0x50, 19),/* F2xx, F3xx */
947  SCC_DMA1 = _REG_BIT(0x50, 21),
948  SCC_DMA2 = _REG_BIT(0x50, 22),
949  SCC_DMA2D = _REG_BIT(0x50, 23), /* F4x9 */
950  SCC_ETHMAC = _REG_BIT(0x50, 25),
951  SCC_ETHMACTX = _REG_BIT(0x50, 26),
952  SCC_ETHMACRX = _REG_BIT(0x50, 27),
953  SCC_ETHMACPTP = _REG_BIT(0x50, 28),
954  SCC_OTGHS = _REG_BIT(0x50, 29),
955  SCC_OTGHSULPI = _REG_BIT(0x50, 30),
956 
957  /* AHB2 peripherals */
958  SCC_DCMI = _REG_BIT(0x54, 0),
959  SCC_CRYP = _REG_BIT(0x54, 4),
960  SCC_HASH = _REG_BIT(0x54, 5),
961  SCC_RNG = _REG_BIT(0x54, 6),
962  SCC_OTGFS = _REG_BIT(0x54, 7),
963 
964  /* AHB3 peripherals */
965  SCC_QSPIC = _REG_BIT(0x58, 1),
966  SCC_FMC = _REG_BIT(0x58, 0),
967  SCC_FSMC = _REG_BIT(0x58, 0),
968 
969  /* APB1 peripherals*/
970  SCC_TIM2 = _REG_BIT(0x60, 0),
971  SCC_TIM3 = _REG_BIT(0x60, 1),
972  SCC_TIM4 = _REG_BIT(0x60, 2),
973  SCC_TIM5 = _REG_BIT(0x60, 3),
974  SCC_TIM6 = _REG_BIT(0x60, 4),
975  SCC_TIM7 = _REG_BIT(0x60, 5),
976  SCC_TIM12 = _REG_BIT(0x60, 6),
977  SCC_TIM13 = _REG_BIT(0x60, 7),
978  SCC_TIM14 = _REG_BIT(0x60, 8),
979  SCC_WWDG = _REG_BIT(0x60, 11),
980  SCC_SPI2 = _REG_BIT(0x60, 14),
981  SCC_SPI3 = _REG_BIT(0x60, 15),
982  SCC_USART2 = _REG_BIT(0x60, 17),
983  SCC_USART3 = _REG_BIT(0x60, 18),
984  SCC_UART4 = _REG_BIT(0x60, 19),
985  SCC_UART5 = _REG_BIT(0x60, 20),
986  SCC_I2C1 = _REG_BIT(0x60, 21),
987  SCC_I2C2 = _REG_BIT(0x60, 22),
988  SCC_I2C3 = _REG_BIT(0x60, 23),
989  SCC_CAN1 = _REG_BIT(0x60, 25),
990  SCC_CAN2 = _REG_BIT(0x60, 26),
991  SCC_PWR = _REG_BIT(0x60, 28),
992  SCC_DAC = _REG_BIT(0x60, 29),
993  SCC_UART7 = _REG_BIT(0x60, 30),/* F2xx, F3xx */
994  SCC_UART8 = _REG_BIT(0x60, 31),/* F2xx, F3xx */
995 
996  /* APB2 peripherals */
997  SCC_TIM1 = _REG_BIT(0x64, 0),
998  SCC_TIM8 = _REG_BIT(0x64, 1),
999  SCC_USART1 = _REG_BIT(0x64, 4),
1000  SCC_USART6 = _REG_BIT(0x64, 5),
1001  SCC_ADC1 = _REG_BIT(0x64, 8),
1002  SCC_ADC2 = _REG_BIT(0x64, 9),
1003  SCC_ADC3 = _REG_BIT(0x64, 10),
1004  SCC_SDIO = _REG_BIT(0x64, 11),
1005  SCC_SPI1 = _REG_BIT(0x64, 12),
1006  SCC_SPI4 = _REG_BIT(0x64, 13),/* F2xx, F3xx */
1007  SCC_SYSCFG = _REG_BIT(0x64, 14),
1008  SCC_TIM9 = _REG_BIT(0x64, 16),
1009  SCC_TIM10 = _REG_BIT(0x64, 17),
1010  SCC_TIM11 = _REG_BIT(0x64, 18),
1011  SCC_SPI5 = _REG_BIT(0x64, 20),/* F2xx, F3xx */
1012  SCC_SPI6 = _REG_BIT(0x64, 21),/* F2xx, F3xx */
1013  SCC_SAI1 = _REG_BIT(0x64, 22),/* F4x9 */
1014  SCC_LTDC = _REG_BIT(0x64, 26),/* F4x9 */
1015  SCC_DSI = _REG_BIT(0x64, 27),/* F4x9 */
1016 };
1017 
1019  /* AHB1 peripherals*/
1020  RST_GPIOA = _REG_BIT(0x10, 0),
1021  RST_GPIOB = _REG_BIT(0x10, 1),
1022  RST_GPIOC = _REG_BIT(0x10, 2),
1023  RST_GPIOD = _REG_BIT(0x10, 3),
1024  RST_GPIOE = _REG_BIT(0x10, 4),
1025  RST_GPIOF = _REG_BIT(0x10, 5),
1026  RST_GPIOG = _REG_BIT(0x10, 6),
1027  RST_GPIOH = _REG_BIT(0x10, 7),
1028  RST_GPIOI = _REG_BIT(0x10, 8),
1029  RST_GPIOJ = _REG_BIT(0x10, 9),
1030  RST_GPIOK = _REG_BIT(0x10, 10),
1031  RST_CRC = _REG_BIT(0x10, 12),
1032  RST_DMA1 = _REG_BIT(0x10, 21),
1033  RST_DMA2 = _REG_BIT(0x10, 22),
1034  RST_DMA2D = _REG_BIT(0x10, 23),
1035  RST_ETHMAC = _REG_BIT(0x10, 25),
1036  RST_OTGHS = _REG_BIT(0x10, 29),
1037 
1038  /* AHB2 peripherals */
1039  RST_DCMI = _REG_BIT(0x14, 0),
1040  RST_CRYP = _REG_BIT(0x14, 4),
1041  RST_HASH = _REG_BIT(0x14, 5),
1042  RST_RNG = _REG_BIT(0x14, 6),
1043  RST_OTGFS = _REG_BIT(0x14, 7),
1044 
1045  /* AHB3 peripherals */
1046  RST_QSPI = _REG_BIT(0x18, 1), /* F4x9 */
1047  RST_FSMC = _REG_BIT(0x18, 0),
1048  RST_FMC = _REG_BIT(0x18, 0), /* F4x9 */
1049 
1050  /* APB1 peripherals*/
1051  RST_TIM2 = _REG_BIT(0x20, 0),
1052  RST_TIM3 = _REG_BIT(0x20, 1),
1053  RST_TIM4 = _REG_BIT(0x20, 2),
1054  RST_TIM5 = _REG_BIT(0x20, 3),
1055  RST_TIM6 = _REG_BIT(0x20, 4),
1056  RST_TIM7 = _REG_BIT(0x20, 5),
1057  RST_TIM12 = _REG_BIT(0x20, 6),
1058  RST_TIM13 = _REG_BIT(0x20, 7),
1059  RST_TIM14 = _REG_BIT(0x20, 8),
1060  RST_WWDG = _REG_BIT(0x20, 11),
1061  RST_SPI2 = _REG_BIT(0x20, 14),
1062  RST_SPI3 = _REG_BIT(0x20, 15),
1063  RST_USART2 = _REG_BIT(0x20, 17),
1064  RST_USART3 = _REG_BIT(0x20, 18),
1065  RST_UART4 = _REG_BIT(0x20, 19),
1066  RST_UART5 = _REG_BIT(0x20, 20),
1067  RST_I2C1 = _REG_BIT(0x20, 21),
1068  RST_I2C2 = _REG_BIT(0x20, 22),
1069  RST_I2C3 = _REG_BIT(0x20, 23),
1070  RST_CAN1 = _REG_BIT(0x20, 25),
1071  RST_CAN2 = _REG_BIT(0x20, 26),
1072  RST_PWR = _REG_BIT(0x20, 28),
1073  RST_DAC = _REG_BIT(0x20, 29),
1074  RST_UART7 = _REG_BIT(0x20, 30),/* F2xx, F3xx */
1075  RST_UART8 = _REG_BIT(0x20, 31),/* F2xx, F3xx */
1076 
1077  /* APB2 peripherals */
1078  RST_TIM1 = _REG_BIT(0x24, 0),
1079  RST_TIM8 = _REG_BIT(0x24, 1),
1080  RST_USART1 = _REG_BIT(0x24, 4),
1081  RST_USART6 = _REG_BIT(0x24, 5),
1082  RST_ADC = _REG_BIT(0x24, 8),
1083  RST_SDIO = _REG_BIT(0x24, 11),
1084  RST_SPI1 = _REG_BIT(0x24, 12),
1085  RST_SPI4 = _REG_BIT(0x24, 13),/* F2xx, F3xx */
1086  RST_SYSCFG = _REG_BIT(0x24, 14),
1087  RST_TIM9 = _REG_BIT(0x24, 16),
1088  RST_TIM10 = _REG_BIT(0x24, 17),
1089  RST_TIM11 = _REG_BIT(0x24, 18),
1090  RST_SPI5 = _REG_BIT(0x24, 20),/* F2xx, F3xx */
1091  RST_SPI6 = _REG_BIT(0x24, 21),/* F2xx, F3xx */
1092  RST_SAI1RST = _REG_BIT(0x24, 22),/* F42x, F43x */
1093  RST_LTDC = _REG_BIT(0x24, 26),/* F42x, F43x */
1094  RST_DSI = _REG_BIT(0x24, 27),/* F42x, F43x */
1095 
1096  /* Backup domain control */
1097  RST_BDCR = _REG_BIT(0x70, 16),/* BDCR[16] */
1098 };
1099 
1100 #undef _REG_BIT
1101 
1103 
1105 
1106 void rcc_osc_ready_int_clear(enum rcc_osc osc);
1107 void rcc_osc_ready_int_enable(enum rcc_osc osc);
1108 void rcc_osc_ready_int_disable(enum rcc_osc osc);
1109 int rcc_osc_ready_int_flag(enum rcc_osc osc);
1110 void rcc_css_int_clear(void);
1111 int rcc_css_int_flag(void);
1112 void rcc_wait_for_sysclk_status(enum rcc_osc osc);
1113 void rcc_osc_on(enum rcc_osc osc);
1114 void rcc_osc_off(enum rcc_osc osc);
1115 void rcc_css_enable(void);
1116 void rcc_css_disable(void);
1117 void rcc_plli2s_config(uint16_t n, uint8_t r);
1118 void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r);
1119 void rcc_pllsai_postscalers(uint8_t q, uint8_t r);
1120 void rcc_set_sysclk_source(uint32_t clk);
1121 void rcc_set_pll_source(uint32_t pllsrc);
1122 void rcc_set_ppre2(uint32_t ppre2);
1123 void rcc_set_ppre1(uint32_t ppre1);
1124 void rcc_set_hpre(uint32_t hpre);
1125 void rcc_set_rtcpre(uint32_t rtcpre);
1126 void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
1127  uint32_t pllq, uint32_t pllr);
1128 void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
1129  uint32_t pllq, uint32_t pllr);
1130 uint32_t rcc_system_clock_source(void);
1131 void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
1132 void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);
1133 uint32_t rcc_get_usart_clk_freq(uint32_t usart);
1134 uint32_t rcc_get_timer_clk_freq(uint32_t timer);
1135 uint32_t rcc_get_i2c_clk_freq(uint32_t i2c);
1136 uint32_t rcc_get_spi_clk_freq(uint32_t spi);
1137 
1138 END_DECLS
1139 
1140 #endif
1141 /**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
pwr_vos_scale
Definition: f4/pwr.h:76
int rcc_osc_ready_int_flag(enum rcc_osc osc)
Definition: rcc.c:403
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
Setup clocks with the HSE.
Definition: rcc.c:789
int rcc_css_int_flag(void)
Definition: rcc.c:429
void rcc_osc_ready_int_clear(enum rcc_osc osc)
Definition: rcc.c:322
void rcc_css_disable(void)
Definition: rcc.c:540
uint32_t rcc_get_spi_clk_freq(uint32_t spi)
Get the peripheral clock speed for the SPI device at base specified.
Definition: rcc.c:839
void rcc_set_sysclk_source(uint32_t clk)
Definition: rcc.c:593
void rcc_pllsai_postscalers(uint8_t q, uint8_t r)
Set the dedicated dividers after the PLLSAI configuration.
Definition: rcc.c:583
uint32_t rcc_apb2_frequency
Definition: rcc.c:50
void rcc_set_pll_source(uint32_t pllsrc)
Definition: rcc.c:602
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
Get the peripheral clock speed for the Timer at base specified.
Definition: rcc.c:812
uint32_t rcc_system_clock_source(void)
Definition: rcc.c:695
const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]
Definition: rcc.c:106
void rcc_plli2s_config(uint16_t n, uint8_t r)
Set the dividers for the PLLI2S clock outputs.
Definition: rcc.c:550
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
Get the peripheral clock speed for the USART at base specified.
Definition: rcc.c:798
const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]
Definition: rcc.c:52
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
Setup clocks to run from PLL.
Definition: rcc.c:709
rcc_periph_rst
Definition: f4/rcc.h:1018
rcc_periph_clken
Definition: f4/rcc.h:839
const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]
Definition: rcc.c:160
void rcc_set_rtcpre(uint32_t rtcpre)
Definition: rcc.c:638
const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END]
Definition: rcc.c:268
void rcc_osc_ready_int_enable(enum rcc_osc osc)
Definition: rcc.c:349
rcc_osc
Definition: f4/rcc.h:827
void rcc_osc_ready_int_disable(enum rcc_osc osc)
Definition: rcc.c:376
void rcc_osc_on(enum rcc_osc osc)
Definition: rcc.c:481
#define _REG_BIT(base, bit)
Definition: f4/rcc.h:837
uint32_t rcc_ahb_frequency
Definition: rcc.c:48
void rcc_osc_off(enum rcc_osc osc)
Definition: rcc.c:508
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
Reconfigures the main PLL for a HSE source.
Definition: rcc.c:680
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
Get the peripheral clock speed for the I2C device at base specified.
Definition: rcc.c:830
rcc_clock_3v3
Definition: f4/rcc.h:797
uint32_t rcc_apb1_frequency
Definition: rcc.c:49
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
Definition: rcc.c:460
void rcc_set_ppre1(uint32_t ppre1)
Definition: rcc.c:620
void rcc_css_int_clear(void)
Definition: rcc.c:424
void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r)
Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts,...
Definition: rcc.c:566
void rcc_set_ppre2(uint32_t ppre2)
Definition: rcc.c:611
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
Reconfigures the main PLL for a HSI source.
Definition: rcc.c:656
void rcc_css_enable(void)
Definition: rcc.c:535
void rcc_set_hpre(uint32_t hpre)
Definition: rcc.c:629
const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]
Definition: rcc.c:214
@ RST_DSI
Definition: f4/rcc.h:1094
@ RST_SPI4
Definition: f4/rcc.h:1085
@ RST_DMA2
Definition: f4/rcc.h:1033
@ RST_FSMC
Definition: f4/rcc.h:1047
@ RST_QSPI
Definition: f4/rcc.h:1046
@ RST_DMA1
Definition: f4/rcc.h:1032
@ RST_SPI1
Definition: f4/rcc.h:1084
@ RST_I2C3
Definition: f4/rcc.h:1069
@ RST_SPI6
Definition: f4/rcc.h:1091
@ RST_USART6
Definition: f4/rcc.h:1081
@ RST_GPIOI
Definition: f4/rcc.h:1028
@ RST_OTGHS
Definition: f4/rcc.h:1036
@ RST_GPIOG
Definition: f4/rcc.h:1026
@ RST_DMA2D
Definition: f4/rcc.h:1034
@ RST_RNG
Definition: f4/rcc.h:1042
@ RST_TIM14
Definition: f4/rcc.h:1059
@ RST_GPIOF
Definition: f4/rcc.h:1025
@ RST_UART7
Definition: f4/rcc.h:1074
@ RST_BDCR
Definition: f4/rcc.h:1097
@ RST_SPI2
Definition: f4/rcc.h:1061
@ RST_GPIOH
Definition: f4/rcc.h:1027
@ RST_TIM9
Definition: f4/rcc.h:1087
@ RST_UART4
Definition: f4/rcc.h:1065
@ RST_TIM8
Definition: f4/rcc.h:1079
@ RST_TIM3
Definition: f4/rcc.h:1052
@ RST_TIM12
Definition: f4/rcc.h:1057
@ RST_TIM10
Definition: f4/rcc.h:1088
@ RST_DCMI
Definition: f4/rcc.h:1039
@ RST_GPIOA
Definition: f4/rcc.h:1020
@ RST_ETHMAC
Definition: f4/rcc.h:1035
@ RST_GPIOC
Definition: f4/rcc.h:1022
@ RST_TIM6
Definition: f4/rcc.h:1055
@ RST_GPIOB
Definition: f4/rcc.h:1021
@ RST_TIM1
Definition: f4/rcc.h:1078
@ RST_SPI3
Definition: f4/rcc.h:1062
@ RST_CRYP
Definition: f4/rcc.h:1040
@ RST_USART3
Definition: f4/rcc.h:1064
@ RST_DAC
Definition: f4/rcc.h:1073
@ RST_ADC
Definition: f4/rcc.h:1082
@ RST_TIM13
Definition: f4/rcc.h:1058
@ RST_TIM7
Definition: f4/rcc.h:1056
@ RST_SPI5
Definition: f4/rcc.h:1090
@ RST_TIM2
Definition: f4/rcc.h:1051
@ RST_CAN2
Definition: f4/rcc.h:1071
@ RST_CRC
Definition: f4/rcc.h:1031
@ RST_GPIOD
Definition: f4/rcc.h:1023
@ RST_GPIOK
Definition: f4/rcc.h:1030
@ RST_GPIOJ
Definition: f4/rcc.h:1029
@ RST_TIM4
Definition: f4/rcc.h:1053
@ RST_TIM5
Definition: f4/rcc.h:1054
@ RST_SYSCFG
Definition: f4/rcc.h:1086
@ RST_UART5
Definition: f4/rcc.h:1066
@ RST_GPIOE
Definition: f4/rcc.h:1024
@ RST_HASH
Definition: f4/rcc.h:1041
@ RST_I2C2
Definition: f4/rcc.h:1068
@ RST_CAN1
Definition: f4/rcc.h:1070
@ RST_UART8
Definition: f4/rcc.h:1075
@ RST_PWR
Definition: f4/rcc.h:1072
@ RST_USART1
Definition: f4/rcc.h:1080
@ RST_SDIO
Definition: f4/rcc.h:1083
@ RST_WWDG
Definition: f4/rcc.h:1060
@ RST_I2C1
Definition: f4/rcc.h:1067
@ RST_FMC
Definition: f4/rcc.h:1048
@ RST_USART2
Definition: f4/rcc.h:1063
@ RST_OTGFS
Definition: f4/rcc.h:1043
@ RST_TIM11
Definition: f4/rcc.h:1089
@ RST_SAI1RST
Definition: f4/rcc.h:1092
@ RST_LTDC
Definition: f4/rcc.h:1093
@ SCC_CRC
Definition: f4/rcc.h:941
@ SCC_TIM14
Definition: f4/rcc.h:978
@ RCC_TIM8
Definition: f4/rcc.h:906
@ RCC_DSI
Definition: f4/rcc.h:923
@ SCC_TIM8
Definition: f4/rcc.h:998
@ SCC_SPI3
Definition: f4/rcc.h:981
@ RCC_UART5
Definition: f4/rcc.h:893
@ RCC_RNG
Definition: f4/rcc.h:869
@ SCC_TIM11
Definition: f4/rcc.h:1010
@ RCC_GPIOJ
Definition: f4/rcc.h:850
@ RCC_TIM9
Definition: f4/rcc.h:916
@ RCC_FMC
Definition: f4/rcc.h:874
@ RCC_FSMC
Definition: f4/rcc.h:873
@ SCC_CAN2
Definition: f4/rcc.h:990
@ SCC_GPIOD
Definition: f4/rcc.h:933
@ SCC_TIM12
Definition: f4/rcc.h:976
@ RCC_SPI2
Definition: f4/rcc.h:888
@ RCC_WWDG
Definition: f4/rcc.h:887
@ SCC_TIM1
Definition: f4/rcc.h:997
@ RCC_TIM3
Definition: f4/rcc.h:879
@ SCC_SPI2
Definition: f4/rcc.h:980
@ RCC_SDIO
Definition: f4/rcc.h:912
@ RCC_TIM1
Definition: f4/rcc.h:905
@ RCC_ETHMACPTP
Definition: f4/rcc.h:861
@ SCC_ETHMACTX
Definition: f4/rcc.h:951
@ SCC_SPI6
Definition: f4/rcc.h:1012
@ SCC_UART4
Definition: f4/rcc.h:984
@ RCC_CAN2
Definition: f4/rcc.h:898
@ SCC_SRAM1
Definition: f4/rcc.h:943
@ RCC_GPIOA
Definition: f4/rcc.h:841
@ SCC_GPIOH
Definition: f4/rcc.h:937
@ SCC_RNG
Definition: f4/rcc.h:961
@ RCC_SPI6
Definition: f4/rcc.h:920
@ SCC_DSI
Definition: f4/rcc.h:1015
@ SCC_SRAM3
Definition: f4/rcc.h:946
@ RCC_RTC
Definition: f4/rcc.h:927
@ SCC_TIM13
Definition: f4/rcc.h:977
@ SCC_GPIOA
Definition: f4/rcc.h:930
@ SCC_ADC2
Definition: f4/rcc.h:1002
@ SCC_DMA2
Definition: f4/rcc.h:948
@ RCC_GPIOK
Definition: f4/rcc.h:851
@ RCC_TIM2
Definition: f4/rcc.h:878
@ SCC_USART6
Definition: f4/rcc.h:1000
@ SCC_TIM6
Definition: f4/rcc.h:974
@ SCC_ADC1
Definition: f4/rcc.h:1001
@ RCC_BKPSRAM
Definition: f4/rcc.h:853
@ SCC_TIM2
Definition: f4/rcc.h:970
@ SCC_TIM3
Definition: f4/rcc.h:971
@ SCC_DMA2D
Definition: f4/rcc.h:949
@ SCC_TIM9
Definition: f4/rcc.h:1008
@ RCC_GPIOG
Definition: f4/rcc.h:847
@ SCC_QSPIC
Definition: f4/rcc.h:965
@ RCC_UART8
Definition: f4/rcc.h:902
@ RCC_GPIOH
Definition: f4/rcc.h:848
@ RCC_TIM10
Definition: f4/rcc.h:917
@ RCC_CAN1
Definition: f4/rcc.h:897
@ SCC_FSMC
Definition: f4/rcc.h:967
@ RCC_PWR
Definition: f4/rcc.h:899
@ RCC_CRC
Definition: f4/rcc.h:852
@ RCC_ETHMACRX
Definition: f4/rcc.h:860
@ SCC_USART2
Definition: f4/rcc.h:982
@ RCC_TIM14
Definition: f4/rcc.h:886
@ RCC_OTGHSULPI
Definition: f4/rcc.h:863
@ RCC_OTGHS
Definition: f4/rcc.h:862
@ SCC_USART3
Definition: f4/rcc.h:983
@ SCC_GPIOJ
Definition: f4/rcc.h:939
@ SCC_I2C2
Definition: f4/rcc.h:987
@ SCC_UART8
Definition: f4/rcc.h:994
@ RCC_USART1
Definition: f4/rcc.h:907
@ SCC_WWDG
Definition: f4/rcc.h:979
@ SCC_PWR
Definition: f4/rcc.h:991
@ SCC_SYSCFG
Definition: f4/rcc.h:1007
@ RCC_TIM4
Definition: f4/rcc.h:880
@ RCC_I2C1
Definition: f4/rcc.h:894
@ RCC_ADC2
Definition: f4/rcc.h:910
@ RCC_DMA2D
Definition: f4/rcc.h:857
@ SCC_DCMI
Definition: f4/rcc.h:958
@ RCC_TIM13
Definition: f4/rcc.h:885
@ SCC_DAC
Definition: f4/rcc.h:992
@ SCC_ETHMAC
Definition: f4/rcc.h:950
@ RCC_ADC1
Definition: f4/rcc.h:909
@ SCC_SRAM2
Definition: f4/rcc.h:944
@ RCC_CCMDATARAM
Definition: f4/rcc.h:854
@ RCC_LTDC
Definition: f4/rcc.h:922
@ SCC_SPI1
Definition: f4/rcc.h:1005
@ RCC_DCMI
Definition: f4/rcc.h:866
@ SCC_DMA1
Definition: f4/rcc.h:947
@ SCC_ETHMACRX
Definition: f4/rcc.h:952
@ SCC_ADC3
Definition: f4/rcc.h:1003
@ SCC_SPI4
Definition: f4/rcc.h:1006
@ SCC_LTDC
Definition: f4/rcc.h:1014
@ RCC_ETHMACTX
Definition: f4/rcc.h:859
@ RCC_USART2
Definition: f4/rcc.h:890
@ SCC_GPIOE
Definition: f4/rcc.h:934
@ RCC_ADC3
Definition: f4/rcc.h:911
@ RCC_TIM12
Definition: f4/rcc.h:884
@ SCC_USART1
Definition: f4/rcc.h:999
@ RCC_USART3
Definition: f4/rcc.h:891
@ SCC_I2C1
Definition: f4/rcc.h:986
@ RCC_TIM5
Definition: f4/rcc.h:881
@ RCC_SPI1
Definition: f4/rcc.h:913
@ RCC_SYSCFG
Definition: f4/rcc.h:915
@ SCC_GPIOC
Definition: f4/rcc.h:932
@ RCC_HASH
Definition: f4/rcc.h:868
@ RCC_UART7
Definition: f4/rcc.h:901
@ SCC_SPI5
Definition: f4/rcc.h:1011
@ RCC_ETHMAC
Definition: f4/rcc.h:858
@ RCC_I2C2
Definition: f4/rcc.h:895
@ SCC_HASH
Definition: f4/rcc.h:960
@ RCC_GPIOB
Definition: f4/rcc.h:842
@ RCC_TIM7
Definition: f4/rcc.h:883
@ RCC_SPI5
Definition: f4/rcc.h:919
@ RCC_GPIOF
Definition: f4/rcc.h:846
@ SCC_GPIOF
Definition: f4/rcc.h:935
@ SCC_OTGFS
Definition: f4/rcc.h:962
@ SCC_ETHMACPTP
Definition: f4/rcc.h:953
@ RCC_GPIOC
Definition: f4/rcc.h:843
@ RCC_QUADSPI
Definition: f4/rcc.h:875
@ SCC_FLTIF
Definition: f4/rcc.h:942
@ RCC_CRYP
Definition: f4/rcc.h:867
@ RCC_TIM6
Definition: f4/rcc.h:882
@ RCC_UART4
Definition: f4/rcc.h:892
@ SCC_CAN1
Definition: f4/rcc.h:989
@ SCC_TIM5
Definition: f4/rcc.h:973
@ SCC_I2C3
Definition: f4/rcc.h:988
@ SCC_GPIOB
Definition: f4/rcc.h:931
@ RCC_DMA1
Definition: f4/rcc.h:855
@ RCC_GPIOI
Definition: f4/rcc.h:849
@ RCC_SPI3
Definition: f4/rcc.h:889
@ SCC_GPIOI
Definition: f4/rcc.h:938
@ SCC_GPIOG
Definition: f4/rcc.h:936
@ RCC_DAC
Definition: f4/rcc.h:900
@ RCC_GPIOD
Definition: f4/rcc.h:844
@ SCC_OTGHS
Definition: f4/rcc.h:954
@ SCC_GPIOK
Definition: f4/rcc.h:940
@ SCC_CRYP
Definition: f4/rcc.h:959
@ SCC_FMC
Definition: f4/rcc.h:966
@ SCC_SDIO
Definition: f4/rcc.h:1004
@ RCC_I2C3
Definition: f4/rcc.h:896
@ RCC_GPIOE
Definition: f4/rcc.h:845
@ SCC_SAI1
Definition: f4/rcc.h:1013
@ SCC_UART7
Definition: f4/rcc.h:993
@ RCC_OTGFS
Definition: f4/rcc.h:870
@ SCC_OTGHSULPI
Definition: f4/rcc.h:955
@ SCC_BKPSRAM
Definition: f4/rcc.h:945
@ SCC_UART5
Definition: f4/rcc.h:985
@ SCC_TIM7
Definition: f4/rcc.h:975
@ RCC_USART6
Definition: f4/rcc.h:908
@ RCC_DMA2
Definition: f4/rcc.h:856
@ RCC_SAI1EN
Definition: f4/rcc.h:921
@ RCC_SPI4
Definition: f4/rcc.h:914
@ RCC_TIM11
Definition: f4/rcc.h:918
@ SCC_TIM4
Definition: f4/rcc.h:972
@ SCC_TIM10
Definition: f4/rcc.h:1009
@ RCC_HSI
Definition: f4/rcc.h:832
@ RCC_PLLSAI
Definition: f4/rcc.h:829
@ RCC_PLLI2S
Definition: f4/rcc.h:830
@ RCC_LSI
Definition: f4/rcc.h:834
@ RCC_PLL
Definition: f4/rcc.h:828
@ RCC_LSE
Definition: f4/rcc.h:833
@ RCC_HSE
Definition: f4/rcc.h:831
@ RCC_CLOCK_3V3_180MHZ
Definition: f4/rcc.h:800
@ RCC_CLOCK_3V3_END
Definition: f4/rcc.h:801
@ RCC_CLOCK_3V3_168MHZ
Definition: f4/rcc.h:799
@ RCC_CLOCK_3V3_84MHZ
Definition: f4/rcc.h:798
uint8_t ppre1
Definition: f4/rcc.h:813
uint8_t pllq
Definition: f4/rcc.h:808
uint8_t ppre2
Definition: f4/rcc.h:814
uint8_t pllp
Definition: f4/rcc.h:807
uint32_t apb1_frequency
Definition: f4/rcc.h:817
uint8_t pllm
Definition: f4/rcc.h:805
uint32_t ahb_frequency
Definition: f4/rcc.h:816
uint16_t plln
Definition: f4/rcc.h:806
enum pwr_vos_scale voltage_scale
Definition: f4/rcc.h:815
uint8_t pllr
Definition: f4/rcc.h:809
uint32_t flash_config
Definition: f4/rcc.h:811
uint8_t hpre
Definition: f4/rcc.h:812
uint32_t apb2_frequency
Definition: f4/rcc.h:818
uint8_t pll_source
Definition: f4/rcc.h:810