libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Modules | |
ADC external trigger selection values | |
EXTEN: External trigger enable and polarity selection for regular channels | |
RES: Data resolution | |
Macros | |
#define | ADC_CFGR1_ALIGN (1 << 5) |
ALIGN: Data alignment. More... | |
#define | ADC_CFGR1_EXTSEL_SHIFT 6 |
#define | ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) |
#define | ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) |
#define | ADC_CFGR1_CHSELRMOD (1 << 21) |
CHSELRMOD: Mode Selection of the ADC_CHSELR register. More... | |
#define | ADC_CFGR1_AWD1CH_SHIFT 26 |
#define | ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) |
#define | ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT) |
AWD1CH: Analog watchdog 1 channel selection. More... | |
#define | ADC_CFGR1_AWD1EN (1 << 23) |
AWD1EN: Analog watchdog 1 enable on regular channels. More... | |
#define | ADC_CFGR1_AWD1SGL (1 << 22) |
AWD1SGL: Enable the watchdog 1 on a single channel or on all channels. More... | |
#define | ADC_CFGR1_DISCEN (1 << 16) |
DISCEN: Discontinuous mode for regular channels. More... | |
#define | ADC_CFGR1_AUTDLY (1 << 14) |
AUTDLY: Delayed conversion mode. More... | |
#define | ADC_CFGR1_CONT (1 << 13) |
CONT: Single / continuous conversion mode for regular conversions. More... | |
#define | ADC_CFGR1_OVRMOD (1 << 12) |
OVRMOD: Overrun Mode. More... | |
#define | ADC_CFGR1_EXTEN_MASK (0x3 << 10) |
#define | ADC_CFGR1_RES_MASK (0x3 << 3) |
#define | ADC_CFGR1_DMACFG (1 << 1) |
DMACFG: Direct memory access configuration. More... | |
#define | ADC_CFGR1_DMAEN (1 << 0) |
DMAEN: Direct memory access enable. More... | |
#define | ADC_CFGR1_WAIT (1<<14) |
Wait conversion mode. More... | |
#define | ADC_CFGR1_AUTOFF (1 << 15) |
Auto off mode. More... | |
#define | ADC_CFGR1_SCANDIR (1 << 2) |
SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) More... | |
#define ADC_CFGR1_AUTDLY (1 << 14) |
AUTDLY: Delayed conversion mode.
Definition at line 138 of file adc_common_v2.h.
#define ADC_CFGR1_AUTOFF (1 << 15) |
Auto off mode.
Definition at line 59 of file adc_common_v2_single.h.
#define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) |
Definition at line 127 of file adc_common_v2.h.
#define ADC_CFGR1_AWD1CH_SHIFT 26 |
Definition at line 126 of file adc_common_v2.h.
#define ADC_CFGR1_AWD1CH_VAL | ( | x | ) | ((x) << ADC_CFGR1_AWD1CH_SHIFT) |
AWD1CH: Analog watchdog 1 channel selection.
Definition at line 129 of file adc_common_v2.h.
#define ADC_CFGR1_AWD1EN (1 << 23) |
AWD1EN: Analog watchdog 1 enable on regular channels.
Definition at line 132 of file adc_common_v2.h.
#define ADC_CFGR1_AWD1SGL (1 << 22) |
AWD1SGL: Enable the watchdog 1 on a single channel or on all channels.
Definition at line 134 of file adc_common_v2.h.
#define ADC_CFGR1_CHSELRMOD (1 << 21) |
#define ADC_CFGR1_CONT (1 << 13) |
CONT: Single / continuous conversion mode for regular conversions.
Definition at line 140 of file adc_common_v2.h.
#define ADC_CFGR1_DISCEN (1 << 16) |
DISCEN: Discontinuous mode for regular channels.
Definition at line 136 of file adc_common_v2.h.
#define ADC_CFGR1_DMACFG (1 << 1) |
DMACFG: Direct memory access configuration.
Definition at line 163 of file adc_common_v2.h.
#define ADC_CFGR1_DMAEN (1 << 0) |
DMAEN: Direct memory access enable.
Definition at line 166 of file adc_common_v2.h.
#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) |
Definition at line 144 of file adc_common_v2.h.
#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) |
#define ADC_CFGR1_EXTSEL_VAL | ( | x | ) | ((x) << ADC_CFGR1_EXTSEL_SHIFT) |
#define ADC_CFGR1_OVRMOD (1 << 12) |
OVRMOD: Overrun Mode.
Definition at line 142 of file adc_common_v2.h.
#define ADC_CFGR1_RES_MASK (0x3 << 3) |
Definition at line 153 of file adc_common_v2.h.
#define ADC_CFGR1_SCANDIR (1 << 2) |
SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1)
Definition at line 62 of file adc_common_v2_single.h.
#define ADC_CFGR1_WAIT (1<<14) |
Wait conversion mode.
Definition at line 57 of file adc_common_v2_single.h.