libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
g0/adc.h
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1/** @defgroup adc_defines ADC Defines
2 *
3 * @ingroup STM32G0xx_defines
4*
5 * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
6 *
7 * @brief <b>Defined Constants and Types for the STM32STM32G0xx Analog to Digital Converter</b>
8 *
9 * @version 1.0.0
10 *
11 * LGPL License Terms @ref lgpl_license
12 * */
13/*
14 * This file is part of the libopencm3 project.
15 *
16 * This library is free software: you can redistribute it and/or modify
17 * it under the terms of the GNU Lesser General Public License as published by
18 * the Free Software Foundation, either version 3 of the License, or
19 * (at your option) any later version.
20 *
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU Lesser General Public License for more details.
25 *
26 * You should have received a copy of the GNU Lesser General Public License
27 * along with this library. If not, see <http://www.gnu.org/licenses/>.
28 */
29
30/**@{*/
31
32#ifndef LIBOPENCM3_ADC_H
33#define LIBOPENCM3_ADC_H
34
35#include <libopencm3/stm32/common/adc_common_v2.h>
36#include <libopencm3/stm32/common/adc_common_v2_single.h>
37
38/** @defgroup adc_reg_base ADC register base addresses
39 *@{*/
40#define ADC1 ADC1_BASE
41/**@}*/
42
43/** @defgroup adc_channel ADC Channel Numbers
44 *@{*/
45#define ADC_CHANNEL_TEMP 12
46#define ADC_CHANNEL_VREF 13
47#define ADC_CHANNEL_VBAT 14
48/**@}*/
49
50/** @addtogroup adc_registers
51 *@{*/
52/* ----- ADC registers -----------------------------------------------------*/
53/** ADC_AWD1TR Watchdog 1 Threshold register */
54#define ADC_AWD1TR(adc) MMIO32((adc) + 0x20)
55/** ADC_AWD2TR Watchdog 2 Threshold register */
56#define ADC_AWD2TR(adc) MMIO32((adc) + 0x22)
57/** ADC_AWD3TR Watchdog 3 Threshold register */
58#define ADC_AWD3TR(adc) MMIO32((adc) + 0x2c)
59
60/** ADC_AWD2CR Watchdog 2 Configuration register */
61#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)
62/** ADC_AWD3CR Watchdog 3 Configuration register */
63#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)
64
65/** ADC_CALFACT Calibration factor register */
66#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4)
67/**@}*/
68
69/* --- Register values -------------------------------------------------------*/
70
71/** @addtogroup adc_isr
72@{*/
73
74/** CCRDY: Channel Configuration Ready flag */
75#define ADC_ISR_CCRDY (1 << 13)
76
77/**@}*/
78
79/** @addtogroup adc_ier
80@{*/
81
82/** CCRDYIE: Channel Configuration Ready Interrupt enable bit */
83#define ADC_IER_CCRDYIE (1 << 13)
84
85/**@}*/
86
87/** @addtogroup adc_ccr
88@{*/
89
90#define ADC_CCR_PRESC_MASK (0xf)
91#define ADC_CCR_PRESC_SHIFT (18)
92/** @defgroup adc_ccr_presc ADC clock prescaler
93 *@{*/
94#define ADC_CCR_PRESC_NODIV (0x0)
95#define ADC_CCR_PRESC_DIV2 (0x1)
96#define ADC_CCR_PRESC_DIV4 (0x2)
97#define ADC_CCR_PRESC_DIV6 (0x3)
98#define ADC_CCR_PRESC_DIV8 (0x4)
99#define ADC_CCR_PRESC_DIV10 (0x5)
100#define ADC_CCR_PRESC_DIV12 (0x6)
101#define ADC_CCR_PRESC_DIV16 (0x7)
102#define ADC_CCR_PRESC_DIV32 (0x8)
103#define ADC_CCR_PRESC_DIV64 (0x9)
104#define ADC_CCR_PRESC_DIV128 (0xa)
105#define ADC_CCR_PRESC_DIV256 (0xb)
106/**@}*/
107
108/**@}*/
109
110/** @addtogroup adc_cr
111@{*/
112
113/** ADVREGEN: Voltage regulator enable bit */
114#define ADC_CR_ADVREGEN (1 << 28)
115
116/**@}*/
117
118/** @addtogroup adc_cfgr1
119@{*/
120
121/** ALIGN: Data alignment */
122#define ADC_CFGR1_ALIGN (1 << 5)
123
124/* EXTSEL[2:0]: External trigger selection for regular group */
125#define ADC_CFGR1_EXTSEL_SHIFT 6
126#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)
127#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
128/** @defgroup adc_cfgr1_extsel ADC external trigger selection values
129 *@{*/
130#define ADC_CFGR1_EXTSEL_TIM1_TRGO2 0x0
131#define ADC_CFGR1_EXTSEL_TIM1_CC4 0x1
132#define ADC_CFGR1_EXTSEL_TIM2_TRGO 0x2
133#define ADC_CFGR1_EXTSEL_TIM3_TRGO 0x3
134#define ADC_CFGR1_EXTSEL_TIM15_TRGO 0x4
135#define ADC_CFGR1_EXTSEL_TIM6_TRGO 0x5
136#define ADC_CFGR1_EXTSEL_TIM4_TRGO 0x6
137#define ADC_CFGR1_EXTSEL_EXTI11 0x7
138/**@}*/
139
140/** CHSELRMOD: Mode Selection of the ADC_CHSELR register */
141#define ADC_CFGR1_CHSELRMOD (1 << 21)
142
143/**@}*/
144
145/** @addtogroup adc_cfgr2
146@{*/
147
148#define ADC_CFGR2_CKMODE_SHIFT (30)
149#define ADC_CFGR2_CKMODE_MASK (0x3)
150/** @defgroup adc_cfgr2_ckmode ADC Clock mode
151 *@{*/
152#define ADC_CFGR2_CKMODE_ADCCLK (0x0)
153#define ADC_CFGR2_CKMODE_PCLK_DIV2 (0x1)
154#define ADC_CFGR2_CKMODE_PCLK_DIV4 (0x2)
155#define ADC_CFGR2_CKMODE_PCLK (0x3)
156/**@}*/
157
158/** LFTRIG: Low Frequency Trigger Mode enable bit */
159#define ADC_CFGR2_LFTRIG (1 << 29)
160
161/** TOVS: Triggered Oversampling */
162#define ADC_CFGR2_TOVS (1 << 9)
163
164#define ADC_CFGR2_OVSS_SHIFT (5)
165#define ADC_CFGR2_OVSS_MASK (0xf)
166/** @defgroup adc_cfgr2_ovss ADC Oversampling shift
167 *@{*/
168#define ADC_CFGR2_OVSS_BITS(bits) (bits)
169/**@}*/
170
171#define ADC_CFGR2_OVSR_SHIFT (2)
172#define ADC_CFGR2_OVSR_MASK (0x7)
173/** @defgroup adc_cfgr2_ovsr ADC Oversampling ratio
174 *@{*/
175#define ADC_CFGR2_OVSR_2x (0x0)
176#define ADC_CFGR2_OVSR_4x (0x1)
177#define ADC_CFGR2_OVSR_8x (0x2)
178#define ADC_CFGR2_OVSR_16x (0x3)
179#define ADC_CFGR2_OVSR_32x (0x4)
180#define ADC_CFGR2_OVSR_64x (0x5)
181#define ADC_CFGR2_OVSR_128x (0x6)
182#define ADC_CFGR2_OVSR_256x (0x7)
183/**@}*/
184
185/** OVSE: Oversampler mode enable bit */
186#define ADC_CFGR2_OVSE (1 << 0)
187
188/**@}*/
189
190/** @addtogroup adc_smpr
191@{*/
192
193/* SMP1 ADC Channel Sample Time selection */
194#define ADC_SMPR_SMPSEL_SHIFT 0x8
195#define ADC_SMPR_SMPSEL_MASK 0x7ffff
196#define ADC_SMPR_SMPSEL_CHANNEL_SHIFT(channel) ((channel) + ADC_SMPR_SMPSEL_SHIFT)
197#define ADC_SMPR_SMPSEL_CHANNEL_MASK (1)
198/** @defgroup adc_smpr_smpsel ADC Sample Time selection
199@{*/
200#define ADC_SMPR_SMPSEL_SMP1 0x0
201#define ADC_SMPR_SMPSEL_SMP2 0x1
202/**@}*/
203
204/** SMP1 ADC Sample Time #1 selection */
205#define ADC_SMPR_SMP1_SHIFT 0x0
206#define ADC_SMPR_SMP1_MASK 0x7
207
208/** SMP1 ADC Sample Time #2 selection */
209#define ADC_SMPR_SMP2_SHIFT 0x4
210#define ADC_SMPR_SMP2_MASK 0x7
211
212/** @defgroup adc_smpr_smp ADC Sample Time selection values
213@{*/
214#define ADC_SMPR_SMPx_001DOT5CYC 0x0
215#define ADC_SMPR_SMPx_003DOT5CYC 0x1
216#define ADC_SMPR_SMPx_007DOT5CYC 0x2
217#define ADC_SMPR_SMPx_012DOT5CYC 0x3
218#define ADC_SMPR_SMPx_019DOT5CYC 0x4
219#define ADC_SMPR_SMPx_039DOT5CYC 0x5
220#define ADC_SMPR_SMPx_079DOT5CYC 0x6
221#define ADC_SMPR_SMPx_160DOT5CYC 0x7
222/**@}*/
223
224/**@}*/
225
226/** @defgroup adc_awdtr1 AWDTR1 ADC watchdog threshold register 1
227* Shadows adc adc_tr1 register on other chips.
228@{*/
229
230#define ADC_AWDTR1_LT_SHIFT 0
231#define ADC_AWDTR1_LT (0xFFF << ADC_TR1_LT_SHIFT)
232#define ADC_AWDTR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT)
233
234#define ADC_AWDTR1_HT_SHIFT 16
235#define ADC_AWDTR1_HT (0xFFF << ADC_TR1_HT_SHIFT)
236#define ADC_AWDTR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT)
237
238/**@}*/
239
240/** @defgroup adc_awdtr2 AWDTR2 ADC watchdog threshold register 2
241@{*/
242
243#define ADC_AWDTR2_LT_SHIFT 0
244#define ADC_AWDTR2_LT (0xFFF << ADC_TR2_LT_SHIFT)
245#define ADC_AWDTR2_LT_VAL(x) ((x) << ADC_TR2_LT_SHIFT)
246
247#define ADC_AWDTR2_HT_SHIFT 16
248#define ADC_AWDTR2_HT (0xFFF << ADC_TR2_HT_SHIFT)
249#define ADC_AWDTR2_HT_VAL(x) ((x) << ADC_TR2_HT_SHIFT)
250
251/**@}*/
252
253/** @addtogroup adc_chselr
254@{*/
255
256/** ADC_CHSELR_MAX_CHANNELS Maximum number of channel in regular sequence */
257#define ADC_CHSELR_MAX_CHANNELS 18
258
259/** ADC_CHSELR_MAX_SQ_CHANNELS Maximum number of sequences in fully configurable mode */
260#define ADC_CHSELR_MAX_SQS 8
261/** ADC_CHSELR_SQS_MAX_CHANNEL Maximum channel number in a fully configuralbe sequence */
262#define ADC_CHSELR_SQS_MAX_CHANNEL 14
263
264#define ADC_CHSELR_SQx_MASK 0xf
265#define ADC_CHSELR_SQx_SHIFT(seqnum) (4 * ((seqnum)-1))
266
267/** ADC_CHSELR_SQx Xth conversion of ADC sequence channel number value */
268#define ADC_CHSELR_SQx(seqnum, value) ((value) << ADC_CHSELR_SQx_SHIFT(seqnum))
269
270/** ADC_CHSELR_SQx_EOS End of Sequence */
271#define ADC_CHSELR_SQx_EOS 0xf
272
273/**@}*/
274
275/** @defgroup adc_awdtr2 AWDTR2 ADC watchdog threshold register 2
276@{*/
277
278#define ADC_AWDTR3_LT_SHIFT 0
279#define ADC_AWDTR3_LT (0xFFF << ADC_TR3_LT_SHIFT)
280#define ADC_AWDTR3_LT_VAL(x) ((x) << ADC_TR3_LT_SHIFT)
281
282#define ADC_AWDTR3_HT_SHIFT 16
283#define ADC_AWDTR3_HT (0xFFF << ADC_TR3_HT_SHIFT)
284#define ADC_AWDTR3_HT_VAL(x) ((x) << ADC_TR3_HT_SHIFT)
285
286/**@}*/
287
288/** @defgroup adc_awd2cr AWD2CR ADC Analog watchdog 2 configuration register
289@{*/
290
291/** AWD2CR Analog watchdog channel selection */
292#define ADC_AW2CR_AWD2CHx_EN(x) (1 << x)
293
294/**@}*/
295
296/** @defgroup adc_awd3cr AWD3CR ADC Analog watchdog 3 configuration register
297@{*/
298
299/** AWD3CR Analog watchdog channel selection */
300#define ADC_AW3CR_AWD3CHx_EN(x) (1 << x)
301
302/**@}*/
303
304/* --- API definition ----------------------------------------------------- */
305
306/** @defgroup adc_api_clksource ADC clock source
307 *@{*/
308#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_ADCCLK
309#define ADC_CLKSOURCE_PCLK ADC_CFGR2_CKMODE_PCLK
310#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2
311#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4
312/**@}*/
313
314/** @defgroup adc_api_smptime ADC Sampling Time
315 *@{*/
316#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMPx_001DOT5CYC
317#define ADC_SMPTIME_003DOT5 ADC_SMPR_SMPx_003DOT5CYC
318#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMPx_007DOT5CYC
319#define ADC_SMPTIME_012DOT5 ADC_SMPR_SMPx_012DOT5CYC
320#define ADC_SMPTIME_019DOT5 ADC_SMPR_SMPx_019DOT5CYC
321#define ADC_SMPTIME_039DOT5 ADC_SMPR_SMPx_039DOT5CYC
322#define ADC_SMPTIME_079DOT5 ADC_SMPR_SMPx_079DOT5CYC
323#define ADC_SMPTIME_160DOT5 ADC_SMPR_SMPx_160DOT5CYC
324/**@}*/
325
326/* --- Function prototypes ------------------------------------------------- */
327
328BEGIN_DECLS
329
330void adc_set_clk_source(uint32_t adc, uint32_t source);
331void adc_set_clk_prescale(uint32_t adc, uint32_t prescale);
332
333void adc_set_channel_sample_time_selection(uint32_t adc, uint8_t channel, uint8_t selection);
334void adc_set_selection_sample_time(uint32_t adc, uint8_t selection, uint8_t time);
335
336void adc_enable_regulator(uint32_t adc);
337void adc_disable_regulator(uint32_t adc);
338
339END_DECLS
340
341/**@}*/
342
343#endif
344
adc_common_v2.h
adc_common_v2_single.h
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
adc_disable_regulator
void adc_disable_regulator(uint32_t adc)
Disable the ADC Voltage regulator.
Definition: adc.c:201
adc_set_clk_prescale
void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
ADC Set Clock Prescale.
Definition: adc.c:51
adc_set_selection_sample_time
void adc_set_selection_sample_time(uint32_t adc, uint8_t selection, uint8_t time)
ADC Set the Sample Time for Given Selection.
Definition: adc.c:100
adc_enable_regulator
void adc_enable_regulator(uint32_t adc)
Enable the ADC Voltage regulator.
Definition: adc.c:191
adc_set_channel_sample_time_selection
void adc_set_channel_sample_time_selection(uint32_t adc, uint8_t channel, uint8_t selection)
ADC Set the Sample Time Selection for a Single Channel.
Definition: adc.c:84
adc_set_clk_source
void adc_set_clk_source(uint32_t adc, uint32_t source)
ADC Set Clock Source.
Definition: adc.c:38