Collaboration diagram for ADC registers:

Macros
#define	ADC_AWD1TR(adc) MMIO32((adc) + 0x20)
	ADC_AWD1TR Watchdog 1 Threshold register. More...

#define	ADC_AWD2TR(adc) MMIO32((adc) + 0x22)
	ADC_AWD2TR Watchdog 2 Threshold register. More...

#define	ADC_AWD3TR(adc) MMIO32((adc) + 0x2c)
	ADC_AWD3TR Watchdog 3 Threshold register. More...

#define	ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)
	ADC_AWD2CR Watchdog 2 Configuration register. More...

#define	ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)
	ADC_AWD3CR Watchdog 3 Configuration register. More...

#define	ADC_CALFACT(adc) MMIO32((adc) + 0xB4)
	ADC_CALFACT Calibration factor register. More...

#define	ADC_ISR(adc) MMIO32((adc) + 0x00)
	ADC interrupt and status register. More...

#define	ADC_IER(adc) MMIO32((adc) + 0x04)
	Interrupt Enable Register. More...

#define	ADC_CR(adc) MMIO32((adc) + 0x08)
	Control Register. More...

#define	ADC_CFGR1(adc) MMIO32((adc) + 0x0C)
	Configuration Register 1. More...

#define	ADC_CFGR2(adc) MMIO32((adc) + 0x10)
	Configuration Register 2. More...

#define	ADC_SMPR1(adc) MMIO32((adc) + 0x14)
	Sample Time Register 1. More...

#define	ADC_TR1(adc) MMIO32((adc) + 0x20)
	Watchdog Threshold Register 1. More...

#define	ADC_DR(adc) MMIO32((adc) + 0x40)
	Regular Data Register. More...

#define	ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)
	Common Configuration register. More...

#define	ADC_CHSELR(adc) MMIO32((adc) + 0x28)
	Channel Select Register. More...

Detailed Description

Macro Definition Documentation

◆ ADC_AWD1TR

#define ADC_AWD1TR ( adc ) MMIO32((adc) + 0x20)

ADC_AWD1TR Watchdog 1 Threshold register.

Definition at line 54 of file g0/adc.h.

◆ ADC_AWD2CR

#define ADC_AWD2CR ( adc ) MMIO32((adc) + 0xA0)

ADC_AWD2CR Watchdog 2 Configuration register.

Definition at line 61 of file g0/adc.h.

◆ ADC_AWD2TR

#define ADC_AWD2TR ( adc ) MMIO32((adc) + 0x22)

ADC_AWD2TR Watchdog 2 Threshold register.

Definition at line 56 of file g0/adc.h.

◆ ADC_AWD3CR

#define ADC_AWD3CR ( adc ) MMIO32((adc) + 0xA4)

ADC_AWD3CR Watchdog 3 Configuration register.

Definition at line 63 of file g0/adc.h.

◆ ADC_AWD3TR

#define ADC_AWD3TR ( adc ) MMIO32((adc) + 0x2c)

ADC_AWD3TR Watchdog 3 Threshold register.

Definition at line 58 of file g0/adc.h.

◆ ADC_CALFACT

#define ADC_CALFACT ( adc ) MMIO32((adc) + 0xB4)

ADC_CALFACT Calibration factor register.

Definition at line 66 of file g0/adc.h.

◆ ADC_CCR

#define ADC_CCR ( adc ) MMIO32((adc) + 0x300 + 0x8)

Common Configuration register.

Definition at line 60 of file adc_common_v2.h.

◆ ADC_CFGR1

#define ADC_CFGR1 ( adc ) MMIO32((adc) + 0x0C)

Configuration Register 1.

Definition at line 48 of file adc_common_v2.h.

◆ ADC_CFGR2

#define ADC_CFGR2 ( adc ) MMIO32((adc) + 0x10)

Configuration Register 2.

Definition at line 50 of file adc_common_v2.h.

◆ ADC_CHSELR

#define ADC_CHSELR ( adc ) MMIO32((adc) + 0x28)

Channel Select Register.

Definition at line 49 of file adc_common_v2_single.h.

◆ ADC_CR

#define ADC_CR ( adc ) MMIO32((adc) + 0x08)

Control Register.

Definition at line 46 of file adc_common_v2.h.

◆ ADC_DR

#define ADC_DR ( adc ) MMIO32((adc) + 0x40)

Regular Data Register.

Definition at line 56 of file adc_common_v2.h.

◆ ADC_IER

#define ADC_IER ( adc ) MMIO32((adc) + 0x04)

Interrupt Enable Register.

Definition at line 44 of file adc_common_v2.h.

◆ ADC_ISR

#define ADC_ISR ( adc ) MMIO32((adc) + 0x00)

ADC interrupt and status register.

Definition at line 42 of file adc_common_v2.h.

◆ ADC_SMPR1

#define ADC_SMPR1 ( adc ) MMIO32((adc) + 0x14)

Sample Time Register 1.

Definition at line 52 of file adc_common_v2.h.

◆ ADC_TR1

#define ADC_TR1 ( adc ) MMIO32((adc) + 0x20)

Watchdog Threshold Register 1.

Definition at line 54 of file adc_common_v2.h.

Macros