libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Defined Constants and Types for the STM32G0xx Independent Watchdog Timer More...
Modules | |
IWDG Key Values | |
IWDG prescaler divider | |
IWDG Status Register Values | |
Macros | |
#define | IWDG_KR MMIO32(IWDG_BASE + 0x00) |
Key Register (IWDG_KR) More... | |
#define | IWDG_PR MMIO32(IWDG_BASE + 0x04) |
Prescaler register (IWDG_PR) More... | |
#define | IWDG_RLR MMIO32(IWDG_BASE + 0x08) |
Reload register (IWDG_RLR) More... | |
#define | IWDG_SR MMIO32(IWDG_BASE + 0x0c) |
Status register (IWDG_SR) More... | |
#define | IWDG_PR_LSB 0 |
#define | IWDG_WINR MMIO32(IWDG_BASE + 0x10) |
Window Register (IWDG_WINR) More... | |
Functions | |
void | iwdg_start (void) |
IWDG Enable Watchdog Timer. More... | |
void | iwdg_set_period_ms (uint32_t period) |
IWDG Set Period in Milliseconds. More... | |
bool | iwdg_reload_busy (void) |
IWDG Get Reload Register Status. More... | |
bool | iwdg_prescaler_busy (void) |
IWDG Get Prescaler Register Status. More... | |
void | iwdg_reset (void) |
IWDG reset Watchdog Timer. More... | |
Defined Constants and Types for the STM32G0xx Independent Watchdog Timer
LGPL License Terms libopencm3 License
Key Register (IWDG_KR)
Definition at line 40 of file iwdg_common_all.h.
Prescaler register (IWDG_PR)
Definition at line 43 of file iwdg_common_all.h.
#define IWDG_PR_LSB 0 |
Definition at line 70 of file iwdg_common_all.h.
Reload register (IWDG_RLR)
Definition at line 46 of file iwdg_common_all.h.
Status register (IWDG_SR)
Definition at line 49 of file iwdg_common_all.h.
Window Register (IWDG_WINR)
Definition at line 48 of file iwdg_common_v2.h.
bool iwdg_prescaler_busy | ( | void | ) |
IWDG Get Prescaler Register Status.
Definition at line 135 of file iwdg_common_all.c.
References IWDG_SR, and IWDG_SR_PVU.
Referenced by iwdg_set_period_ms().
bool iwdg_reload_busy | ( | void | ) |
IWDG Get Reload Register Status.
Definition at line 123 of file iwdg_common_all.c.
References IWDG_SR, and IWDG_SR_RVU.
Referenced by iwdg_set_period_ms().
void iwdg_reset | ( | void | ) |
IWDG reset Watchdog Timer.
The watchdog timer is reset. The counter restarts from the value in the reload register.
Definition at line 147 of file iwdg_common_all.c.
References IWDG_KR, and IWDG_KR_RESET.
Referenced by iwdg_set_period_ms().
void iwdg_set_period_ms | ( | uint32_t | period | ) |
IWDG Set Period in Milliseconds.
The countdown period is converted into count and prescale values. The maximum period is 32.76 seconds; values above this are truncated. Periods less than 1ms are not supported by this library.
A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value.
[in] | period | uint32_t Period in milliseconds (< 32760) from a watchdog reset until a system reset is issued. |
Definition at line 73 of file iwdg_common_all.c.
References COUNT_LENGTH, COUNT_MASK, IWDG_KR, IWDG_KR_UNLOCK, IWDG_PR, iwdg_prescaler_busy(), iwdg_reload_busy(), iwdg_reset(), and IWDG_RLR.
void iwdg_start | ( | void | ) |
IWDG Enable Watchdog Timer.
The watchdog timer is started. The timeout period defaults to 512 milliseconds unless it has been previously defined.
Definition at line 54 of file iwdg_common_all.c.
References IWDG_KR, and IWDG_KR_START.