libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
#define ADC1_BASE (PERIPH_BASE_APB + 0x12400) |
Definition at line 70 of file stm32/g0/memorymap.h.
#define AES_BASE (PERIPH_BASE_AHB + 0x06000) |
Definition at line 89 of file stm32/g0/memorymap.h.
#define CEC_BASE (PERIPH_BASE_APB + 0x7800) |
Definition at line 54 of file stm32/g0/memorymap.h.
#define COMP_BASE (PERIPH_BASE_APB + 0x10200) |
Definition at line 69 of file stm32/g0/memorymap.h.
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) |
Definition at line 87 of file stm32/g0/memorymap.h.
#define CRS_BASE (PERIPH_BASE_APB + 0x6c00) |
Definition at line 51 of file stm32/g0/memorymap.h.
#define DAC_BASE (PERIPH_BASE_APB + 0x7400) |
Definition at line 53 of file stm32/g0/memorymap.h.
#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) |
Definition at line 78 of file stm32/g0/memorymap.h.
#define DESIG_FLASH_SIZE_BASE (0x1FFF75E0) |
Definition at line 99 of file stm32/g0/memorymap.h.
#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) |
Definition at line 101 of file stm32/g0/memorymap.h.
#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) |
Definition at line 102 of file stm32/g0/memorymap.h.
#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) |
Definition at line 103 of file stm32/g0/memorymap.h.
#define DESIG_UNIQUE_ID_BASE (0x1FFF7590) |
Definition at line 100 of file stm32/g0/memorymap.h.
#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) |
Definition at line 81 of file stm32/g0/memorymap.h.
#define DMA2_BASE (PERIPH_BASE_AHB + 0x00400) |
Definition at line 82 of file stm32/g0/memorymap.h.
#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800) |
Definition at line 83 of file stm32/g0/memorymap.h.
#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800) |
Definition at line 85 of file stm32/g0/memorymap.h.
#define FDCAN1_BASE (PERIPH_BASE_APB + 0x6400) |
Definition at line 49 of file stm32/g0/memorymap.h.
#define FDCAN2_BASE (PERIPH_BASE_APB + 0x6800) |
Definition at line 50 of file stm32/g0/memorymap.h.
#define FDCANMSG_BASE (PERIPH_BASE_APB + 0xB400) |
Definition at line 65 of file stm32/g0/memorymap.h.
#define FLASH_BASE (0x08000000U) |
Definition at line 23 of file stm32/g0/memorymap.h.
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) |
Definition at line 86 of file stm32/g0/memorymap.h.
#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) |
Definition at line 91 of file stm32/g0/memorymap.h.
#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) |
Definition at line 92 of file stm32/g0/memorymap.h.
#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) |
Definition at line 93 of file stm32/g0/memorymap.h.
#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) |
Definition at line 94 of file stm32/g0/memorymap.h.
#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000) |
Definition at line 95 of file stm32/g0/memorymap.h.
#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400) |
Definition at line 96 of file stm32/g0/memorymap.h.
#define I2C1_BASE (PERIPH_BASE_APB + 0x5400) |
Definition at line 46 of file stm32/g0/memorymap.h.
#define I2C2_BASE (PERIPH_BASE_APB + 0x5800) |
Definition at line 47 of file stm32/g0/memorymap.h.
#define I2C3_BASE (PERIPH_BASE_APB + 0x8800) |
Definition at line 58 of file stm32/g0/memorymap.h.
#define INFO_BASE (0x1fff7500U) |
Definition at line 26 of file stm32/g0/memorymap.h.
#define IOPORT_BASE (0x50000000U) |
Definition at line 25 of file stm32/g0/memorymap.h.
#define IWDG_BASE (PERIPH_BASE_APB + 0x3000) |
Definition at line 39 of file stm32/g0/memorymap.h.
#define LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00) |
Definition at line 55 of file stm32/g0/memorymap.h.
#define LPTIM2_BASE (PERIPH_BASE_APB + 0x9400) |
Definition at line 59 of file stm32/g0/memorymap.h.
#define LPUART1_BASE (PERIPH_BASE_APB + 0x8000) |
Definition at line 56 of file stm32/g0/memorymap.h.
#define LPUART2_BASE (PERIPH_BASE_APB + 0x8400) |
Definition at line 57 of file stm32/g0/memorymap.h.
#define PERIPH_BASE (0x40000000U) |
Definition at line 24 of file stm32/g0/memorymap.h.
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) |
Definition at line 28 of file stm32/g0/memorymap.h.
#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000) |
Definition at line 27 of file stm32/g0/memorymap.h.
#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) |
Definition at line 52 of file stm32/g0/memorymap.h.
#define RCC_BASE (PERIPH_BASE_AHB + 0x01000) |
Definition at line 84 of file stm32/g0/memorymap.h.
#define RNG_BASE (PERIPH_BASE_AHB + 0x05000) |
Definition at line 88 of file stm32/g0/memorymap.h.
#define RTC_BASE (PERIPH_BASE_APB + 0x2800) |
Definition at line 37 of file stm32/g0/memorymap.h.
#define SPI1_BASE (PERIPH_BASE_APB + 0x13000) |
Definition at line 72 of file stm32/g0/memorymap.h.
#define SPI2_BASE (PERIPH_BASE_APB + 0x3800) |
Definition at line 40 of file stm32/g0/memorymap.h.
#define SPI3_BASE (PERIPH_BASE_APB + 0x3c00) |
Definition at line 41 of file stm32/g0/memorymap.h.
Definition at line 107 of file stm32/g0/memorymap.h.
Definition at line 108 of file stm32/g0/memorymap.h.
Definition at line 106 of file stm32/g0/memorymap.h.
#define SYSCFG_BASE (PERIPH_BASE_APB + 0x10000) |
Definition at line 66 of file stm32/g0/memorymap.h.
#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080) |
Definition at line 68 of file stm32/g0/memorymap.h.
#define TAMP_BASE (PERIPH_BASE_APB + 0xB000) |
Definition at line 64 of file stm32/g0/memorymap.h.
#define TIM14_BASE (PERIPH_BASE_APB + 0x2000) |
Definition at line 36 of file stm32/g0/memorymap.h.
#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) |
Definition at line 75 of file stm32/g0/memorymap.h.
#define TIM16_BASE (PERIPH_BASE_APB + 0x14400) |
Definition at line 76 of file stm32/g0/memorymap.h.
#define TIM17_BASE (PERIPH_BASE_APB + 0x14800) |
Definition at line 77 of file stm32/g0/memorymap.h.
#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) |
Definition at line 71 of file stm32/g0/memorymap.h.
#define TIM2_BASE (PERIPH_BASE_APB + 0x0000) |
Definition at line 31 of file stm32/g0/memorymap.h.
#define TIM3_BASE (PERIPH_BASE_APB + 0x0400) |
Definition at line 32 of file stm32/g0/memorymap.h.
#define TIM4_BASE (PERIPH_BASE_APB + 0x0800) |
Definition at line 33 of file stm32/g0/memorymap.h.
#define TIM6_BASE (PERIPH_BASE_APB + 0x1000) |
Definition at line 34 of file stm32/g0/memorymap.h.
#define TIM7_BASE (PERIPH_BASE_APB + 0x1400) |
Definition at line 35 of file stm32/g0/memorymap.h.
#define UCPD1_BASE (PERIPH_BASE_APB + 0xA000) |
Definition at line 62 of file stm32/g0/memorymap.h.
#define UCPD2_BASE (PERIPH_BASE_APB + 0xA400) |
Definition at line 63 of file stm32/g0/memorymap.h.
#define USART1_BASE (PERIPH_BASE_APB + 0x13800) |
Definition at line 73 of file stm32/g0/memorymap.h.
#define USART2_BASE (PERIPH_BASE_APB + 0x4400) |
Definition at line 42 of file stm32/g0/memorymap.h.
#define USART3_BASE (PERIPH_BASE_APB + 0x4800) |
Definition at line 43 of file stm32/g0/memorymap.h.
#define USART4_BASE (PERIPH_BASE_APB + 0x4C00) |
Definition at line 44 of file stm32/g0/memorymap.h.
#define USART5_BASE (PERIPH_BASE_APB + 0x5000) |
Definition at line 45 of file stm32/g0/memorymap.h.
#define USART6_BASE (PERIPH_BASE_APB + 0x13c00) |
Definition at line 74 of file stm32/g0/memorymap.h.
#define USB_BASE (PERIPH_BASE_APB + 0x5c00) |
Definition at line 48 of file stm32/g0/memorymap.h.
#define USB_RAM1_BASE (PERIPH_BASE_APB + 0x9800) |
Definition at line 60 of file stm32/g0/memorymap.h.
#define USB_RAM2_BASE (PERIPH_BASE_APB + 0x9c00) |
Definition at line 61 of file stm32/g0/memorymap.h.
#define VREFBUF_BASE (PERIPH_BASE_APB + 0x10030) |
Definition at line 67 of file stm32/g0/memorymap.h.
#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) |
Definition at line 38 of file stm32/g0/memorymap.h.