libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/g0/memorymap.h
Go to the documentation of this file.
1/*
2 * This file is part of the libopencm3 project.
3 *
4 * This library is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU Lesser General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public License
15 * along with this library. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef LIBOPENCM3_MEMORYMAP_H
19#define LIBOPENCM3_MEMORYMAP_H
20
22
23#define FLASH_BASE (0x08000000U)
24#define PERIPH_BASE (0x40000000U)
25#define IOPORT_BASE (0x50000000U)
26#define INFO_BASE (0x1fff7500U)
27#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000)
28#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
29
30/* APB */
31#define TIM2_BASE (PERIPH_BASE_APB + 0x0000)
32#define TIM3_BASE (PERIPH_BASE_APB + 0x0400)
33#define TIM4_BASE (PERIPH_BASE_APB + 0x0800)
34#define TIM6_BASE (PERIPH_BASE_APB + 0x1000)
35#define TIM7_BASE (PERIPH_BASE_APB + 0x1400)
36#define TIM14_BASE (PERIPH_BASE_APB + 0x2000)
37#define RTC_BASE (PERIPH_BASE_APB + 0x2800)
38#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00)
39#define IWDG_BASE (PERIPH_BASE_APB + 0x3000)
40#define SPI2_BASE (PERIPH_BASE_APB + 0x3800)
41#define SPI3_BASE (PERIPH_BASE_APB + 0x3c00)
42#define USART2_BASE (PERIPH_BASE_APB + 0x4400)
43#define USART3_BASE (PERIPH_BASE_APB + 0x4800)
44#define USART4_BASE (PERIPH_BASE_APB + 0x4C00)
45#define USART5_BASE (PERIPH_BASE_APB + 0x5000)
46#define I2C1_BASE (PERIPH_BASE_APB + 0x5400)
47#define I2C2_BASE (PERIPH_BASE_APB + 0x5800)
48#define USB_BASE (PERIPH_BASE_APB + 0x5c00)
49#define FDCAN1_BASE (PERIPH_BASE_APB + 0x6400)
50#define FDCAN2_BASE (PERIPH_BASE_APB + 0x6800)
51#define CRS_BASE (PERIPH_BASE_APB + 0x6c00)
52#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)
53#define DAC_BASE (PERIPH_BASE_APB + 0x7400)
54#define CEC_BASE (PERIPH_BASE_APB + 0x7800)
55#define LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)
56#define LPUART1_BASE (PERIPH_BASE_APB + 0x8000)
57#define LPUART2_BASE (PERIPH_BASE_APB + 0x8400)
58#define I2C3_BASE (PERIPH_BASE_APB + 0x8800)
59#define LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)
60#define USB_RAM1_BASE (PERIPH_BASE_APB + 0x9800)
61#define USB_RAM2_BASE (PERIPH_BASE_APB + 0x9c00)
62#define UCPD1_BASE (PERIPH_BASE_APB + 0xA000)
63#define UCPD2_BASE (PERIPH_BASE_APB + 0xA400)
64#define TAMP_BASE (PERIPH_BASE_APB + 0xB000)
65#define FDCANMSG_BASE (PERIPH_BASE_APB + 0xB400)
66#define SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)
67#define VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)
68#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)
69#define COMP_BASE (PERIPH_BASE_APB + 0x10200)
70#define ADC1_BASE (PERIPH_BASE_APB + 0x12400)
71#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00)
72#define SPI1_BASE (PERIPH_BASE_APB + 0x13000)
73#define USART1_BASE (PERIPH_BASE_APB + 0x13800)
74#define USART6_BASE (PERIPH_BASE_APB + 0x13c00)
75#define TIM15_BASE (PERIPH_BASE_APB + 0x14000)
76#define TIM16_BASE (PERIPH_BASE_APB + 0x14400)
77#define TIM17_BASE (PERIPH_BASE_APB + 0x14800)
78#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)
79
80/* AHB */
81#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000)
82#define DMA2_BASE (PERIPH_BASE_AHB + 0x00400)
83#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)
84#define RCC_BASE (PERIPH_BASE_AHB + 0x01000)
85#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800)
86#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)
87#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
88#define RNG_BASE (PERIPH_BASE_AHB + 0x05000)
89#define AES_BASE (PERIPH_BASE_AHB + 0x06000)
90
91#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)
92#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)
93#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)
94#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)
95#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)
96#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)
97
98/* Device Electronic Signature */
99#define DESIG_FLASH_SIZE_BASE (0x1FFF75E0)
100#define DESIG_UNIQUE_ID_BASE (0x1FFF7590)
101#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
102#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
103#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
104
105/* ST provided factory calibration values @ 3.0V */
106#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))
107#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))
108#define ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))
109
110#endif