Collaboration diagram for PWR Registers:

Macros
#define	PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
	Power control register 1 (PWR_CR1) More...

#define	PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)
	Power control register 2 (PWR_CR2) More...

#define	PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)
	Power control register 3 (PWR_CR3) More...

#define	PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)
	Power control register 4 (PWR_CR4) More...

#define	PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)
	Power status register 1 (PWR_SR1) More...

#define	PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)
	Power status registery 2 (PWR_SR2) More...

#define	PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)
	Power status clear register (PWR_SCR) More...

#define	PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)

#define	PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)

#define	PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)

#define	PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)

#define	PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)

#define	PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)

#define	PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)

#define	PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)

Detailed Description

Macro Definition Documentation

◆ PWR_CR1

#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)

Power control register 1 (PWR_CR1)

Definition at line 35 of file g0/pwr.h.

◆ PWR_CR2

#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)

Power control register 2 (PWR_CR2)

Definition at line 38 of file g0/pwr.h.

◆ PWR_CR3

#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)

Power control register 3 (PWR_CR3)

Definition at line 41 of file g0/pwr.h.

◆ PWR_CR4

#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)

Power control register 4 (PWR_CR4)

Definition at line 44 of file g0/pwr.h.

◆ PWR_PDCR

#define PWR_PDCR ( pwr_port ) MMIO32((pwr_port) + 0x04)

Definition at line 63 of file g0/pwr.h.

◆ PWR_PORT_A

#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)

Definition at line 55 of file g0/pwr.h.

◆ PWR_PORT_B

#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)

Definition at line 56 of file g0/pwr.h.

◆ PWR_PORT_C

#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)

Definition at line 57 of file g0/pwr.h.

◆ PWR_PORT_D

#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)

Definition at line 58 of file g0/pwr.h.

◆ PWR_PORT_E

#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)

Definition at line 59 of file g0/pwr.h.

◆ PWR_PORT_F

#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)

Definition at line 60 of file g0/pwr.h.

◆ PWR_PUCR

#define PWR_PUCR ( pwr_port ) MMIO32((pwr_port) + 0x00)

Definition at line 62 of file g0/pwr.h.

◆ PWR_SCR

#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)

Power status clear register (PWR_SCR)

Definition at line 53 of file g0/pwr.h.

◆ PWR_SR1

#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)

Power status register 1 (PWR_SR1)

Definition at line 47 of file g0/pwr.h.

◆ PWR_SR2

#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)

Power status registery 2 (PWR_SR2)

Definition at line 50 of file g0/pwr.h.

Macros