CFGR Configuration Register
Collaboration diagram for CFGR Configuration Register:
Modules | |
| MCO Pre | |
| Division factor of microcontroler clock output. | |
| MCO Sel | |
| Microcontroler clock output selector. | |
| PPRE | |
| APB Prescaler. | |
| HPRE | |
| APB Prescaler. | |
| SWS | |
| System clock switch status. | |
| SW | |
| System clock switch. | |
Macros | |
| #define | RCC_CFGR_MCOPRE_SHIFT 28 |
| #define | RCC_CFGR_MCOPRE_MASK 0x7 |
| #define | RCC_CFGR_MCO_SHIFT 24 |
| #define | RCC_CFGR_MCO_MASK 0xf |
| #define | RCC_CFGR_PPRE_MASK 0x7 |
| #define | RCC_CFGR_PPRE_SHIFT 12 |
| #define | RCC_CFGR_HPRE_MASK 0xf |
| #define | RCC_CFGR_HPRE_SHIFT 8 |
| #define | RCC_CFGR_SWS_MASK 0x3 |
| #define | RCC_CFGR_SWS_SHIFT 3 |
| #define | RCC_CFGR_SW_MASK 0x3 |
| #define | RCC_CFGR_SW_SHIFT 0 |
