RCC Defines

Defined Constants and Types for the STM32G0xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	Reset and Clock Control Register
	CR Clock control Register
	ICSCR Internal Clock Source Calibration Register
	CFGR Configuration Register
	PLLCFGR PLL Configuration Register
	CIER Clock Interrupt Enable Register
	CIFR Clock Interrupt Flag Register
	CICR Clock Interrupt Clear Register
	RCC_AHBRSTR reset values
	RCC_APBRSTRx reset values (full set)
	RCC_AHBENR enable values
	RCC_APBENRx enable values (full set)
	RCC_AHBSMENR enable in sleep/stop mode values
	RCC_APBSMENR1 enable in sleep/stop mode values
	RCC_APBSMENR2 enable in sleep/stop mode values
	CCIPR Peripherals Independent Clock Config Register
	BDCR Backup Domain Control Register
	CSR Control and Status Register

Macros
#define	rcc_apb2_frequency   rcc_apb1_frequency
#define	_REG_BIT(offset, bit)   (((offset) << 5) + (bit))

Enumerations
enum	rcc_osc {   RCC_HSI , RCC_HSE , RCC_PLL , RCC_LSE ,   RCC_LSI }
enum	rcc_periph_clken {   RCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5) , RCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4) , RCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3) , RCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2) ,   RCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1) , RCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0) , RCC_RNG = _REG_BIT(RCC_AHBENR_OFFSET, 18) , RCC_AES = _REG_BIT(RCC_AHBENR_OFFSET, 16) ,   RCC_CRC = _REG_BIT(RCC_AHBENR_OFFSET, 12) , RCC_FLASH = _REG_BIT(RCC_AHBENR_OFFSET, 8) , RCC_DMA2 = _REG_BIT(RCC_AHBENR_OFFSET, 1) , RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0) ,   RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0) , RCC_LPTIM1 = _REG_BIT(RCC_APBENR1_OFFSET, 31) , RCC_LPTIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 30) , RCC_DAC1 = _REG_BIT(RCC_APBENR1_OFFSET, 29) ,   RCC_PWR = _REG_BIT(RCC_APBENR1_OFFSET, 28) , RCC_DBG = _REG_BIT(RCC_APBENR1_OFFSET, 27) , RCC_UCPD2 = _REG_BIT(RCC_APBENR1_OFFSET, 26) , RCC_UCPD1 = _REG_BIT(RCC_APBENR1_OFFSET, 25) ,   RCC_CEC = _REG_BIT(RCC_APBENR1_OFFSET, 24) , RCC_I2C3 = _REG_BIT(RCC_APBENR1_OFFSET, 23) , RCC_I2C2 = _REG_BIT(RCC_APBENR1_OFFSET, 22) , RCC_I2C1 = _REG_BIT(RCC_APBENR1_OFFSET, 21) ,   RCC_LPUART1 = _REG_BIT(RCC_APBENR1_OFFSET, 20) , RCC_USART4 = _REG_BIT(RCC_APBENR1_OFFSET, 19) , RCC_USART3 = _REG_BIT(RCC_APBENR1_OFFSET, 18) , RCC_USART2 = _REG_BIT(RCC_APBENR1_OFFSET, 17) ,   RCC_CRS = _REG_BIT(RCC_APBENR1_OFFSET, 16) , RCC_SPI3 = _REG_BIT(RCC_APBENR1_OFFSET, 15) , RCC_SPI2 = _REG_BIT(RCC_APBENR1_OFFSET, 14) , RCC_USB = _REG_BIT(RCC_APBENR1_OFFSET, 13) ,   RCC_FDCAN = _REG_BIT(RCC_APBENR1_OFFSET, 12) , RCC_WWDG = _REG_BIT(RCC_APBENR1_OFFSET, 11) , RCC_RTCAPB = _REG_BIT(RCC_APBENR1_OFFSET, 10) , RCC_USART6 = _REG_BIT(RCC_APBENR1_OFFSET, 9) ,   RCC_USART5 = _REG_BIT(RCC_APBENR1_OFFSET, 8) , RCC_LPUART2 = _REG_BIT(RCC_APBENR1_OFFSET, 7) , RCC_TIM7 = _REG_BIT(RCC_APBENR1_OFFSET, 5) , RCC_TIM6 = _REG_BIT(RCC_APBENR1_OFFSET, 4) ,   RCC_TIM4 = _REG_BIT(RCC_APBENR1_OFFSET, 2) , RCC_TIM3 = _REG_BIT(RCC_APBENR1_OFFSET, 1) , RCC_TIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 0) , RCC_ADC = _REG_BIT(RCC_APBENR2_OFFSET, 20) ,   RCC_TIM17 = _REG_BIT(RCC_APBENR2_OFFSET, 18) , RCC_TIM16 = _REG_BIT(RCC_APBENR2_OFFSET, 17) , RCC_TIM15 = _REG_BIT(RCC_APBENR2_OFFSET, 16) , RCC_TIM14 = _REG_BIT(RCC_APBENR2_OFFSET, 15) ,   RCC_USART1 = _REG_BIT(RCC_APBENR2_OFFSET, 14) , RCC_SPI1 = _REG_BIT(RCC_APBENR2_OFFSET, 12) , RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11) , RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0) ,   SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5) , SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4) , SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3) , SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2) ,   SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1) , SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0) , SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18) , SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16) ,   SCC_CRC = _REG_BIT(RCC_AHBSMENR_OFFSET, 12) , SCC_SRAM = _REG_BIT(RCC_AHBSMENR_OFFSET, 9) , SCC_FLASH = _REG_BIT(RCC_AHBSMENR_OFFSET, 8) , SCC_DMA2 = _REG_BIT(RCC_AHBSMENR_OFFSET, 1) ,   SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0) , SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0) , SCC_LPTIM1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 31) , SCC_LPTIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 30) ,   SCC_DAC1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 29) , SCC_PWR = _REG_BIT(RCC_APBSMENR1_OFFSET, 28) , SCC_DBG = _REG_BIT(RCC_APBSMENR1_OFFSET, 27) , SCC_UCPD2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 26) ,   SCC_UCPD1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 25) , SCC_CEC = _REG_BIT(RCC_APBSMENR1_OFFSET, 24) , SCC_I2C3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 23) , SCC_I2C2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 22) ,   SCC_I2C1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 21) , SCC_LPUART1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 20) , SCC_USART4 = _REG_BIT(RCC_APBSMENR1_OFFSET, 19) , SCC_USART3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 18) ,   SCC_USART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 17) , SCC_CRS = _REG_BIT(RCC_APBSMENR1_OFFSET, 16) , SCC_SPI3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 15) , SCC_SPI2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 14) ,   SCC_USB = _REG_BIT(RCC_APBSMENR1_OFFSET, 13) , SCC_FDCAN = _REG_BIT(RCC_APBSMENR1_OFFSET, 12) , SCC_WWDG = _REG_BIT(RCC_APBSMENR1_OFFSET, 11) , SCC_RTCAPB = _REG_BIT(RCC_APBSMENR1_OFFSET, 10) ,   SCC_USART6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 9) , SCC_USART5 = _REG_BIT(RCC_APBSMENR1_OFFSET, 8) , SCC_LPUART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 7) , SCC_TIM7 = _REG_BIT(RCC_APBSMENR1_OFFSET, 5) ,   SCC_TIM6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 4) , SCC_TIM3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 1) , SCC_TIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 0) , SCC_ADC = _REG_BIT(RCC_APBSMENR2_OFFSET, 20) ,   SCC_TIM17 = _REG_BIT(RCC_APBSMENR2_OFFSET, 18) , SCC_TIM16 = _REG_BIT(RCC_APBSMENR2_OFFSET, 17) , SCC_TIM15 = _REG_BIT(RCC_APBSMENR2_OFFSET, 16) , SCC_TIM14 = _REG_BIT(RCC_APBSMENR2_OFFSET, 15) ,   SCC_USART1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 14) , SCC_SPI1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 12) , SCC_TIM1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 11) , SCC_SYSCFG = _REG_BIT(RCC_APBSMENR2_OFFSET, 0) }
enum	rcc_periph_rst {   RST_GPIOF = _REG_BIT(RCC_IOPRSTR_OFFSET, 5) , RST_GPIOE = _REG_BIT(RCC_IOPRSTR_OFFSET, 4) , RST_GPIOD = _REG_BIT(RCC_IOPRSTR_OFFSET, 3) , RST_GPIOC = _REG_BIT(RCC_IOPRSTR_OFFSET, 2) ,   RST_GPIOB = _REG_BIT(RCC_IOPRSTR_OFFSET, 1) , RST_GPIOA = _REG_BIT(RCC_IOPRSTR_OFFSET, 0) , RST_RNG = _REG_BIT(RCC_AHBRSTR_OFFSET, 18) , RST_AES = _REG_BIT(RCC_AHBRSTR_OFFSET, 16) ,   RST_CRC = _REG_BIT(RCC_AHBRSTR_OFFSET, 12) , RST_FLASH = _REG_BIT(RCC_AHBRSTR_OFFSET, 8) , RST_DMA2 = _REG_BIT(RCC_AHBRSTR_OFFSET, 1) , RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0) ,   RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0) , RST_LPTIM1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 31) , RST_LPTIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 30) , RST_DAC1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 29) ,   RST_PWR = _REG_BIT(RCC_APBRSTR1_OFFSET, 28) , RST_DBG = _REG_BIT(RCC_APBRSTR1_OFFSET, 27) , RST_UCPD2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 26) , RST_UCPD1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 25) ,   RST_CEC = _REG_BIT(RCC_APBRSTR1_OFFSET, 24) , RST_I2C3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 23) , RST_I2C2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 22) , RST_I2C1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 21) ,   RST_LPUART1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 20) , RST_USART4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 19) , RST_USART3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 18) , RST_USART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 17) ,   RST_CRS = _REG_BIT(RCC_APBRSTR1_OFFSET, 16) , RST_SPI3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 15) , RST_SPI2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 14) , RST_USB = _REG_BIT(RCC_APBRSTR1_OFFSET, 13) ,   RST_FDCAN = _REG_BIT(RCC_APBRSTR1_OFFSET, 12) , RST_USART6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 9) , RST_USART5 = _REG_BIT(RCC_APBRSTR1_OFFSET, 8) , RST_LPUART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 7) ,   RST_TIM7 = _REG_BIT(RCC_APBRSTR1_OFFSET, 5) , RST_TIM6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 4) , RST_TIM4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 2) , RST_TIM3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 1) ,   RST_TIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 0) , RST_ADC = _REG_BIT(RCC_APBRSTR2_OFFSET, 20) , RST_TIM17 = _REG_BIT(RCC_APBRSTR2_OFFSET, 18) , RST_TIM16 = _REG_BIT(RCC_APBRSTR2_OFFSET, 17) ,   RST_TIM15 = _REG_BIT(RCC_APBRSTR2_OFFSET, 16) , RST_TIM14 = _REG_BIT(RCC_APBRSTR2_OFFSET, 15) , RST_USART1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 14) , RST_SPI1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 12) ,   RST_TIM1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 11) , RST_SYSCFG = _REG_BIT(RCC_APBRSTR2_OFFSET, 0) }
enum	rcc_clock {   RCC_CLOCK_CONFIG_LSI_32KHZ , RCC_CLOCK_CONFIG_HSI_4MHZ , RCC_CLOCK_CONFIG_HSI_16MHZ , RCC_CLOCK_CONFIG_HSI_PLL_32MHZ ,   RCC_CLOCK_CONFIG_HSI_PLL_64MHZ , RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ , RCC_CLOCK_CONFIG_END }

Functions
void	rcc_osc_on (enum rcc_osc osc)
void	rcc_osc_off (enum rcc_osc osc)
void	rcc_css_enable (void)
void	rcc_css_disable (void)
void	rcc_css_int_clear (void)
int	rcc_css_int_flag (void)
void	rcc_set_sysclk_source (enum rcc_osc osc)
	Set the Source for the System Clock. More...
void	rcc_wait_for_sysclk_status (enum rcc_osc osc)
	Wait until system clock switched to given oscillator. More...
enum rcc_osc	rcc_system_clock_source (void)
	Return the clock source which is used as system clock. More...
void	rcc_set_pll_source (uint32_t pllsrc)
	Configure pll source. More...
void	rcc_set_main_pll (uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
	Configure pll source and output frequencies. More...
void	rcc_enable_pllp (bool enable)
	Enable PLL P clock output. More...
void	rcc_enable_pllq (bool enable)
	Enable PLL Q clock output. More...
void	rcc_enable_pllr (bool enable)
	Enable PLL R clock output. More...
void	rcc_set_ppre (uint32_t ppre)
	Configure APB peripheral clock prescaler. More...
void	rcc_set_hpre (uint32_t hpre)
	Configure AHB peripheral clock prescaler. More...
void	rcc_set_hsisys_div (uint32_t hsidiv)
	Configure HSI16 clock division factor to feed SYSCLK. More...
void	rcc_set_mcopre (uint32_t mcopre)
	Configure mco prescaler. More...
void	rcc_clock_setup (const struct rcc_clock_scale *clock)
	Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). More...
void	rcc_set_rng_clk_div (uint32_t rng_div)
	Setup RNG Peripheral Clock Divider. More...
void	rcc_set_peripheral_clk_sel (uint32_t periph, uint32_t sel)
	Set the peripheral clock source. More...
uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...
uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...
uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...
uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...
void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...
void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...
void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...
void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...
void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...
void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...
void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...
void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...
void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...
void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...
void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...
void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...
bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...
void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...
uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
uint32_t	rcc_ahb_frequency
uint32_t	rcc_apb1_frequency
const struct rcc_clock_scale	rcc_clock_config [RCC_CLOCK_CONFIG_END]

Detailed Description

Defined Constants and Types for the STM32G0xx Reset and Clock Control

Version

1.0.0

LGPL License Terms libopencm3 License

Author

© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

_REG_BIT

#define _REG_BIT	(		offset,
			bit
	)		(((offset) << 5) + (bit))

Definition at line 641 of file g0/rcc.h.

rcc_apb2_frequency

#define rcc_apb2_frequency   rcc_apb1_frequency

Definition at line 637 of file g0/rcc.h.

Enumeration Type Documentation

rcc_clock

enum rcc_clock

Enumerator
RCC_CLOCK_CONFIG_LSI_32KHZ
RCC_CLOCK_CONFIG_HSI_4MHZ
RCC_CLOCK_CONFIG_HSI_16MHZ
RCC_CLOCK_CONFIG_HSI_PLL_32MHZ
RCC_CLOCK_CONFIG_HSI_PLL_64MHZ
RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ
RCC_CLOCK_CONFIG_END

Definition at line 843 of file g0/rcc.h.

rcc_osc

enum rcc_osc

Enumerator
RCC_HSI
RCC_HSE
RCC_PLL
RCC_LSE
RCC_LSI

Definition at line 643 of file g0/rcc.h.

rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_GPIOF
RCC_GPIOE
RCC_GPIOD
RCC_GPIOC
RCC_GPIOB
RCC_GPIOA
RCC_RNG
RCC_AES
RCC_CRC
RCC_FLASH
RCC_DMA2
RCC_DMA1
RCC_DMA
RCC_LPTIM1
RCC_LPTIM2
RCC_DAC1
RCC_PWR
RCC_DBG
RCC_UCPD2
RCC_UCPD1
RCC_CEC
RCC_I2C3
RCC_I2C2
RCC_I2C1
RCC_LPUART1
RCC_USART4
RCC_USART3
RCC_USART2
RCC_CRS
RCC_SPI3
RCC_SPI2
RCC_USB
RCC_FDCAN
RCC_WWDG
RCC_RTCAPB
RCC_USART6
RCC_USART5
RCC_LPUART2
RCC_TIM7
RCC_TIM6
RCC_TIM4
RCC_TIM3
RCC_TIM2
RCC_ADC
RCC_TIM17
RCC_TIM16
RCC_TIM15
RCC_TIM14
RCC_USART1
RCC_SPI1
RCC_TIM1
RCC_SYSCFG
SCC_GPIOF
SCC_GPIOE
SCC_GPIOD
SCC_GPIOC
SCC_GPIOB
SCC_GPIOA
SCC_RNG
SCC_AES
SCC_CRC
SCC_SRAM
SCC_FLASH
SCC_DMA2
SCC_DMA1
SCC_DMA
SCC_LPTIM1
SCC_LPTIM2
SCC_DAC1
SCC_PWR
SCC_DBG
SCC_UCPD2
SCC_UCPD1
SCC_CEC
SCC_I2C3
SCC_I2C2
SCC_I2C1
SCC_LPUART1
SCC_USART4
SCC_USART3
SCC_USART2
SCC_CRS
SCC_SPI3
SCC_SPI2
SCC_USB
SCC_FDCAN
SCC_WWDG
SCC_RTCAPB
SCC_USART6
SCC_USART5
SCC_LPUART2
SCC_TIM7
SCC_TIM6
SCC_TIM3
SCC_TIM2
SCC_ADC
SCC_TIM17
SCC_TIM16
SCC_TIM15
SCC_TIM14
SCC_USART1
SCC_SPI1
SCC_TIM1
SCC_SYSCFG

Definition at line 651 of file g0/rcc.h.

rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_GPIOF
RST_GPIOE
RST_GPIOD
RST_GPIOC
RST_GPIOB
RST_GPIOA
RST_RNG
RST_AES
RST_CRC
RST_FLASH
RST_DMA2
RST_DMA1
RST_DMA
RST_LPTIM1
RST_LPTIM2
RST_DAC1
RST_PWR
RST_DBG
RST_UCPD2
RST_UCPD1
RST_CEC
RST_I2C3
RST_I2C2
RST_I2C1
RST_LPUART1
RST_USART4
RST_USART3
RST_USART2
RST_CRS
RST_SPI3
RST_SPI2
RST_USB
RST_FDCAN
RST_USART6
RST_USART5
RST_LPUART2
RST_TIM7
RST_TIM6
RST_TIM4
RST_TIM3
RST_TIM2
RST_ADC
RST_TIM17
RST_TIM16
RST_TIM15
RST_TIM14
RST_USART1
RST_SPI1
RST_TIM1
RST_SYSCFG

Definition at line 765 of file g0/rcc.h.

Function Documentation

rcc_clock_setup()

void rcc_clock_setup

(

const struct rcc_clock_scale *

clock

)

Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI).

taking care of flash/pwr and src configuration

Parameters

clock

rcc_clock_scale with desired parameters

Definition at line 439 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb_frequency, FLASH_ACR_LATENCY_0WS, flash_prefetch_disable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::hsisys_div, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::pllp_div, rcc_clock_scale::pllq_div, rcc_clock_scale::pllr_div, rcc_clock_scale::ppre, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_enable_pllr(), RCC_HSE, RCC_HSI, rcc_is_osc_ready(), rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PLLCFGR_PLLSRC_HSE, RCC_PWR, rcc_set_hpre(), rcc_set_hsisys_div(), rcc_set_main_pll(), rcc_set_ppre(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), rcc_wait_for_sysclk_status(), rcc_clock_scale::sysclock_source, and rcc_clock_scale::voltage_scale.

Here is the call graph for this function:

rcc_css_disable()

void rcc_css_disable

(

void

)

Definition at line 206 of file rcc.c.

References RCC_CR.

rcc_css_enable()

void rcc_css_enable

(

void

)

Definition at line 201 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

rcc_css_int_clear()

void rcc_css_int_clear

(

void

)

Definition at line 211 of file rcc.c.

References RCC_CICR, and RCC_CICR_CSSC.

rcc_css_int_flag()

int rcc_css_int_flag

(

void

)

Definition at line 216 of file rcc.c.

References RCC_CIFR, and RCC_CIFR_CSSF.

rcc_enable_pllp()

void rcc_enable_pllp

(

bool

enable

)

Enable PLL P clock output.

Parameters

[in]

enable

or disable P clock output

Definition at line 348 of file rcc.c.

References RCC_PLLCFGR, and RCC_PLLCFGR_PLLPEN.

rcc_enable_pllq()

void rcc_enable_pllq

(

bool

enable

)

Enable PLL Q clock output.

Parameters

[in]

enable

or disable Q clock output

Definition at line 361 of file rcc.c.

References RCC_PLLCFGR, and RCC_PLLCFGR_PLLQEN.

rcc_enable_pllr()

void rcc_enable_pllr

(

bool

enable

)

Enable PLL R clock output.

Parameters

[in]

enable

or disable R clock output

Definition at line 374 of file rcc.c.

References RCC_PLLCFGR, and RCC_PLLCFGR_PLLREN.

Referenced by rcc_clock_setup().

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rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre

(

uint8_t

div_val

)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val

Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_get_clksel_freq().

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rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq

(

uint32_t

i2c

)

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 601 of file rcc.c.

References cm3_assert_not_reached, I2C1_BASE, I2C2_BASE, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C2SEL_SHIFT, and rcc_get_clksel_freq().

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rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq

(

uint32_t

spi

)

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 615 of file rcc.c.

References rcc_apb1_frequency.

rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq

(

uint32_t

timer

)

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer

Base address of TIM to get clock frequency for.

Definition at line 590 of file rcc.c.

References rcc_clock_scale::ppre, rcc_apb1_frequency, RCC_CFGR, RCC_CFGR_PPRE_MASK, RCC_CFGR_PPRE_NODIV, and RCC_CFGR_PPRE_SHIFT.

rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq

(

uint32_t

usart

)

Get the peripheral clock speed for the USART at base specified.

Parameters

usart

Base address of USART to get clock frequency for.

Definition at line 570 of file rcc.c.

References cm3_assert_not_reached, LPUART1_BASE, LPUART2_BASE, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_LPUART2SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_get_clksel_freq(), USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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rcc_is_osc_ready()

bool rcc_is_osc_ready

(

enum rcc_osc

osc

)

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns

true if the hardware indicates the oscillator is ready.

Definition at line 176 of file rcc.c.

References cm3_assert_not_reached, RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup(), and rcc_wait_for_osc_ready().

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rcc_osc_bypass_disable()

void rcc_osc_bypass_disable

(

enum rcc_osc

osc

)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note

The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in]

osc

Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

rcc_osc_bypass_enable()

void rcc_osc_bypass_enable

(

enum rcc_osc

osc

)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note

The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in]

osc

Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

rcc_osc_off()

void rcc_osc_off

(

enum rcc_osc

osc

)

Definition at line 152 of file rcc.c.

References cm3_assert_not_reached, RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup().

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rcc_osc_on()

void rcc_osc_on

(

enum rcc_osc

osc

)

Definition at line 128 of file rcc.c.

References cm3_assert_not_reached, RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup().

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rcc_periph_clock_disable()

void rcc_periph_clock_disable

(

enum rcc_periph_clken

clken

)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in]

clken

rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

rcc_periph_clock_enable()

void rcc_periph_clock_enable

(

enum rcc_periph_clken

clken

)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in]

clken

rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by rcc_clock_setup().

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rcc_periph_reset_hold()

void rcc_periph_reset_hold

(

enum rcc_periph_rst

rst

)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in]

rst

rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

rcc_periph_reset_pulse()

void rcc_periph_reset_pulse

(

enum rcc_periph_rst

rst

)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in]

rst

rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

rcc_periph_reset_release()

void rcc_periph_reset_release

(

enum rcc_periph_rst

rst

)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in]

rst

rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also

rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.

rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APBRSTRx reset values (full set) If register is RCC_APB2RSTR, from rcc_apb2rstr_rst

Definition at line 111 of file rcc_common_all.c.

rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also

rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APBENRx enable values (full set) If register is RCC_APB2ENR, from rcc_apb2enr_en

Definition at line 66 of file rcc_common_all.c.

rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also

rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APBENRx enable values (full set) If register is RCC_APB2ENR, from rcc_apb2enr_en

Definition at line 44 of file rcc_common_all.c.

rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also

rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.

rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APBRSTRx reset values (full set) If register is RCC_APB2RSTR, from rcc_apb2rstr_rst

Definition at line 88 of file rcc_common_all.c.

rcc_set_hpre()

void rcc_set_hpre

(

uint32_t

hpre

)

Configure AHB peripheral clock prescaler.

Parameters

[in]

hpre

AHB clock prescaler value HPRE

Definition at line 400 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup().

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rcc_set_hsisys_div()

void rcc_set_hsisys_div

(

uint32_t

hsidiv

)

Configure HSI16 clock division factor to feed SYSCLK.

Parameters

[in]

hsidiv

HSYSSIS clock division factor HSI Div

Definition at line 413 of file rcc.c.

References RCC_CR, RCC_CR_HSIDIV_MASK, and RCC_CR_HSIDIV_SHIFT.

Referenced by rcc_clock_setup().

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rcc_set_main_pll()

void rcc_set_main_pll	(	uint32_t	source,
		uint32_t	pllm,
		uint32_t	plln,
		uint32_t	pllp,
		uint32_t	pllq,
		uint32_t	pllr
	)

Configure pll source and output frequencies.

Parameters

[in]	source	pll clock source PLLSRC
[in]	pllm	pll vco division factor PLLM
[in]	plln	pll vco multiplation factor PLLN
[in]	pllp	pll P clock output division factor PLLP
[in]	pllq	pll Q clock output division factor PLLQ
[in]	pllr	pll R clock output (sysclock pll) division factor PLLR

Definition at line 333 of file rcc.c.

References RCC_PLLCFGR, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLP_SHIFT, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_SHIFT, and RCC_PLLCFGR_PLLSRC_SHIFT.

Referenced by rcc_clock_setup().

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rcc_set_mco()

void rcc_set_mco

(

uint32_t

mcosrc

)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in]

mcosrc

the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

rcc_set_mcopre()

void rcc_set_mcopre

(

uint32_t

mcopre

)

Configure mco prescaler.

Parameters

[in]

mcopre

prescaler value MCO Pre

Definition at line 426 of file rcc.c.

References RCC_CFGR, RCC_CFGR_MCOPRE_MASK, and RCC_CFGR_MCOPRE_SHIFT.

rcc_set_peripheral_clk_sel()

void rcc_set_peripheral_clk_sel	(	uint32_t	periph,
		uint32_t	sel
	)

Set the peripheral clock source.

Parameters

periph	peripheral of choice, eg XXX_BASE
sel	periphral clock source

Definition at line 503 of file rcc.c.

References ADC1_BASE, CEC_BASE, cm3_assert_not_reached, LPTIM1_BASE, LPTIM2_BASE, RCC_CCIPR, RCC_CCIPR_ADCSEL_MASK, RCC_CCIPR_ADCSEL_SHIFT, RCC_CCIPR_CECSEL_MASK, RCC_CCIPR_CECSEL_SHIFT, RCC_CCIPR_LPTIM1SEL_MASK, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPTIM2SEL_MASK, RCC_CCIPR_LPTIM2SEL_SHIFT, RCC_CCIPR_RNGSEL_MASK, RCC_CCIPR_RNGSEL_SHIFT, RCC_CCIPR_TIM1SEL_MASK, RCC_CCIPR_TIM1SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USARTxSEL_MASK, RNG_BASE, TIM1_BASE, USART1_BASE, and USART2_BASE.

rcc_set_pll_source()

void rcc_set_pll_source

(

uint32_t

pllsrc

)

Configure pll source.

Parameters

[in]

pllsrc

pll clock source PLLSRC

Definition at line 315 of file rcc.c.

References RCC_PLLCFGR, RCC_PLLCFGR_PLLSRC_MASK, and RCC_PLLCFGR_PLLSRC_SHIFT.

rcc_set_ppre()

void rcc_set_ppre

(

uint32_t

ppre

)

Configure APB peripheral clock prescaler.

Parameters

[in]

ppre

APB clock prescaler value PPRE

Definition at line 387 of file rcc.c.

References rcc_clock_scale::ppre, RCC_CFGR, RCC_CFGR_PPRE_MASK, and RCC_CFGR_PPRE_SHIFT.

Referenced by rcc_clock_setup().

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rcc_set_rng_clk_div()

void rcc_set_rng_clk_div

(

uint32_t

rng_div

)

Setup RNG Peripheral Clock Divider.

Parameters

rng_div

clock divider RNGDIV

Definition at line 492 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_RNGDIV_MASK, and RCC_CCIPR_RNGDIV_SHIFT.

rcc_set_sysclk_source()

void rcc_set_sysclk_source

(

enum rcc_osc

osc

)

Set the Source for the System Clock.

Parameters

osc	Oscillator to use.

Definition at line 225 of file rcc.c.

References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSISYS, RCC_CFGR_SW_LSE, RCC_CFGR_SW_LSI, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLLRCLK, RCC_CFGR_SW_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup().

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rcc_system_clock_source()

enum rcc_osc rcc_system_clock_source

(

void

)

Return the clock source which is used as system clock.

Returns

rcc_osc system clock source

Definition at line 260 of file rcc.c.

References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSISYS, RCC_CFGR_SW_LSE, RCC_CFGR_SW_LSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLLRCLK, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready

(

enum rcc_osc

osc

)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Definition at line 196 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup().

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rcc_wait_for_sysclk_status()

void rcc_wait_for_sysclk_status

(

enum rcc_osc

osc

)

Wait until system clock switched to given oscillator.

Parameters

osc	Oscillator.

Definition at line 283 of file rcc.c.

References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSISYS, RCC_CFGR_SWS_LSE, RCC_CFGR_SWS_LSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLLRCLK, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup().

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Variable Documentation

rcc_ahb_frequency

uint32_t rcc_ahb_frequency

extern

Definition at line 42 of file rcc.c.

Referenced by rcc_clock_setup(), and rcc_get_clksel_freq().

rcc_apb1_frequency

uint32_t rcc_apb1_frequency

extern

Definition at line 43 of file rcc.c.

Referenced by rcc_clock_setup(), rcc_get_clksel_freq(), rcc_get_spi_clk_freq(), and rcc_get_timer_clk_freq().

rcc_clock_config

const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END]

extern

Definition at line 45 of file rcc.c.