libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
Macros
Reset and Clock Control Register
STM32G0xx Defines » RCC Defines
Collaboration diagram for Reset and Clock Control Register:

Macros

#define RCC_CR   MMIO32(RCC_BASE + 0x00)
 
#define RCC_ICSCR   MMIO32(RCC_BASE + 0x04)
 
#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)
 
#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x0c)
 
#define RCC_CIER   MMIO32(RCC_BASE + 0x18)
 
#define RCC_CIFR   MMIO32(RCC_BASE + 0x1c)
 
#define RCC_CICR   MMIO32(RCC_BASE + 0x20)
 
#define RCC_IOPRSTR_OFFSET   0x24
 
#define RCC_IOPRSTR   MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)
 
#define RCC_AHBRSTR_OFFSET   0x28
 
#define RCC_AHBRSTR   MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)
 
#define RCC_APBRSTR1_OFFSET   0x2c
 
#define RCC_APBRSTR1   MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)
 
#define RCC_APBRSTR2_OFFSET   0x30
 
#define RCC_APBRSTR2   MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)
 
#define RCC_IOPENR_OFFSET   0x34
 
#define RCC_IOPENR   MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)
 
#define RCC_AHBENR_OFFSET   0x38
 
#define RCC_AHBENR   MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)
 
#define RCC_APBENR1_OFFSET   0x3c
 
#define RCC_APBENR1   MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)
 
#define RCC_APBENR2_OFFSET   0x40
 
#define RCC_APBENR2   MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)
 
#define RCC_IOPSMENR_OFFSET   0x44
 
#define RCC_IOPSMENR   MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)
 
#define RCC_AHBSMENR_OFFSET   0x48
 
#define RCC_AHBSMENR   MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)
 
#define RCC_APBSMENR1_OFFSET   0x4c
 
#define RCC_APBSMENR1   MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)
 
#define RCC_APBSMENR2_OFFSET   0x50
 
#define RCC_APBSMENR2   MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)
 
#define RCC_CCIPR   MMIO32(RCC_BASE + 0x54)
 
#define RCC_BDCR   MMIO32(RCC_BASE + 0x5c)
 
#define RCC_CSR   MMIO32(RCC_BASE + 0x60)
 

Detailed Description

Macro Definition Documentation

◆ RCC_AHBENR

#define RCC_AHBENR   MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)

Definition at line 56 of file g0/rcc.h.

◆ RCC_AHBENR_OFFSET

#define RCC_AHBENR_OFFSET   0x38

Definition at line 55 of file g0/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR   MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)

Definition at line 48 of file g0/rcc.h.

◆ RCC_AHBRSTR_OFFSET

#define RCC_AHBRSTR_OFFSET   0x28

Definition at line 47 of file g0/rcc.h.

◆ RCC_AHBSMENR

#define RCC_AHBSMENR   MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)

Definition at line 64 of file g0/rcc.h.

◆ RCC_AHBSMENR_OFFSET

#define RCC_AHBSMENR_OFFSET   0x48

Definition at line 63 of file g0/rcc.h.

◆ RCC_APBENR1

#define RCC_APBENR1   MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)

Definition at line 58 of file g0/rcc.h.

◆ RCC_APBENR1_OFFSET

#define RCC_APBENR1_OFFSET   0x3c

Definition at line 57 of file g0/rcc.h.

◆ RCC_APBENR2

#define RCC_APBENR2   MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)

Definition at line 60 of file g0/rcc.h.

◆ RCC_APBENR2_OFFSET

#define RCC_APBENR2_OFFSET   0x40

Definition at line 59 of file g0/rcc.h.

◆ RCC_APBRSTR1

#define RCC_APBRSTR1   MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)

Definition at line 50 of file g0/rcc.h.

◆ RCC_APBRSTR1_OFFSET

#define RCC_APBRSTR1_OFFSET   0x2c

Definition at line 49 of file g0/rcc.h.

◆ RCC_APBRSTR2

#define RCC_APBRSTR2   MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)

Definition at line 52 of file g0/rcc.h.

◆ RCC_APBRSTR2_OFFSET

#define RCC_APBRSTR2_OFFSET   0x30

Definition at line 51 of file g0/rcc.h.

◆ RCC_APBSMENR1

#define RCC_APBSMENR1   MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)

Definition at line 66 of file g0/rcc.h.

◆ RCC_APBSMENR1_OFFSET

#define RCC_APBSMENR1_OFFSET   0x4c

Definition at line 65 of file g0/rcc.h.

◆ RCC_APBSMENR2

#define RCC_APBSMENR2   MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)

Definition at line 68 of file g0/rcc.h.

◆ RCC_APBSMENR2_OFFSET

#define RCC_APBSMENR2_OFFSET   0x50

Definition at line 67 of file g0/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR   MMIO32(RCC_BASE + 0x5c)

Definition at line 70 of file g0/rcc.h.

◆ RCC_CCIPR

#define RCC_CCIPR   MMIO32(RCC_BASE + 0x54)

Definition at line 69 of file g0/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)

Definition at line 40 of file g0/rcc.h.

◆ RCC_CICR

#define RCC_CICR   MMIO32(RCC_BASE + 0x20)

Definition at line 44 of file g0/rcc.h.

◆ RCC_CIER

#define RCC_CIER   MMIO32(RCC_BASE + 0x18)

Definition at line 42 of file g0/rcc.h.

◆ RCC_CIFR

#define RCC_CIFR   MMIO32(RCC_BASE + 0x1c)

Definition at line 43 of file g0/rcc.h.

◆ RCC_CR

#define RCC_CR   MMIO32(RCC_BASE + 0x00)

Definition at line 38 of file g0/rcc.h.

◆ RCC_CSR

#define RCC_CSR   MMIO32(RCC_BASE + 0x60)

Definition at line 71 of file g0/rcc.h.

◆ RCC_ICSCR

#define RCC_ICSCR   MMIO32(RCC_BASE + 0x04)

Definition at line 39 of file g0/rcc.h.

◆ RCC_IOPENR

#define RCC_IOPENR   MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)

Definition at line 54 of file g0/rcc.h.

◆ RCC_IOPENR_OFFSET

#define RCC_IOPENR_OFFSET   0x34

Definition at line 53 of file g0/rcc.h.

◆ RCC_IOPRSTR

#define RCC_IOPRSTR   MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)

Definition at line 46 of file g0/rcc.h.

◆ RCC_IOPRSTR_OFFSET

#define RCC_IOPRSTR_OFFSET   0x24

Definition at line 45 of file g0/rcc.h.

◆ RCC_IOPSMENR

#define RCC_IOPSMENR   MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)

Definition at line 62 of file g0/rcc.h.

◆ RCC_IOPSMENR_OFFSET

#define RCC_IOPSMENR_OFFSET   0x44

Definition at line 61 of file g0/rcc.h.

◆ RCC_PLLCFGR

#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x0c)

Definition at line 41 of file g0/rcc.h.