libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
pwr.c
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1/** @defgroup pwr_file PWR peripheral API
2 * @ingroup peripheral_apis
3 *
4 * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
5 *
6 * @brief <b>libopencm3 STM32G0xx Power Control</b>
7 *
8 * @version 1.0.0
9 *
10 * This library supports the power control system for the
11 * STM32G0 series of ARM Cortex Microcontrollers by ST Microelectronics.
12 *
13 * LGPL License Terms @ref lgpl_license
14 */
15/*
16 * This file is part of the libopencm3 project.
17 *
18 * This library is free software: you can redistribute it and/or modify
19 * it under the terms of the GNU Lesser General Public License as published by
20 * the Free Software Foundation, either version 3 of the License, or
21 * (at your option) any later version.
22 *
23 * This library is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU Lesser General Public License for more details.
27 *
28 * You should have received a copy of the GNU Lesser General Public License
29 * along with this library. If not, see <http://www.gnu.org/licenses/>.
30 */
31/**@{*/
33
34/*---------------------------------------------------------------------------*/
35/** @brief Setup voltage scaling range.
36 */
38{
39 uint32_t reg32;
40
42 reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT;
43 PWR_CR1 = reg32;
44}
45
46/*---------------------------------------------------------------------------*/
47/** @brief Disable RTC domain write protect.
48 */
50{
52}
53
54/*---------------------------------------------------------------------------*/
55/** @brief Enable RTC domain write protect.
56 */
58{
59 PWR_CR1 &= ~PWR_CR1_DBP;
60}
61
62/*---------------------------------------------------------------------------*/
63/** @brief Select the low power mode used in deep sleep.
64 * @param lpms low power mode @ref pwr_cr1_lpms
65 */
67{
68 uint32_t reg32;
69
70 reg32 = PWR_CR1;
72 PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
73}
74
75/*---------------------------------------------------------------------------*/
76/** @brief Enable Power Voltage Detector.
77 * @param[in] pvdr_level Power Voltage Detector Rising Threshold voltage @ref pwr_cr2_pvdrt.
78 * @param[in] pvdf_level Power Voltage Detector Falling Threshold voltage @ref pwr_cr2_pvdft.
79*/
80void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level)
81{
82 uint32_t reg32;
83
84 reg32 = PWR_CR2;
87 PWR_CR2 = (reg32 | (pvdf_level << PWR_CR2_PVDFT_SHIFT) | (pvdr_level << PWR_CR2_PVDRT_SHIFT) | PWR_CR2_PVDE);
88}
89
90/*---------------------------------------------------------------------------*/
91/** @brief Disable Power Voltage Detector.
92*/
94{
95 PWR_CR2 &= ~PWR_CR2_PVDE;
96}
97
98/**@}*/
#define PWR_CR1_DBP
Definition: g0/pwr.h:79
#define PWR_CR2_PVDFT_MASK
Definition: g0/pwr.h:115
#define PWR_CR1_VOS_MASK
Definition: g0/pwr.h:71
#define PWR_CR2_PVDFT_SHIFT
Definition: g0/pwr.h:114
#define PWR_CR1_LPMS_SHIFT
Definition: g0/pwr.h:85
#define PWR_CR1_VOS_SHIFT
Definition: g0/pwr.h:70
pwr_vos_scale
Definition: g0/pwr.h:181
#define PWR_CR2_PVDRT_SHIFT
Definition: g0/pwr.h:99
#define PWR_CR2_PVDE
Definition: g0/pwr.h:128
#define PWR_CR1_LPMS_MASK
Definition: g0/pwr.h:86
#define PWR_CR2_PVDRT_MASK
Definition: g0/pwr.h:100
void pwr_set_low_power_mode_selection(uint32_t lpms)
Select the low power mode used in deep sleep.
Definition: pwr.c:66
void pwr_enable_backup_domain_write_protect(void)
Enable RTC domain write protect.
Definition: pwr.c:57
void pwr_disable_power_voltage_detect(void)
Disable Power Voltage Detector.
Definition: pwr.c:93
void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level)
Enable Power Voltage Detector.
Definition: pwr.c:80
void pwr_disable_backup_domain_write_protect(void)
Disable RTC domain write protect.
Definition: pwr.c:49
void pwr_set_vos_scale(enum pwr_vos_scale scale)
Setup voltage scaling range.
Definition: pwr.c:37
#define PWR_CR1
Power control register 1 (PWR_CR1)
Definition: g0/pwr.h:35
#define PWR_CR2
Power control register 2 (PWR_CR2)
Definition: g0/pwr.h:38