VCO Division factor R for PLLRCLK clock output [2..8]. More...
Collaboration diagram for PLLR:
Macros | |
| #define | RCC_PLLCFGR_PLLR_DIV(x) ((x)-1) |
Detailed Description
VCO Division factor R for PLLRCLK clock output [2..8].
Frequency must not exceed 64mhz in voltage range 1, or 16mhz in voltage range 2.
- See also
- PLLR
