Division factor M [1..8] for PLL input clock. More...
Collaboration diagram for PLLM:
Macros | |
| #define | RCC_PLLCFGR_PLLM_DIV(x) ((x)-1) |
Detailed Description
Division factor M [1..8] for PLL input clock.
Input frequency must be between 4mhz and 16mhz.
