libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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libopencm3 STM32G0xx Reset and Clock Control More...
Macros | |
#define | _RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5)) |
#define | _RCC_BIT(i) (1 << ((i) & 0x1f)) |
Functions | |
void | rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en) |
RCC Enable Peripheral Clocks. More... | |
void | rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en) |
RCC Disable Peripheral Clocks. More... | |
void | rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset) |
RCC Reset Peripherals. More... | |
void | rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset) |
RCC Remove Reset on Peripherals. More... | |
void | rcc_periph_clock_enable (enum rcc_periph_clken clken) |
Enable Peripheral Clock in running mode. More... | |
void | rcc_periph_clock_disable (enum rcc_periph_clken clken) |
Disable Peripheral Clock in running mode. More... | |
void | rcc_periph_reset_pulse (enum rcc_periph_rst rst) |
Reset Peripheral, pulsed. More... | |
void | rcc_periph_reset_hold (enum rcc_periph_rst rst) |
Reset Peripheral, hold. More... | |
void | rcc_periph_reset_release (enum rcc_periph_rst rst) |
Reset Peripheral, release. More... | |
void | rcc_set_mco (uint32_t mcosrc) |
Select the source of Microcontroller Clock Output. More... | |
void | rcc_osc_bypass_enable (enum rcc_osc osc) |
RCC Enable Bypass. More... | |
void | rcc_osc_bypass_disable (enum rcc_osc osc) |
RCC Disable Bypass. More... | |
uint16_t | rcc_get_div_from_hpre (uint8_t div_val) |
This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More... | |
void | rcc_osc_on (enum rcc_osc osc) |
void | rcc_osc_off (enum rcc_osc osc) |
bool | rcc_is_osc_ready (enum rcc_osc osc) |
Is the given oscillator ready? More... | |
void | rcc_wait_for_osc_ready (enum rcc_osc osc) |
Wait for Oscillator Ready. More... | |
void | rcc_css_enable (void) |
void | rcc_css_disable (void) |
void | rcc_css_int_clear (void) |
int | rcc_css_int_flag (void) |
void | rcc_set_sysclk_source (enum rcc_osc osc) |
Set the Source for the System Clock. More... | |
enum rcc_osc | rcc_system_clock_source (void) |
Return the clock source which is used as system clock. More... | |
void | rcc_wait_for_sysclk_status (enum rcc_osc osc) |
Wait until system clock switched to given oscillator. More... | |
void | rcc_set_pll_source (uint32_t pllsrc) |
Configure pll source. More... | |
void | rcc_set_main_pll (uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr) |
Configure pll source and output frequencies. More... | |
void | rcc_enable_pllp (bool enable) |
Enable PLL P clock output. More... | |
void | rcc_enable_pllq (bool enable) |
Enable PLL Q clock output. More... | |
void | rcc_enable_pllr (bool enable) |
Enable PLL R clock output. More... | |
void | rcc_set_ppre (uint32_t ppre) |
Configure APB peripheral clock prescaler. More... | |
void | rcc_set_hpre (uint32_t hpre) |
Configure AHB peripheral clock prescaler. More... | |
void | rcc_set_hsisys_div (uint32_t hsidiv) |
Configure HSI16 clock division factor to feed SYSCLK. More... | |
void | rcc_set_mcopre (uint32_t mcopre) |
Configure mco prescaler. More... | |
void | rcc_clock_setup (const struct rcc_clock_scale *clock) |
Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). More... | |
void | rcc_set_rng_clk_div (uint32_t rng_div) |
Setup RNG Peripheral Clock Divider. More... | |
void | rcc_set_peripheral_clk_sel (uint32_t periph, uint32_t sel) |
Set the peripheral clock source. More... | |
static uint32_t | rcc_get_clksel_freq (uint8_t shift) |
uint32_t | rcc_get_usart_clk_freq (uint32_t usart) |
Get the peripheral clock speed for the USART at base specified. More... | |
uint32_t | rcc_get_timer_clk_freq (uint32_t timer) |
Get the peripheral clock speed for the Timer at base specified. More... | |
uint32_t | rcc_get_i2c_clk_freq (uint32_t i2c) |
Get the peripheral clock speed for the I2C device at base specified. More... | |
uint32_t | rcc_get_spi_clk_freq (uint32_t spi) |
Get the peripheral clock speed for the SPI device at base specified. More... | |
Variables | |
uint32_t | rcc_ahb_frequency = 16000000 |
uint32_t | rcc_apb1_frequency = 16000000 |
const struct rcc_clock_scale | rcc_clock_config [RCC_CLOCK_CONFIG_END] |
libopencm3 STM32G0xx Reset and Clock Control
This library supports the Reset and Clock Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
LGPL License Terms libopencm3 License
#define _RCC_BIT | ( | i | ) | (1 << ((i) & 0x1f)) |
Definition at line 117 of file rcc_common_all.c.
Definition at line 116 of file rcc_common_all.c.
void rcc_clock_setup | ( | const struct rcc_clock_scale * | clock | ) |
Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI).
taking care of flash/pwr and src configuration
clock | rcc_clock_scale with desired parameters |
Definition at line 439 of file rcc.c.
References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb_frequency, FLASH_ACR_LATENCY_0WS, flash_prefetch_disable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::hsisys_div, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::pllp_div, rcc_clock_scale::pllq_div, rcc_clock_scale::pllr_div, rcc_clock_scale::ppre, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_enable_pllr(), RCC_HSE, RCC_HSI, rcc_is_osc_ready(), rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PLLCFGR_PLLSRC_HSE, RCC_PWR, rcc_set_hpre(), rcc_set_hsisys_div(), rcc_set_main_pll(), rcc_set_ppre(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), rcc_wait_for_sysclk_status(), rcc_clock_scale::sysclock_source, and rcc_clock_scale::voltage_scale.
void rcc_css_enable | ( | void | ) |
Definition at line 201 of file rcc.c.
References RCC_CR, and RCC_CR_CSSON.
void rcc_css_int_clear | ( | void | ) |
Definition at line 211 of file rcc.c.
References RCC_CICR, and RCC_CICR_CSSC.
int rcc_css_int_flag | ( | void | ) |
Definition at line 216 of file rcc.c.
References RCC_CIFR, and RCC_CIFR_CSSF.
void rcc_enable_pllp | ( | bool | enable | ) |
Enable PLL P clock output.
[in] | enable | or disable P clock output |
Definition at line 348 of file rcc.c.
References RCC_PLLCFGR, and RCC_PLLCFGR_PLLPEN.
void rcc_enable_pllq | ( | bool | enable | ) |
Enable PLL Q clock output.
[in] | enable | or disable Q clock output |
Definition at line 361 of file rcc.c.
References RCC_PLLCFGR, and RCC_PLLCFGR_PLLQEN.
void rcc_enable_pllr | ( | bool | enable | ) |
Enable PLL R clock output.
[in] | enable | or disable R clock output |
Definition at line 374 of file rcc.c.
References RCC_PLLCFGR, and RCC_PLLCFGR_PLLREN.
Referenced by rcc_clock_setup().
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static |
Definition at line 550 of file rcc.c.
References cm3_assert_not_reached, rcc_clock_scale::hpre, rcc_ahb_frequency, rcc_apb1_frequency, RCC_CCIPR, RCC_CCIPR_USARTxSEL_HSI16, RCC_CCIPR_USARTxSEL_LSE, RCC_CCIPR_USARTxSEL_MASK, RCC_CCIPR_USARTxSEL_PCLK, RCC_CCIPR_USARTxSEL_SYSCLK, RCC_CFGR, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().
Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clk_freq().
uint16_t rcc_get_div_from_hpre | ( | uint8_t | div_val | ) |
This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.
div_val | Masked and shifted divider value from register (e.g. RCC_CFGR) |
Definition at line 260 of file rcc_common_all.c.
Referenced by rcc_get_clksel_freq().
uint32_t rcc_get_i2c_clk_freq | ( | uint32_t | i2c | ) |
Get the peripheral clock speed for the I2C device at base specified.
i2c | Base address of I2C to get clock frequency for. |
Definition at line 601 of file rcc.c.
References cm3_assert_not_reached, I2C1_BASE, I2C2_BASE, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C2SEL_SHIFT, and rcc_get_clksel_freq().
uint32_t rcc_get_spi_clk_freq | ( | uint32_t | spi | ) |
Get the peripheral clock speed for the SPI device at base specified.
spi | Base address of SPI device to get clock frequency for (e.g. SPI1_BASE). |
Definition at line 615 of file rcc.c.
References rcc_apb1_frequency.
uint32_t rcc_get_timer_clk_freq | ( | uint32_t | timer | ) |
Get the peripheral clock speed for the Timer at base specified.
timer | Base address of TIM to get clock frequency for. |
Definition at line 590 of file rcc.c.
References rcc_clock_scale::ppre, rcc_apb1_frequency, RCC_CFGR, RCC_CFGR_PPRE_MASK, RCC_CFGR_PPRE_NODIV, and RCC_CFGR_PPRE_SHIFT.
uint32_t rcc_get_usart_clk_freq | ( | uint32_t | usart | ) |
Get the peripheral clock speed for the USART at base specified.
usart | Base address of USART to get clock frequency for. |
Definition at line 570 of file rcc.c.
References cm3_assert_not_reached, LPUART1_BASE, LPUART2_BASE, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_LPUART2SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_get_clksel_freq(), USART1_BASE, USART2_BASE, and USART3_BASE.
Referenced by usart_set_baudrate().
bool rcc_is_osc_ready | ( | enum rcc_osc | osc | ) |
Is the given oscillator ready?
osc | Oscillator ID |
Definition at line 176 of file rcc.c.
References cm3_assert_not_reached, RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup(), and rcc_wait_for_osc_ready().
void rcc_osc_bypass_disable | ( | enum rcc_osc | osc | ) |
RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.
[in] | osc | Oscillator ID. Only HSE and LSE have effect. |
Definition at line 238 of file rcc_common_all.c.
void rcc_osc_bypass_enable | ( | enum rcc_osc | osc | ) |
RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.
[in] | osc | Oscillator ID. Only HSE and LSE have effect. |
Definition at line 208 of file rcc_common_all.c.
References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.
void rcc_osc_off | ( | enum rcc_osc | osc | ) |
void rcc_osc_on | ( | enum rcc_osc | osc | ) |
Definition at line 128 of file rcc.c.
References cm3_assert_not_reached, RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup().
void rcc_periph_clock_disable | ( | enum rcc_periph_clken | clken | ) |
Disable Peripheral Clock in running mode.
Disable the clock on particular peripheral.
[in] | clken | rcc_periph_clken Peripheral RCC |
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 139 of file rcc_common_all.c.
References _RCC_REG.
void rcc_periph_clock_enable | ( | enum rcc_periph_clken | clken | ) |
Enable Peripheral Clock in running mode.
Enable the clock on particular peripheral.
[in] | clken | rcc_periph_clken Peripheral RCC |
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 127 of file rcc_common_all.c.
References _RCC_BIT, and _RCC_REG.
Referenced by rcc_clock_setup().
void rcc_periph_reset_hold | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, hold.
Reset particular peripheral, and hold in reset state.
[in] | rst | rcc_periph_rst Peripheral reset |
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 166 of file rcc_common_all.c.
void rcc_periph_reset_pulse | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, pulsed.
Reset particular peripheral, and restore to working state.
[in] | rst | rcc_periph_rst Peripheral reset |
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 152 of file rcc_common_all.c.
void rcc_periph_reset_release | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, release.
Restore peripheral from reset state to working state.
[in] | rst | rcc_periph_rst Peripheral reset |
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 179 of file rcc_common_all.c.
References _RCC_REG.
void rcc_peripheral_clear_reset | ( | volatile uint32_t * | reg, |
uint32_t | clear_reset | ||
) |
RCC Remove Reset on Peripherals.
Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.
[in] | *reg | Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) |
[in] | clear_reset | Unsigned int32. Logical OR of all resets to be removed:
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Definition at line 111 of file rcc_common_all.c.
void rcc_peripheral_disable_clock | ( | volatile uint32_t * | reg, |
uint32_t | en | ||
) |
RCC Disable Peripheral Clocks.
Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.
[in] | *reg | Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) |
[in] | en | Unsigned int32. Logical OR of all enables to be used for disabling.
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Definition at line 66 of file rcc_common_all.c.
void rcc_peripheral_enable_clock | ( | volatile uint32_t * | reg, |
uint32_t | en | ||
) |
RCC Enable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.
[in] | *reg | Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) |
[in] | en | Unsigned int32. Logical OR of all enables to be set
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Definition at line 44 of file rcc_common_all.c.
void rcc_peripheral_reset | ( | volatile uint32_t * | reg, |
uint32_t | reset | ||
) |
RCC Reset Peripherals.
Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.
[in] | *reg | Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) |
[in] | reset | Unsigned int32. Logical OR of all resets.
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Definition at line 88 of file rcc_common_all.c.
void rcc_set_hpre | ( | uint32_t | hpre | ) |
Configure AHB peripheral clock prescaler.
[in] | hpre | AHB clock prescaler value HPRE |
Definition at line 400 of file rcc.c.
References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.
Referenced by rcc_clock_setup().
void rcc_set_hsisys_div | ( | uint32_t | hsidiv | ) |
Configure HSI16 clock division factor to feed SYSCLK.
[in] | hsidiv | HSYSSIS clock division factor HSI Div |
Definition at line 413 of file rcc.c.
References RCC_CR, RCC_CR_HSIDIV_MASK, and RCC_CR_HSIDIV_SHIFT.
Referenced by rcc_clock_setup().
void rcc_set_main_pll | ( | uint32_t | source, |
uint32_t | pllm, | ||
uint32_t | plln, | ||
uint32_t | pllp, | ||
uint32_t | pllq, | ||
uint32_t | pllr | ||
) |
Configure pll source and output frequencies.
[in] | source | pll clock source PLLSRC |
[in] | pllm | pll vco division factor PLLM |
[in] | plln | pll vco multiplation factor PLLN |
[in] | pllp | pll P clock output division factor PLLP |
[in] | pllq | pll Q clock output division factor PLLQ |
[in] | pllr | pll R clock output (sysclock pll) division factor PLLR |
Definition at line 333 of file rcc.c.
References RCC_PLLCFGR, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLP_SHIFT, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_SHIFT, and RCC_PLLCFGR_PLLSRC_SHIFT.
Referenced by rcc_clock_setup().
void rcc_set_mco | ( | uint32_t | mcosrc | ) |
Select the source of Microcontroller Clock Output.
Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1
[in] | mcosrc | the unshifted source bits |
Definition at line 191 of file rcc_common_all.c.
References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.
void rcc_set_mcopre | ( | uint32_t | mcopre | ) |
Configure mco prescaler.
[in] | mcopre | prescaler value MCO Pre |
Definition at line 426 of file rcc.c.
References RCC_CFGR, RCC_CFGR_MCOPRE_MASK, and RCC_CFGR_MCOPRE_SHIFT.
void rcc_set_peripheral_clk_sel | ( | uint32_t | periph, |
uint32_t | sel | ||
) |
Set the peripheral clock source.
periph | peripheral of choice, eg XXX_BASE |
sel | periphral clock source |
Definition at line 503 of file rcc.c.
References ADC1_BASE, CEC_BASE, cm3_assert_not_reached, LPTIM1_BASE, LPTIM2_BASE, RCC_CCIPR, RCC_CCIPR_ADCSEL_MASK, RCC_CCIPR_ADCSEL_SHIFT, RCC_CCIPR_CECSEL_MASK, RCC_CCIPR_CECSEL_SHIFT, RCC_CCIPR_LPTIM1SEL_MASK, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPTIM2SEL_MASK, RCC_CCIPR_LPTIM2SEL_SHIFT, RCC_CCIPR_RNGSEL_MASK, RCC_CCIPR_RNGSEL_SHIFT, RCC_CCIPR_TIM1SEL_MASK, RCC_CCIPR_TIM1SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USARTxSEL_MASK, RNG_BASE, TIM1_BASE, USART1_BASE, and USART2_BASE.
void rcc_set_pll_source | ( | uint32_t | pllsrc | ) |
Configure pll source.
[in] | pllsrc | pll clock source PLLSRC |
Definition at line 315 of file rcc.c.
References RCC_PLLCFGR, RCC_PLLCFGR_PLLSRC_MASK, and RCC_PLLCFGR_PLLSRC_SHIFT.
void rcc_set_ppre | ( | uint32_t | ppre | ) |
Configure APB peripheral clock prescaler.
[in] | ppre | APB clock prescaler value PPRE |
Definition at line 387 of file rcc.c.
References rcc_clock_scale::ppre, RCC_CFGR, RCC_CFGR_PPRE_MASK, and RCC_CFGR_PPRE_SHIFT.
Referenced by rcc_clock_setup().
void rcc_set_rng_clk_div | ( | uint32_t | rng_div | ) |
Setup RNG Peripheral Clock Divider.
rng_div | clock divider RNGDIV |
Definition at line 492 of file rcc.c.
References RCC_CCIPR, RCC_CCIPR_RNGDIV_MASK, and RCC_CCIPR_RNGDIV_SHIFT.
void rcc_set_sysclk_source | ( | enum rcc_osc | osc | ) |
Set the Source for the System Clock.
osc | Oscillator to use. |
Definition at line 225 of file rcc.c.
References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSISYS, RCC_CFGR_SW_LSE, RCC_CFGR_SW_LSI, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLLRCLK, RCC_CFGR_SW_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup().
enum rcc_osc rcc_system_clock_source | ( | void | ) |
Return the clock source which is used as system clock.
Definition at line 260 of file rcc.c.
References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSISYS, RCC_CFGR_SW_LSE, RCC_CFGR_SW_LSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLLRCLK, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.
void rcc_wait_for_osc_ready | ( | enum rcc_osc | osc | ) |
Wait for Oscillator Ready.
Block until the hardware indicates that the Oscillator is ready.
osc | Oscillator ID |
Definition at line 196 of file rcc.c.
References rcc_is_osc_ready().
Referenced by rcc_clock_setup().
void rcc_wait_for_sysclk_status | ( | enum rcc_osc | osc | ) |
Wait until system clock switched to given oscillator.
osc | Oscillator. |
Definition at line 283 of file rcc.c.
References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSISYS, RCC_CFGR_SWS_LSE, RCC_CFGR_SWS_LSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLLRCLK, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup().
uint32_t rcc_ahb_frequency = 16000000 |
Definition at line 42 of file rcc.c.
Referenced by rcc_clock_setup(), and rcc_get_clksel_freq().
uint32_t rcc_apb1_frequency = 16000000 |
Definition at line 43 of file rcc.c.
Referenced by rcc_clock_setup(), rcc_get_clksel_freq(), rcc_get_spi_clk_freq(), and rcc_get_timer_clk_freq().
const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] |