VCO Division factor Q for PLLQCLK clock output [2..8]. More...
Collaboration diagram for PLLQ:
Macros | |
| #define | RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1) |
Detailed Description
VCO Division factor Q for PLLQCLK clock output [2..8].
Frequency must not exceed 128mhz in voltage range 1, or 32mhz in range 2
- See also
- PLLQ
