CR Clock control Register
Collaboration diagram for CR Clock control Register:
Modules | |
| HSI Div | |
| Division factor of the HSI16 oscillator to produce HSISYS clock. | |
Macros | |
| #define | RCC_CR_PLLRDY (1 << 25) |
| #define | RCC_CR_PLLON (1 << 24) |
| #define | RCC_CR_CSSON (1 << 19) |
| #define | RCC_CR_HSEBYP (1 << 18) |
| #define | RCC_CR_HSERDY (1 << 17) |
| #define | RCC_CR_HSEON (1 << 16) |
| #define | RCC_CR_HSIDIV_SHIFT 11 |
| #define | RCC_CR_HSIDIV_MASK 0x7 |
| #define | RCC_CR_HSIRDY (1 << 10) |
| #define | RCC_CR_HSIKERON (1 << 9) |
| #define | RCC_CR_HSION (1 << 8) |
