59 NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
72 NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
86 return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
100 NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
114 NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
128 return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
131#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
159#if defined(__ARM_ARCH_6M__)
161 irqn = (irqn & 0xF) - 4;
162 uint8_t shift = (irqn & 0x3) << 3;
163 uint8_t reg = irqn >> 2;
165 ((uint32_t) priority) << shift);
167 SCB_SHPR((irqn & 0xF) - 4) = priority;
171#if defined(__ARM_ARCH_6M__)
173 uint8_t shift = (irqn & 0x3) << 3;
174 uint8_t reg = irqn >> 2;
176 ((uint32_t) priority) << shift);
178 NVIC_IPR(irqn) = priority;
184#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
194uint8_t nvic_get_active_irq(uint8_t irqn)
196 return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
209void nvic_generate_software_interrupt(uint16_t irqn)
uint8_t nvic_get_pending_irq(uint8_t irqn)
NVIC Return Pending Interrupt.
void nvic_set_pending_irq(uint8_t irqn)
NVIC Set Pending Interrupt.
void nvic_set_priority(uint8_t irqn, uint8_t priority)
NVIC Set Interrupt Priority.
void nvic_clear_pending_irq(uint8_t irqn)
NVIC Clear Pending Interrupt.
uint8_t nvic_get_irq_enabled(uint8_t irqn)
NVIC Return Enabled Interrupt.
void nvic_enable_irq(uint8_t irqn)
NVIC Enable Interrupt.
void nvic_disable_irq(uint8_t irqn)
NVIC Disable Interrupt.
#define SCB_SHPR32(ipr_id)
System Handler Priority 8 bits Registers, SHPR1/2/3.
#define NVIC_ICER(icer_id)
ICER: Interrupt Clear Enable Registers.
#define NVIC_ISER(iser_id)
ISER: Interrupt Set Enable Registers.
#define NVIC_ISPR(ispr_id)
ISPR: Interrupt Set Pending Registers.
#define NVIC_IPR32(ipr_id)
IPR: Interrupt Priority Registers.
#define NVIC_ICPR(icpr_id)
ICPR: Interrupt Clear Pending Registers.