libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
syscfg.h
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1/** @defgroup syscfg_defines SYSCFG Defines
2 *
3 * @ingroup STM32G0xx_defines
4 *
5 * @brief <b>Defined Constants and Types for the STM32G0xx System Configuration controller </b>
6 *
7 * @version 1.0.0
8 *
9 * @author @htmlonly &copy; @endhtmlonly 2019
10 * Guillaume Revaillot <g.revaillot@gmail.com>
11 *
12 * LGPL License Terms @ref lgpl_license
13 */
14/*
15 * This file is part of the libopencm3 project.
16 *
17 * This library is free software: you can redistribute it and/or modify
18 * it under the terms of the GNU Lesser General Public License as published by
19 * the Free Software Foundation, either version 3 of the License, or
20 * (at your option) any later version.
21 *
22 * This library is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU Lesser General Public License for more details.
26 *
27 * You should have received a copy of the GNU Lesser General Public License
28 * along with this library. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#ifndef LIBOPENCM3_SYSCFG_H
32#define LIBOPENCM3_SYSCFG_H
33
34/**@{*/
35
36/**@defgroup syscfg_registers SYSCFG Registers
37 @{*/
38#define SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x00)
39#define SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x18)
40
41#define SYSCFG_ITLINE(line) MMIO32(SYSCFG_BASE + 0x80 + (line)*4)
42/**@}*/
43
44/** @defgroup syscfg_cfgr1 CFGR1 SYSCFG configuration register 1
45@{*/
46
47
48/** SYSCFG_CFGR1_I2C_PA10_FMP FM+ enable for PA10 */
49#define SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23)
50
51/** SYSCFG_CFGR1_I2C_PA9_FMP FM+ enable for PA9 */
52#define SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22)
53
54/** SYSCFG_CFGR1_I2C2_FMP FM+ driving capability activation for I2C2 */
55#define SYSCFG_CFGR1_I2C2_FMP (1 << 21)
56
57/** SYSCFG_CFGR1_I2C1_FMP FM+ driving capability activation for I2C1 */
58#define SYSCFG_CFGR1_I2C1_FMP (1 << 20)
59
60/** SYSCFG_CFGR1_I2C_PB9_FMP FM+ enable for PB9 */
61#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19)
62
63/** SYSCFG_CFGR1_I2C_PB8_FMP FM+ enable for PB8 */
64#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18)
65
66/** SYSCFG_CFGR1_I2C_PB7_FMP FM+ enable for PB7 */
67#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17)
68
69/** SYSCFG_CFGR1_I2C_PB6_FMP FM+ enable for PB6 */
70#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16)
71
72/** SYSCFG_CFGR1_UCPD2_STROBE Strobe signal bit for UCPD2 */
73#define SYSCFG_CFGR1_UCPD2_STROBE (1 << 10)
74
75/** SYSCFG_CFGR1_UCPD1_STROBE Strobe signal bit for UCPD1 */
76#define SYSCFG_CFGR1_UCPD1_STROBE (1 << 9)
77
78/** SYSCFG_CFGR1_BOOSTEN I/O analog switch voltage booster enable */
79#define SYSCFG_CFGR1_BOOSTEN (1 << 8)
80
81#define SYSCFG_CFGR1_IR_MOD_SHIFT 6
82#define SYSCFG_CFGR1_IR_MOD_MASK 0x03
83/** @defgroup syscfg_cfgr1_ir_mod IR MOD
84* @brief IR Modulation Envelope signal selection.
85@{*/
86#define SYSCFG_CFGR1_IR_MOD_TIM16 0
87#define SYSCFG_CFGR1_IR_MOD_USART1 1
88#define SYSCFG_CFGR1_IR_MOD_USART4 2
89/**@}*/
90
91/** SYSCFG_CFGR1_IR_POL IR output polarity selection */
92#define SYSCFG_CFGR1_IR_POL (1 << 5)
93
94/** SYSCFG_CFGR1_PA12_RMP PA12 pin remapping */
95#define SYSCFG_CFGR1_PA12_RMP (1 << 4)
96
97/** SYSCFG_CFGR1_PA11_RMP PA11 pin remapping */
98#define SYSCFG_CFGR1_PA11_RMP (1 << 3)
99
100#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0
101#define SYSCFG_CFGR1_MEM_MODE_MASK 0x03
102/** @defgroup syscfg_cfgr1_mem_mode MEM MODE
103* @brief Memory mapping selection bits
104@{*/
105#define SYSCFG_CFGR1_MEM_MODE_FLASH 0
106#define SYSCFG_CFGR1_MEM_MODE_SYSTEM 1
107#define SYSCFG_CFGR1_MEM_MODE_SRAM 3
108/**@}*/
109
110/**@}*/
111
112
113/** @defgroup syscfg_cfgr2 CFGR2 SYSCFG configuration register 2
114@{*/
115
116/** SYSCFG_CFGR2_PB2_CDEN PB2 clamping diode enable */
117#define SYSCFG_CFGR2_PB2_CDEN (1 << 23)
118
119/** SYSCFG_CFGR2_PB1_CDEN PB1 clamping diode enable */
120#define SYSCFG_CFGR2_PB1_CDEN (1 << 22)
121
122/** SYSCFG_CFGR2_PB0_CDEN PB0 clamping diode enable */
123#define SYSCFG_CFGR2_PB0_CDEN (1 << 21)
124
125/** SYSCFG_CFGR2_PA13_CDEN PA13 clamping diode enable */
126#define SYSCFG_CFGR2_PA13_CDEN (1 << 20)
127
128/** SYSCFG_CFGR2_PA6_CDEN PA6 clamping diode enable */
129#define SYSCFG_CFGR2_PA6_CDEN (1 << 19)
130
131/** SYSCFG_CFGR2_PA5_CDEN PA5 clamping diode enable */
132#define SYSCFG_CFGR2_PA5_CDEN (1 << 18)
133
134/** SYSCFG_CFGR2_PA3_CDEN PA3 clamping diode enable */
135#define SYSCFG_CFGR2_PA3_CDEN (1 << 17)
136
137/** SYSCFG_CFGR2_PA1_CDEN PA1 clamping diode enable */
138#define SYSCFG_CFGR2_PA1_CDEN (1 << 16)
139
140/** SYSCFG_CFGR2_SRAM_PEF SRAM parity error flag */
141#define SYSCFG_CFGR2_SRAM_PEF (1 << 8)
142
143/** SYSCFG_CFGR2_ECC_LOCK ECC error lock bit */
144#define SYSCFG_CFGR2_ECC_LOCK (1 << 3)
145
146/** SYSCFG_CFGR2_PVD_LOCK PVD lock enable bit */
147#define SYSCFG_CFGR2_PVD_LOCK (1 << 2)
148
149/** SYSCFG_CFGR2_SRAM_PARITY_LOCK SRAM parity lock bit */
150#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1)
151
152/** SYSCFG_CFGR2_LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit */
153#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0)
154
155/**@}*/
156
157/** @defgroup syscfg_itline0 ITLINE0 interrupt line 0 status register
158@{*/
159#define SYSCFG_ITLINE0_WWDG (1 << 0)
160/**@}*/
161
162/** @defgroup syscfg_itline1 ITLINE1 interrupt line 1 status register
163@{*/
164#define SYSCFG_ITLINE1_PVDOUT (1 << 0)
165/**@}*/
166
167/** @defgroup syscfg_itline2 ITLINE2 interrupt line 2 status register
168@{*/
169#define SYSCFG_ITLINE2_RTC (1 << 1)
170#define SYSCFG_ITLINE2_TAMP (1 << 0)
171/**@}*/
172
173/** @defgroup syscfg_itline3 ITLINE3 interrupt line 3 status register
174@{*/
175#define SYSCFG_ITLINE3_FLASH_ECC (1 << 1)
176#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0)
177/**@}*/
178
179/** @defgroup syscfg_itline4 ITLINE4 interrupt line 4 status register
180@{*/
181#define SYSCFG_ITLINE4_RCC (1 << 0)
182/**@}*/
183
184/** @defgroup syscfg_itline5 ITLINE5 interrupt line 5 status register
185@{*/
186#define SYSCFG_ITLINE5_EXTI1 (1 << 1)
187#define SYSCFG_ITLINE5_EXTI0 (1 << 0)
188/**@}*/
189
190/** @defgroup syscfg_itline6 ITLINE6 interrupt line 6 status register
191@{*/
192#define SYSCFG_ITLINE6_EXTI3 (1 << 1)
193#define SYSCFG_ITLINE6_EXTI2 (1 << 0)
194/**@}*/
195
196/** @defgroup syscfg_itline7 ITLINE7 interrupt line 7 status register
197@{*/
198#define SYSCFG_ITLINE7_EXTI15 (1 << 11)
199#define SYSCFG_ITLINE7_EXTI14 (1 << 10)
200#define SYSCFG_ITLINE7_EXTI13 (1 << 9)
201#define SYSCFG_ITLINE7_EXTI12 (1 << 8)
202#define SYSCFG_ITLINE7_EXTI11 (1 << 7)
203#define SYSCFG_ITLINE7_EXTI10 (1 << 6)
204#define SYSCFG_ITLINE7_EXTI9 (1 << 5)
205#define SYSCFG_ITLINE7_EXTI8 (1 << 4)
206#define SYSCFG_ITLINE7_EXTI7 (1 << 3)
207#define SYSCFG_ITLINE7_EXTI6 (1 << 2)
208#define SYSCFG_ITLINE7_EXTI5 (1 << 1)
209#define SYSCFG_ITLINE7_EXTI4 (1 << 0)
210/**@}*/
211
212/** @defgroup syscfg_itline8 ITLINE8 interrupt line 8 status register
213@{*/
214#define SYSCFG_ITLINE8_UCPD2 (1 << 1)
215#define SYSCFG_ITLINE8_UCPD1 (1 << 0)
216/**@}*/
217
218/** @defgroup syscfg_itline9 ITLINE9 interrupt line 9 status register
219@{*/
220#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0)
221/**@}*/
222
223/** @defgroup syscfg_itline10 ITLINE10 interrupt line 10 status register
224@{*/
225#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1)
226#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0)
227/**@}*/
228
229/** @defgroup syscfg_itline11 ITLINE11 interrupt line 11 status register
230@{*/
231#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 4)
232#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 3)
233#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 2)
234#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 1)
235#define SYSCFG_ITLINE11_DMAMUX (1 << 0)
236/**@}*/
237
238/** @defgroup syscfg_itline12 ITLINE12 interrupt line 12 status register
239@{*/
240#define SYSCFG_ITLINE12_COMP2 (1 << 2)
241#define SYSCFG_ITLINE12_COMP1 (1 << 1)
242#define SYSCFG_ITLINE12_ADC (1 << 0)
243/**@}*/
244
245/** @defgroup syscfg_itline13 ITLINE13 interrupt line 13 status register
246@{*/
247#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3)
248#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2)
249#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1)
250#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0)
251/**@}*/
252
253/** @defgroup syscfg_itline14 ITLINE14 interrupt line 14 status register
254@{*/
255#define SYSCFG_ITLINE14_TIM1_CC (1 << 0)
256/**@}*/
257
258/** @defgroup syscfg_itline15 ITLINE15 interrupt line 15 status register
259@{*/
260#define SYSCFG_ITLINE15_TIM2 (1 << 0)
261/**@}*/
262
263/** @defgroup syscfg_itline16 ITLINE16 interrupt line 16 status register
264@{*/
265#define SYSCFG_ITLINE16_TIM3 (1 << 0)
266/**@}*/
267
268/** @defgroup syscfg_itline17 ITLINE17 interrupt line 17 status register
269@{*/
270#define SYSCFG_ITLINE17_LPTIM1 (1 << 2)
271#define SYSCFG_ITLINE17_DAC (1 << 1)
272#define SYSCFG_ITLINE17_TIM6 (1 << 0)
273/**@}*/
274
275/** @defgroup syscfg_itline18 ITLINE18 interrupt line 18 status register
276@{*/
277#define SYSCFG_ITLINE18_LPTIM2 (1 << 1)
278#define SYSCFG_ITLINE18_TIM7 (1 << 0)
279/**@}*/
280
281/** @defgroup syscfg_itline19 ITLINE19 interrupt line 19 status register
282@{*/
283#define SYSCFG_ITLINE19_TIM14 (1 << 0)
284/**@}*/
285
286/** @defgroup syscfg_itline20 ITLINE20 interrupt line 20 status register
287@{*/
288#define SYSCFG_ITLINE20_TIM15 (1 << 0)
289/**@}*/
290
291/** @defgroup syscfg_itline21 ITLINE21 interrupt line 21 status register
292@{*/
293#define SYSCFG_ITLINE21_TIM16 (1 << 0)
294/**@}*/
295
296/** @defgroup syscfg_itline22 ITLINE22 interrupt line 22 status register
297@{*/
298#define SYSCFG_ITLINE22_TIM17 (1 << 0)
299/**@}*/
300
301/** @defgroup syscfg_itline23 ITLINE23 interrupt line 23 status register
302@{*/
303#define SYSCFG_ITLINE23_I2C1 (1 << 0)
304/**@}*/
305
306/** @defgroup syscfg_itline24 ITLINE24 interrupt line 24 status register
307@{*/
308#define SYSCFG_ITLINE24_I2C2 (1 << 0)
309/**@}*/
310
311/** @defgroup syscfg_itline25 ITLINE25 interrupt line 25 status register
312@{*/
313#define SYSCFG_ITLINE25_SPI1 (1 << 0)
314/**@}*/
315
316/** @defgroup syscfg_itline26 ITLINE26 interrupt line 26 status register
317@{*/
318#define SYSCFG_ITLINE26_SPI2 (1 << 0)
319/**@}*/
320
321/** @defgroup syscfg_itline27 ITLINE27 interrupt line 27 status register
322@{*/
323#define SYSCFG_ITLINE27_USART1 (1 << 0)
324/**@}*/
325
326/** @defgroup syscfg_itline28 ITLINE28 interrupt line 28 status register
327@{*/
328#define SYSCFG_ITLINE28_USART2 (1 << 0)
329/**@}*/
330
331/** @defgroup syscfg_itline29 ITLINE29 interrupt line 29 status register
332@{*/
333#define SYSCFG_ITLINE29_LPUART1 (1 << 2)
334#define SYSCFG_ITLINE29_USART4 (1 << 1)
335#define SYSCFG_ITLINE29_USART3 (1 << 0)
336/**@}*/
337
338/** @defgroup syscfg_itline30 ITLINE30 interrupt line 30 status register
339@{*/
340#define SYSCFG_ITLINE30_CEC (1 << 0)
341/**@}*/
342
343/** @defgroup syscfg_itline31 ITLINE31 interrupt line 31 status register
344@{*/
345#define SYSCFG_ITLINE31_AES (1 << 1)
346#define SYSCFG_ITLINE31_RNG (1 << 0)
347/**@}*/
348
349/**@}*/
350#endif