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#define	SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x00)

#define	SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x18)

#define	SYSCFG_ITLINE(line) MMIO32(SYSCFG_BASE + 0x80 + (line)*4)

#define	SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23)
	SYSCFG_CFGR1_I2C_PA10_FMP FM+ enable for PA10. More...

#define	SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22)
	SYSCFG_CFGR1_I2C_PA9_FMP FM+ enable for PA9. More...

#define	SYSCFG_CFGR1_I2C2_FMP (1 << 21)
	SYSCFG_CFGR1_I2C2_FMP FM+ driving capability activation for I2C2. More...

#define	SYSCFG_CFGR1_I2C1_FMP (1 << 20)
	SYSCFG_CFGR1_I2C1_FMP FM+ driving capability activation for I2C1. More...

#define	SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19)
	SYSCFG_CFGR1_I2C_PB9_FMP FM+ enable for PB9. More...

#define	SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18)
	SYSCFG_CFGR1_I2C_PB8_FMP FM+ enable for PB8. More...

#define	SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17)
	SYSCFG_CFGR1_I2C_PB7_FMP FM+ enable for PB7. More...

#define	SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16)
	SYSCFG_CFGR1_I2C_PB6_FMP FM+ enable for PB6. More...

#define	SYSCFG_CFGR1_UCPD2_STROBE (1 << 10)
	SYSCFG_CFGR1_UCPD2_STROBE Strobe signal bit for UCPD2. More...

#define	SYSCFG_CFGR1_UCPD1_STROBE (1 << 9)
	SYSCFG_CFGR1_UCPD1_STROBE Strobe signal bit for UCPD1. More...

#define	SYSCFG_CFGR1_BOOSTEN (1 << 8)
	SYSCFG_CFGR1_BOOSTEN I/O analog switch voltage booster enable. More...

#define	SYSCFG_CFGR1_IR_MOD_SHIFT 6

#define	SYSCFG_CFGR1_IR_MOD_MASK 0x03

#define	SYSCFG_CFGR1_IR_MOD_TIM16 0

#define	SYSCFG_CFGR1_IR_MOD_USART1 1

#define	SYSCFG_CFGR1_IR_MOD_USART4 2

#define	SYSCFG_CFGR1_IR_POL (1 << 5)
	SYSCFG_CFGR1_IR_POL IR output polarity selection. More...

#define	SYSCFG_CFGR1_PA12_RMP (1 << 4)
	SYSCFG_CFGR1_PA12_RMP PA12 pin remapping. More...

#define	SYSCFG_CFGR1_PA11_RMP (1 << 3)
	SYSCFG_CFGR1_PA11_RMP PA11 pin remapping. More...

#define	SYSCFG_CFGR1_MEM_MODE_SHIFT 0

#define	SYSCFG_CFGR1_MEM_MODE_MASK 0x03

#define	SYSCFG_CFGR1_MEM_MODE_FLASH 0

#define	SYSCFG_CFGR1_MEM_MODE_SYSTEM 1

#define	SYSCFG_CFGR1_MEM_MODE_SRAM 3

#define	SYSCFG_CFGR2_PB2_CDEN (1 << 23)
	SYSCFG_CFGR2_PB2_CDEN PB2 clamping diode enable. More...

#define	SYSCFG_CFGR2_PB1_CDEN (1 << 22)
	SYSCFG_CFGR2_PB1_CDEN PB1 clamping diode enable. More...

#define	SYSCFG_CFGR2_PB0_CDEN (1 << 21)
	SYSCFG_CFGR2_PB0_CDEN PB0 clamping diode enable. More...

#define	SYSCFG_CFGR2_PA13_CDEN (1 << 20)
	SYSCFG_CFGR2_PA13_CDEN PA13 clamping diode enable. More...

#define	SYSCFG_CFGR2_PA6_CDEN (1 << 19)
	SYSCFG_CFGR2_PA6_CDEN PA6 clamping diode enable. More...

#define	SYSCFG_CFGR2_PA5_CDEN (1 << 18)
	SYSCFG_CFGR2_PA5_CDEN PA5 clamping diode enable. More...

#define	SYSCFG_CFGR2_PA3_CDEN (1 << 17)
	SYSCFG_CFGR2_PA3_CDEN PA3 clamping diode enable. More...

#define	SYSCFG_CFGR2_PA1_CDEN (1 << 16)
	SYSCFG_CFGR2_PA1_CDEN PA1 clamping diode enable. More...

#define	SYSCFG_CFGR2_SRAM_PEF (1 << 8)
	SYSCFG_CFGR2_SRAM_PEF SRAM parity error flag. More...

#define	SYSCFG_CFGR2_ECC_LOCK (1 << 3)
	SYSCFG_CFGR2_ECC_LOCK ECC error lock bit. More...

#define	SYSCFG_CFGR2_PVD_LOCK (1 << 2)
	SYSCFG_CFGR2_PVD_LOCK PVD lock enable bit. More...

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1)
	SYSCFG_CFGR2_SRAM_PARITY_LOCK SRAM parity lock bit. More...

#define	SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0)
	SYSCFG_CFGR2_LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit. More...

#define	SYSCFG_ITLINE0_WWDG (1 << 0)

#define	SYSCFG_ITLINE1_PVDOUT (1 << 0)

#define	SYSCFG_ITLINE2_RTC (1 << 1)

#define	SYSCFG_ITLINE2_TAMP (1 << 0)

#define	SYSCFG_ITLINE3_FLASH_ECC (1 << 1)

#define	SYSCFG_ITLINE3_FLASH_ITF (1 << 0)

#define	SYSCFG_ITLINE4_RCC (1 << 0)

#define	SYSCFG_ITLINE5_EXTI1 (1 << 1)

#define	SYSCFG_ITLINE5_EXTI0 (1 << 0)

#define	SYSCFG_ITLINE6_EXTI3 (1 << 1)

#define	SYSCFG_ITLINE6_EXTI2 (1 << 0)

#define	SYSCFG_ITLINE7_EXTI15 (1 << 11)

#define	SYSCFG_ITLINE7_EXTI14 (1 << 10)

#define	SYSCFG_ITLINE7_EXTI13 (1 << 9)

#define	SYSCFG_ITLINE7_EXTI12 (1 << 8)

#define	SYSCFG_ITLINE7_EXTI11 (1 << 7)

#define	SYSCFG_ITLINE7_EXTI10 (1 << 6)

#define	SYSCFG_ITLINE7_EXTI9 (1 << 5)

#define	SYSCFG_ITLINE7_EXTI8 (1 << 4)

#define	SYSCFG_ITLINE7_EXTI7 (1 << 3)

#define	SYSCFG_ITLINE7_EXTI6 (1 << 2)

#define	SYSCFG_ITLINE7_EXTI5 (1 << 1)

#define	SYSCFG_ITLINE7_EXTI4 (1 << 0)

#define	SYSCFG_ITLINE8_UCPD2 (1 << 1)

#define	SYSCFG_ITLINE8_UCPD1 (1 << 0)

#define	SYSCFG_ITLINE9_DMA1_CH1 (1 << 0)

#define	SYSCFG_ITLINE10_DMA1_CH3 (1 << 1)

#define	SYSCFG_ITLINE10_DMA1_CH2 (1 << 0)

#define	SYSCFG_ITLINE11_DMA1_CH7 (1 << 4)

#define	SYSCFG_ITLINE11_DMA1_CH6 (1 << 3)

#define	SYSCFG_ITLINE11_DMA1_CH5 (1 << 2)

#define	SYSCFG_ITLINE11_DMA1_CH4 (1 << 1)

#define	SYSCFG_ITLINE11_DMAMUX (1 << 0)

#define	SYSCFG_ITLINE12_COMP2 (1 << 2)

#define	SYSCFG_ITLINE12_COMP1 (1 << 1)

#define	SYSCFG_ITLINE12_ADC (1 << 0)

#define	SYSCFG_ITLINE13_TIM1_BRK (1 << 3)

#define	SYSCFG_ITLINE13_TIM1_UPD (1 << 2)

#define	SYSCFG_ITLINE13_TIM1_TRG (1 << 1)

#define	SYSCFG_ITLINE13_TIM1_CCU (1 << 0)

#define	SYSCFG_ITLINE14_TIM1_CC (1 << 0)

#define	SYSCFG_ITLINE15_TIM2 (1 << 0)

#define	SYSCFG_ITLINE16_TIM3 (1 << 0)

#define	SYSCFG_ITLINE17_LPTIM1 (1 << 2)

#define	SYSCFG_ITLINE17_DAC (1 << 1)

#define	SYSCFG_ITLINE17_TIM6 (1 << 0)

#define	SYSCFG_ITLINE18_LPTIM2 (1 << 1)

#define	SYSCFG_ITLINE18_TIM7 (1 << 0)

#define	SYSCFG_ITLINE19_TIM14 (1 << 0)

#define	SYSCFG_ITLINE20_TIM15 (1 << 0)

#define	SYSCFG_ITLINE21_TIM16 (1 << 0)

#define	SYSCFG_ITLINE22_TIM17 (1 << 0)

#define	SYSCFG_ITLINE23_I2C1 (1 << 0)

#define	SYSCFG_ITLINE24_I2C2 (1 << 0)

#define	SYSCFG_ITLINE25_SPI1 (1 << 0)

#define	SYSCFG_ITLINE26_SPI2 (1 << 0)

#define	SYSCFG_ITLINE27_USART1 (1 << 0)

#define	SYSCFG_ITLINE28_USART2 (1 << 0)

#define	SYSCFG_ITLINE29_LPUART1 (1 << 2)

#define	SYSCFG_ITLINE29_USART4 (1 << 1)

#define	SYSCFG_ITLINE29_USART3 (1 << 0)

#define	SYSCFG_ITLINE30_CEC (1 << 0)

#define	SYSCFG_ITLINE31_AES (1 << 1)

#define	SYSCFG_ITLINE31_RNG (1 << 0)

Macros