PLL Configuration structure. More...
#include <rcc.h>
Data Structures | |
| struct | pll_config |
Data Fields | |
| enum rcc_osc | sysclock_source |
| SYSCLK source input selection. More... | |
| uint8_t | pll_source |
| RCC_PLLCKSELR_PLLSRC_xxx value. More... | |
| uint32_t | hse_frequency |
| User specified HSE frequency, 0 if none. More... | |
| struct rcc_pll_config::pll_config | pll1 |
| struct rcc_pll_config::pll_config | pll2 |
| struct rcc_pll_config::pll_config | pll3 |
| PLL1-PLL3 configurations. More... | |
| uint8_t | core_pre |
| Core prescaler note: domain 1. More... | |
| uint8_t | hpre |
| HCLK3 prescaler note: domain 1. More... | |
| uint8_t | ppre1 |
| APB1 Peripheral prescaler note: domain 2. More... | |
| uint8_t | ppre2 |
| APB2 Peripheral prescaler note: domain 2. More... | |
| uint8_t | ppre3 |
| APB3 Peripheral prescaler note: domain 1. More... | |
| uint8_t | ppre4 |
| APB4 Peripheral prescaler note: domain 3. More... | |
| uint8_t | flash_waitstates |
| Latency Value to set for flahs. More... | |
| enum pwr_vos_scale | voltage_scale |
| LDO/SMPS Voltage scale used for this frequency. More... | |
| enum pwr_sys_mode | power_mode |
| LDO/SMPS configuration for device. More... | |
| uint8_t | smps_level |
| If using SMPS, voltage level to set. More... | |
Detailed Description
Field Documentation
◆ core_pre
| uint8_t rcc_pll_config::core_pre |
Core prescaler note: domain 1.
Definition at line 458 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain1().
◆ flash_waitstates
| uint8_t rcc_pll_config::flash_waitstates |
Latency Value to set for flahs.
Definition at line 464 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll().
◆ hpre
| uint8_t rcc_pll_config::hpre |
HCLK3 prescaler note: domain 1.
Definition at line 459 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain1().
◆ hse_frequency
| uint32_t rcc_pll_config::hse_frequency |
User specified HSE frequency, 0 if none.
Definition at line 450 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll(), and rcc_set_and_enable_plls().
◆ pll1
| struct rcc_pll_config::pll_config rcc_pll_config::pll1 |
Referenced by rcc_set_and_enable_plls().
◆ pll2
| struct rcc_pll_config::pll_config rcc_pll_config::pll2 |
Referenced by rcc_set_and_enable_plls().
◆ pll3
| struct rcc_pll_config::pll_config rcc_pll_config::pll3 |
PLL1-PLL3 configurations.
Referenced by rcc_set_and_enable_plls().
◆ pll_source
| uint8_t rcc_pll_config::pll_source |
RCC_PLLCKSELR_PLLSRC_xxx value.
Definition at line 449 of file h7/rcc.h.
Referenced by rcc_set_and_enable_plls().
◆ power_mode
| enum pwr_sys_mode rcc_pll_config::power_mode |
LDO/SMPS configuration for device.
Definition at line 466 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll().
◆ ppre1
| uint8_t rcc_pll_config::ppre1 |
APB1 Peripheral prescaler note: domain 2.
Definition at line 460 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain2().
◆ ppre2
| uint8_t rcc_pll_config::ppre2 |
APB2 Peripheral prescaler note: domain 2.
Definition at line 461 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain2().
◆ ppre3
| uint8_t rcc_pll_config::ppre3 |
APB3 Peripheral prescaler note: domain 1.
Definition at line 462 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain1().
◆ ppre4
| uint8_t rcc_pll_config::ppre4 |
APB4 Peripheral prescaler note: domain 3.
Definition at line 463 of file h7/rcc.h.
Referenced by rcc_clock_setup_domain3().
◆ smps_level
| uint8_t rcc_pll_config::smps_level |
If using SMPS, voltage level to set.
Definition at line 467 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll().
◆ sysclock_source
| enum rcc_osc rcc_pll_config::sysclock_source |
SYSCLK source input selection.
Definition at line 448 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll().
◆ voltage_scale
| enum pwr_vos_scale rcc_pll_config::voltage_scale |
LDO/SMPS Voltage scale used for this frequency.
Definition at line 465 of file h7/rcc.h.
Referenced by rcc_clock_setup_pll().
The documentation for this struct was generated from the following file:
