libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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RCC Registers
STM32L4xx Defines » RCC Defines

Reset / Clock Control Registers. More...

Collaboration diagram for RCC Registers:

Modules

 RCC_CR values
 Clock Control register values.
 

Macros

#define RCC_CR   MMIO32(RCC_BASE + 0x00)
 Clock control register. More...
 
#define RCC_ICSCR   MMIO32(RCC_BASE + 0x04)
 
#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)
 Clock Configuration register. More...
 
#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x0c)
 PLL Configuration register. More...
 
#define RCC_PLLSAI1_CFGR   MMIO32(RCC_BASE + 0x10)
 
#define RCC_PLLSAI2_CFGR   MMIO32(RCC_BASE + 0x14)
 
#define RCC_CIER   MMIO32(RCC_BASE + 0x18)
 Clock interrupt enable register. More...
 
#define RCC_CIFR   MMIO32(RCC_BASE + 0x1c)
 Clock interrupt flag resiger. More...
 
#define RCC_CICR   MMIO32(RCC_BASE + 0x20)
 Clock interrupt clear register. More...
 
#define RCC_AHB1RSTR_OFFSET   0x28
 
#define RCC_AHB1RSTR   MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)
 
#define RCC_AHB2RSTR_OFFSET   0x2c
 
#define RCC_AHB2RSTR   MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)
 
#define RCC_AHB3RSTR_OFFSET   0x30
 
#define RCC_AHB3RSTR   MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)
 
#define RCC_APB1RSTR1_OFFSET   0x38
 
#define RCC_APB1RSTR1   MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)
 
#define RCC_APB1RSTR2_OFFSET   0x3c
 
#define RCC_APB1RSTR2   MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)
 
#define RCC_APB2RSTR_OFFSET   0x40
 
#define RCC_APB2RSTR   MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)
 
#define RCC_AHB1ENR_OFFSET   0x48
 
#define RCC_AHB1ENR   MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)
 
#define RCC_AHB2ENR_OFFSET   0x4c
 
#define RCC_AHB2ENR   MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)
 
#define RCC_AHB3ENR_OFFSET   0x50
 
#define RCC_AHB3ENR   MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)
 
#define RCC_APB1ENR1_OFFSET   0x58
 
#define RCC_APB1ENR1   MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)
 
#define RCC_APB1ENR2_OFFSET   0x5c
 
#define RCC_APB1ENR2   MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)
 
#define RCC_APB2ENR_OFFSET   0x60
 
#define RCC_APB2ENR   MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)
 
#define RCC_AHB1SMENR_OFFSET   0x68
 
#define RCC_AHB1SMENR   MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)
 
#define RCC_AHB2SMENR_OFFSET   0x6c
 
#define RCC_AHB2SMENR   MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)
 
#define RCC_AHB3SMENR_OFFSET   0x70
 
#define RCC_AHB3SMENR   MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)
 
#define RCC_APB1SMENR1_OFFSET   0x78
 
#define RCC_APB1SMENR1   MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)
 
#define RCC_APB1SMENR2_OFFSET   0x7c
 
#define RCC_APB1SMENR2   MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)
 
#define RCC_APB2SMENR_OFFSET   0x80
 
#define RCC_APB2SMENR   MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)
 
#define RCC_CCIPR   MMIO32(RCC_BASE + 0x88)
 
#define RCC_BDCR   MMIO32(RCC_BASE + 0x90)
 Backup Domain control register. More...
 
#define RCC_CSR   MMIO32(RCC_BASE + 0x94)
 Clock control and status register. More...
 
#define RCC_CRRCR   MMIO32(RCC_BASE + 0x98)
 
#define RCC_CCIPR2   MMIO32(RCC_BASE + 0x9C)
 

Detailed Description

Reset / Clock Control Registers.

Macro Definition Documentation

◆ RCC_AHB1ENR

#define RCC_AHB1ENR   MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)

Definition at line 75 of file l4/rcc.h.

◆ RCC_AHB1ENR_OFFSET

#define RCC_AHB1ENR_OFFSET   0x48

Definition at line 74 of file l4/rcc.h.

◆ RCC_AHB1RSTR

#define RCC_AHB1RSTR   MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)

Definition at line 63 of file l4/rcc.h.

◆ RCC_AHB1RSTR_OFFSET

#define RCC_AHB1RSTR_OFFSET   0x28

Definition at line 62 of file l4/rcc.h.

◆ RCC_AHB1SMENR

#define RCC_AHB1SMENR   MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)

Definition at line 87 of file l4/rcc.h.

◆ RCC_AHB1SMENR_OFFSET

#define RCC_AHB1SMENR_OFFSET   0x68

Definition at line 86 of file l4/rcc.h.

◆ RCC_AHB2ENR

#define RCC_AHB2ENR   MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)

Definition at line 77 of file l4/rcc.h.

◆ RCC_AHB2ENR_OFFSET

#define RCC_AHB2ENR_OFFSET   0x4c

Definition at line 76 of file l4/rcc.h.

◆ RCC_AHB2RSTR

#define RCC_AHB2RSTR   MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)

Definition at line 65 of file l4/rcc.h.

◆ RCC_AHB2RSTR_OFFSET

#define RCC_AHB2RSTR_OFFSET   0x2c

Definition at line 64 of file l4/rcc.h.

◆ RCC_AHB2SMENR

#define RCC_AHB2SMENR   MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)

Definition at line 89 of file l4/rcc.h.

◆ RCC_AHB2SMENR_OFFSET

#define RCC_AHB2SMENR_OFFSET   0x6c

Definition at line 88 of file l4/rcc.h.

◆ RCC_AHB3ENR

#define RCC_AHB3ENR   MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)

Definition at line 79 of file l4/rcc.h.

◆ RCC_AHB3ENR_OFFSET

#define RCC_AHB3ENR_OFFSET   0x50

Definition at line 78 of file l4/rcc.h.

◆ RCC_AHB3RSTR

#define RCC_AHB3RSTR   MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)

Definition at line 67 of file l4/rcc.h.

◆ RCC_AHB3RSTR_OFFSET

#define RCC_AHB3RSTR_OFFSET   0x30

Definition at line 66 of file l4/rcc.h.

◆ RCC_AHB3SMENR

#define RCC_AHB3SMENR   MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)

Definition at line 91 of file l4/rcc.h.

◆ RCC_AHB3SMENR_OFFSET

#define RCC_AHB3SMENR_OFFSET   0x70

Definition at line 90 of file l4/rcc.h.

◆ RCC_APB1ENR1

#define RCC_APB1ENR1   MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)

Definition at line 81 of file l4/rcc.h.

◆ RCC_APB1ENR1_OFFSET

#define RCC_APB1ENR1_OFFSET   0x58

Definition at line 80 of file l4/rcc.h.

◆ RCC_APB1ENR2

#define RCC_APB1ENR2   MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)

Definition at line 83 of file l4/rcc.h.

◆ RCC_APB1ENR2_OFFSET

#define RCC_APB1ENR2_OFFSET   0x5c

Definition at line 82 of file l4/rcc.h.

◆ RCC_APB1RSTR1

#define RCC_APB1RSTR1   MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)

Definition at line 69 of file l4/rcc.h.

◆ RCC_APB1RSTR1_OFFSET

#define RCC_APB1RSTR1_OFFSET   0x38

Definition at line 68 of file l4/rcc.h.

◆ RCC_APB1RSTR2

#define RCC_APB1RSTR2   MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)

Definition at line 71 of file l4/rcc.h.

◆ RCC_APB1RSTR2_OFFSET

#define RCC_APB1RSTR2_OFFSET   0x3c

Definition at line 70 of file l4/rcc.h.

◆ RCC_APB1SMENR1

#define RCC_APB1SMENR1   MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)

Definition at line 93 of file l4/rcc.h.

◆ RCC_APB1SMENR1_OFFSET

#define RCC_APB1SMENR1_OFFSET   0x78

Definition at line 92 of file l4/rcc.h.

◆ RCC_APB1SMENR2

#define RCC_APB1SMENR2   MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)

Definition at line 95 of file l4/rcc.h.

◆ RCC_APB1SMENR2_OFFSET

#define RCC_APB1SMENR2_OFFSET   0x7c

Definition at line 94 of file l4/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR   MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)

Definition at line 85 of file l4/rcc.h.

◆ RCC_APB2ENR_OFFSET

#define RCC_APB2ENR_OFFSET   0x60

Definition at line 84 of file l4/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR   MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)

Definition at line 73 of file l4/rcc.h.

◆ RCC_APB2RSTR_OFFSET

#define RCC_APB2RSTR_OFFSET   0x40

Definition at line 72 of file l4/rcc.h.

◆ RCC_APB2SMENR

#define RCC_APB2SMENR   MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)

Definition at line 97 of file l4/rcc.h.

◆ RCC_APB2SMENR_OFFSET

#define RCC_APB2SMENR_OFFSET   0x80

Definition at line 96 of file l4/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR   MMIO32(RCC_BASE + 0x90)

Backup Domain control register.

Definition at line 100 of file l4/rcc.h.

◆ RCC_CCIPR

#define RCC_CCIPR   MMIO32(RCC_BASE + 0x88)

Definition at line 98 of file l4/rcc.h.

◆ RCC_CCIPR2

#define RCC_CCIPR2   MMIO32(RCC_BASE + 0x9C)

Definition at line 104 of file l4/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)

Clock Configuration register.

Definition at line 51 of file l4/rcc.h.

◆ RCC_CICR

#define RCC_CICR   MMIO32(RCC_BASE + 0x20)

Clock interrupt clear register.

Definition at line 61 of file l4/rcc.h.

◆ RCC_CIER

#define RCC_CIER   MMIO32(RCC_BASE + 0x18)

Clock interrupt enable register.

Definition at line 57 of file l4/rcc.h.

◆ RCC_CIFR

#define RCC_CIFR   MMIO32(RCC_BASE + 0x1c)

Clock interrupt flag resiger.

Definition at line 59 of file l4/rcc.h.

◆ RCC_CR

#define RCC_CR   MMIO32(RCC_BASE + 0x00)

Clock control register.

Definition at line 48 of file l4/rcc.h.

◆ RCC_CRRCR

#define RCC_CRRCR   MMIO32(RCC_BASE + 0x98)

Definition at line 103 of file l4/rcc.h.

◆ RCC_CSR

#define RCC_CSR   MMIO32(RCC_BASE + 0x94)

Clock control and status register.

Definition at line 102 of file l4/rcc.h.

◆ RCC_ICSCR

#define RCC_ICSCR   MMIO32(RCC_BASE + 0x04)

Definition at line 49 of file l4/rcc.h.

◆ RCC_PLLCFGR

#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x0c)

PLL Configuration register.

Definition at line 53 of file l4/rcc.h.

◆ RCC_PLLSAI1_CFGR

#define RCC_PLLSAI1_CFGR   MMIO32(RCC_BASE + 0x10)

Definition at line 54 of file l4/rcc.h.

◆ RCC_PLLSAI2_CFGR

#define RCC_PLLSAI2_CFGR   MMIO32(RCC_BASE + 0x14)

Definition at line 55 of file l4/rcc.h.