Defined Constants and Types for the STM32L4xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	RCC Registers
	Reset / Clock Control Registers.

	RCC_CR values
	Clock Control register values.

	MSI Range
	Range of the MSI oscillator Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.

	RCC_CFGR APBx prescale factors
	These can be used for both APB1 and APB2 prescaling.

	RCC_CFGR AHB prescale factors

	RCC_PLLCFGR PLLN values
	Allowed values 8 <= n <= 86.

	RCC_PLLCFGR PLLM values
	Allowed values 1 <= m <= 8.

	RCC_AHBxRSTR reset values (full set)

	RCC_APB1RSTRx reset values (full set)

	RCC_APB2RSTR reset values

	RCC_AHBxENR enable values (full set)

	RCC_APB1ENRx enable values (full set)

	RCC_APB2ENR enable values

	MSI Range after standby values
	Range of the MSI oscillator after returning from standby.

Macros
#define	RCC_CR_MSIRGSEL (1 << 3)

#define	RCC_CR_MSIPLLEN (1 << 2)

#define	RCC_CR_MSIRDY (1 << 1)

#define	RCC_CR_MSION (1 << 0)

#define	RCC_CRRCR_HSI48ON (1 << 0)

#define	RCC_CRRCR_HSI48RDY (1 << 1)

#define	RCC_ICSCR_HSITRIM_SHIFT 24

#define	RCC_ICSCR_HSITRIM_MASK 0x1f

#define	RCC_ICSCR_HSICAL_SHIFT 16

#define	RCC_ICSCR_HSICAL_MASK 0xff

#define	RCC_ICSCR_MSITRIM_SHIFT 8

#define	RCC_ICSCR_MSITRIM_MASK 0xff

#define	RCC_ICSCR_MSICAL_SHIFT 0

#define	RCC_ICSCR_MSICAL_MASK 0xff

#define	RCC_CFGR_MCOPRE_DIV1 0

#define	RCC_CFGR_MCOPRE_DIV2 1

#define	RCC_CFGR_MCOPRE_DIV4 2

#define	RCC_CFGR_MCOPRE_DIV8 3

#define	RCC_CFGR_MCOPRE_DIV16 4

#define	RCC_CFGR_MCOPRE_SHIFT 28

#define	RCC_CFGR_MCOPRE_MASK 0x7

#define	RCC_CFGR_MCO_NOCLK 0x0

#define	RCC_CFGR_MCO_SYSCLK 0x1

#define	RCC_CFGR_MCO_MSI 0x2

#define	RCC_CFGR_MCO_HSI16 0x3

#define	RCC_CFGR_MCO_HSE 0x4

#define	RCC_CFGR_MCO_PLL 0x5

#define	RCC_CFGR_MCO_LSI 0x6

#define	RCC_CFGR_MCO_LSE 0x7

#define	RCC_CFGR_MCO_HSI48 0x8

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0xf

#define	RCC_CFGR_STOPWUCK_MSI (0 << 15)

#define	RCC_CFGR_STOPWUCK_HSI16 (1 << 15)

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_HPRE_MASK 0xf

#define	RCC_CFGR_SWS_MSI 0x0

#define	RCC_CFGR_SWS_HSI16 0x1

#define	RCC_CFGR_SWS_HSE 0x2

#define	RCC_CFGR_SWS_PLL 0x3

#define	RCC_CFGR_SWS_MASK 0x3

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SW_MSI 0x0

#define	RCC_CFGR_SW_HSI16 0x1

#define	RCC_CFGR_SW_HSE 0x2

#define	RCC_CFGR_SW_PLL 0x3

#define	RCC_CFGR_SW_MASK 0x3

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_PLLCFGR_PLLR_SHIFT 25

#define	RCC_PLLCFGR_PLLR_MASK 0x3

#define	RCC_PLLCFGR_PLLR_DIV2 0

#define	RCC_PLLCFGR_PLLR_DIV4 1

#define	RCC_PLLCFGR_PLLR_DIV6 2

#define	RCC_PLLCFGR_PLLR_DIV8 3

#define	RCC_PLLCFGR_PLLREN (1<<24)

#define	RCC_PLLCFGR_PLLQ_SHIFT 21

#define	RCC_PLLCFGR_PLLQ_MASK 0x3

#define	RCC_PLLCFGR_PLLQ_DIV2 0

#define	RCC_PLLCFGR_PLLQ_DIV4 1

#define	RCC_PLLCFGR_PLLQ_DIV6 2

#define	RCC_PLLCFGR_PLLQ_DIV8 3

#define	RCC_PLLCFGR_PLLQEN (1 << 20)

#define	RCC_PLLCFGR_PLLP (1 << 17)

#define	RCC_PLLCFGR_PLLP_DIV7 0

#define	RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP

#define	RCC_PLLPEN (1 << 16)

#define	RCC_PLLCFGR_PLLSRC_SHIFT 0

#define	RCC_PLLCFGR_PLLSRC_MASK 0x3

#define	RCC_PLLCFGR_PLLSRC_NONE 0

#define	RCC_PLLCFGR_PLLSRC_MSI 1

#define	RCC_PLLCFGR_PLLSRC_HSI16 2

#define	RCC_PLLCFGR_PLLSRC_HSE 3

#define	RCC_CIER_HSI48RDYIE (1 << 10)

#define	RCC_CIER_LSE_CSSIE (1 << 9)

#define	RCC_CIER_PLLSAI2RDYIE (1 << 7)

#define	RCC_CIER_PLLSAI1RDYIE (1 << 6)

#define	RCC_CIER_PLLRDYIE (1 << 5)

#define	RCC_CIER_HSERDYIE (1 << 4)

#define	RCC_CIER_HSIRDYIE (1 << 3)

#define	RCC_CIER_MSIRDYIE (1 << 2)

#define	RCC_CIER_LSERDYIE (1 << 1)

#define	RCC_CIER_LSIRDYIE (1 << 0)

#define	RCC_CIFR_HSI48RDYF (1 << 10)

#define	RCC_CIFR_LSECSSF (1 << 9)

#define	RCC_CIFR_CSSF (1 << 8)

#define	RCC_CIFR_PLLSAI2RDYF (1 << 7)

#define	RCC_CIFR_PLLSAI1RDYF (1 << 6)

#define	RCC_CIFR_PLLRDYF (1 << 5)

#define	RCC_CIFR_HSERDYF (1 << 4)

#define	RCC_CIFR_HSIRDYF (1 << 3)

#define	RCC_CIFR_MSIRDYF (1 << 2)

#define	RCC_CIFR_LSERDYF (1 << 1)

#define	RCC_CIFR_LSIRDYF (1 << 0)

#define	RCC_CICR_HSI48RDYC (1 << 10)

#define	RCC_CICR_LSECSSC (1 << 9)

#define	RCC_CICR_CSSC (1 << 8)

#define	RCC_CICR_PLLSAI2RDYC (1 << 7)

#define	RCC_CICR_PLLSAI1RDYC (1 << 6)

#define	RCC_CICR_PLLRDYC (1 << 5)

#define	RCC_CICR_HSERDYC (1 << 4)

#define	RCC_CICR_HSIRDYC (1 << 3)

#define	RCC_CICR_MSIRDYC (1 << 2)

#define	RCC_CICR_LSERDYC (1 << 1)

#define	RCC_CICR_LSIRDYC (1 << 0)

#define	RCC_AHB1SMENR_TSCSMEN (1 << 16)

#define	RCC_AHB1SMENR_CRCSMEN (1 << 12)

#define	RCC_AHB1SMENR_SRAM1SMEN (1 << 9)

#define	RCC_AHB1SMENR_FLASHSMEN (1 << 8)

#define	RCC_AHB1SMENR_DMA2SMEN (1 << 1)

#define	RCC_AHB1SMENR_DMA1SMEN (1 << 0)

#define	RCC_AHB2SMENR_RNGSMEN (1 << 18)

#define	RCC_AHB2SMENR_AESSMEN (1 << 16)

#define	RCC_AHB2SMENR_ADCSMEN (1 << 13)

#define	RCC_AHB2SMENR_OTGFSSMEN (1 << 12)

#define	RCC_AHB2SMENR_SRAM2SMEN (1 << 9)

#define	RCC_AHB2SMENR_GPIOHSMEN (1 << 7)

#define	RCC_AHB2SMENR_GPIOGSMEN (1 << 6)

#define	RCC_AHB2SMENR_GPIOFSMEN (1 << 5)

#define	RCC_AHB2SMENR_GPIOESMEN (1 << 4)

#define	RCC_AHB2SMENR_GPIODSMEN (1 << 3)

#define	RCC_AHB2SMENR_GPIOCSMEN (1 << 2)

#define	RCC_AHB2SMENR_GPIOBSMEN (1 << 1)

#define	RCC_AHB2SMENR_GPIOASMEN (1 << 0)

#define	RCC_AHB3SMENR_QSPISMEN (1 << 8)

#define	RCC_AHB3SMENR_FMCSMEN (1 << 0)

#define	RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)

#define	RCC_APB1SMENR1_OPAMPSMEN (1 << 30)

#define	RCC_APB1SMENR1_DAC1SMEN (1 << 29)

#define	RCC_APB1SMENR1_PWRSMEN (1 << 28)

#define	RCC_APB1SMENR1_CAN2SMEN (1 << 26)

#define	RCC_APB1SMENR1_CAN1SMEN (1 << 25)

#define	RCC_APB1SMENR1_I2C3SMEN (1 << 23)

#define	RCC_APB1SMENR1_I2C2SMEN (1 << 22)

#define	RCC_APB1SMENR1_I2C1SMEN (1 << 21)

#define	RCC_APB1SMENR1_UART5SMEN (1 << 20)

#define	RCC_APB1SMENR1_UART4SMEN (1 << 19)

#define	RCC_APB1SMENR1_USART3SMEN (1 << 18)

#define	RCC_APB1SMENR1_USART2SMEN (1 << 17)

#define	RCC_APB1SMENR1_SPI3SMEN (1 << 15)

#define	RCC_APB1SMENR1_SPI2SMEN (1 << 14)

#define	RCC_APB1SMENR1_WWDGSMEN (1 << 11)

#define	RCC_APB1SMENR1_LCDSMEN (1 << 9)

#define	RCC_APB1SMENR1_TIM7SMEN (1 << 5)

#define	RCC_APB1SMENR1_TIM6SMEN (1 << 4)

#define	RCC_APB1SMENR1_TIM5SMEN (1 << 3)

#define	RCC_APB1SMENR1_TIM4SMEN (1 << 2)

#define	RCC_APB1SMENR1_TIM3SMEN (1 << 1)

#define	RCC_APB1SMENR1_TIM2SMEN (1 << 0)

#define	RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)

#define	RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)

#define	RCC_APB1SMENR2_LPUART1SMEN (1 << 0)

#define	RCC_APB2SMENR_DFSDMSMEN (1 << 24)

#define	RCC_APB2SMENR_SAI2SMEN (1 << 22)

#define	RCC_APB2SMENR_SAI1SMEN (1 << 21)

#define	RCC_APB2SMENR_TIM17SMEN (1 << 18)

#define	RCC_APB2SMENR_TIM16SMEN (1 << 17)

#define	RCC_APB2SMENR_TIM15SMEN (1 << 16)

#define	RCC_APB2SMENR_USART1SMEN (1 << 14)

#define	RCC_APB2SMENR_TIM8SMEN (1 << 13)

#define	RCC_APB2SMENR_SPI1SMEN (1 << 12)

#define	RCC_APB2SMENR_TIM1SMEN (1 << 11)

#define	RCC_APB2SMENR_SDMMC1SMEN (1 << 10)

#define	RCC_APB2SMENR_SYSCFGSMEN (1 << 0)

#define	RCC_CCIPR_DFSDMSEL (1 << 31)

#define	RCC_CCIPR_SWPMI1SEL (1 << 30)

#define	RCC_CCIPR_ADCSEL_NONE 0

#define	RCC_CCIPR_ADCSEL_PLLSAI1R 1

#define	RCC_CCIPR_ADCSEL_PLLSAI2R 2

#define	RCC_CCIPR_ADCSEL_SYSCLK 3

#define	RCC_CCIPR_ADCSEL_MASK 0x3

#define	RCC_CCIPR_ADCSEL_SHIFT 28

#define	RCC_CCIPR_CLK48SEL_HSI48 0

#define	RCC_CCIPR_CLK48SEL_PLLSAI1Q 1

#define	RCC_CCIPR_CLK48SEL_PLL 2

#define	RCC_CCIPR_CLK48SEL_MSI 3

#define	RCC_CCIPR_CLK48SEL_MASK 0x3

#define	RCC_CCIPR_CLK48SEL_SHIFT 26

#define	RCC_CCIPR_SAIxSEL_PLLSAI1P 0

#define	RCC_CCIPR_SAIxSEL_PLLSAI2P 1

#define	RCC_CCIPR_SAIxSEL_PLL 2

#define	RCC_CCIPR_SAIxSEL_EXT 3

#define	RCC_CCIPR_SAIxSEL_MASK 0x3

#define	RCC_CCIPR_SAI2SEL_SHIFT 24

#define	RCC_CCIPR_SAI1SEL_SHIFT 22

#define	RCC_CCIPR_LPTIMxSEL_APB 0

#define	RCC_CCIPR_LPTIMxSEL_LSI 1

#define	RCC_CCIPR_LPTIMxSEL_HSI16 2

#define	RCC_CCIPR_LPTIMxSEL_LSE 3

#define	RCC_CCIPR_LPTIMxSEL_MASK 0x3

#define	RCC_CCIPR_LPTIM2SEL_SHIFT 20

#define	RCC_CCIPR_LPTIM1SEL_SHIFT 18

#define	RCC_CCIPR_I2CxSEL_APB 0

#define	RCC_CCIPR_I2CxSEL_SYSCLK 1

#define	RCC_CCIPR_I2CxSEL_HSI16 2

#define	RCC_CCIPR_I2CxSEL_MASK 0x3

#define	RCC_CCIPR_I2C4SEL_SHIFT 0

#define	RCC_CCIPR_I2C3SEL_SHIFT 16

#define	RCC_CCIPR_I2C2SEL_SHIFT 14

#define	RCC_CCIPR_I2C1SEL_SHIFT 12

#define	RCC_CCIPR_LPUART1SEL_APB 0

#define	RCC_CCIPR_LPUART1SEL_SYS 1

#define	RCC_CCIPR_LPUART1SEL_HSI16 2

#define	RCC_CCIPR_LPUART1SEL_LSE 3

#define	RCC_CCIPR_LPUART1SEL_MASK 0x3

#define	RCC_CCIPR_LPUART1SEL_SHIFT 10

#define	RCC_CCIPR_USARTxSEL_APB 0

#define	RCC_CCIPR_USARTxSEL_SYSCLK 1

#define	RCC_CCIPR_USARTxSEL_HSI16 2

#define	RCC_CCIPR_USARTxSEL_LSE 3

#define	RCC_CCIPR_USARTxSEL_MASK 0x3

#define	RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APB

#define	RCC_CCIPR_UARTxSEL_SYSCLK RCC_CCIPR_USARTxSEL_SYSCLK

#define	RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16

#define	RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE

#define	RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASK

#define	RCC_CCIPR_UART5SEL_SHIFT 8

#define	RCC_CCIPR_UART4SEL_SHIFT 6

#define	RCC_CCIPR_USART3SEL_SHIFT 4

#define	RCC_CCIPR_USART2SEL_SHIFT 2

#define	RCC_CCIPR_USART1SEL_SHIFT 0

#define	RCC_BDCR_LSCOSEL (1 << 25)

#define	RCC_BDCR_LSCOEN (1 << 24)

#define	RCC_BDCR_BDRST (1 << 16)

#define	RCC_BDCR_RTCEN (1 << 15)

#define	RCC_BDCR_RTCSEL_NONE 0

#define	RCC_BDCR_RTCSEL_LSE 1

#define	RCC_BDCR_RTCSEL_LSI 2

#define	RCC_BDCR_RTCSEL_HSEDIV32 3

#define	RCC_BDCR_RTCSEL_SHIFT 8

#define	RCC_BDCR_RTCSEL_MASK 0x3

#define	RCC_BDCR_LSESYSDIS (1 << 7)

#define	RCC_BDCR_LSECSSD (1 << 6)

#define	RCC_BDCR_LSECSSON (1 << 5)

#define	RCC_BDCR_LSEDRV_LOW 0

#define	RCC_BDCR_LSEDRV_MEDLOW 1

#define	RCC_BDCR_LSEDRV_MEDHIGH 2

#define	RCC_BDCR_LSEDRV_HIGH 3

#define	RCC_BDCR_LSEDRV_SHIFT 3

#define	RCC_BDCR_LSEDRV_MASK 0x3

#define	RCC_BDCR_LSEBYP (1 << 2)

#define	RCC_BDCR_LSERDY (1 << 1)

#define	RCC_BDCR_LSEON (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_BORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_OBLRSTF (1 << 25)

#define	RCC_CSR_FWRSTF (1 << 24)

#define	RCC_CSR_RMVF (1 << 23)

#define	RCC_CSR_RESET_FLAGS

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_config_entry { RCC_CLOCK_VRANGE1_80MHZ , RCC_CLOCK_CONFIG_END }

enum	rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI16 , RCC_MSI , RCC_LSE , RCC_LSI , RCC_HSI48 }

enum	rcc_periph_clken { RCC_TSC = _REG_BIT(RCC_AHB1ENR_OFFSET, 16) , RCC_CRC = _REG_BIT(RCC_AHB1ENR_OFFSET, 12) , RCC_FLASH = _REG_BIT(RCC_AHB1ENR_OFFSET, 8) , RCC_DMA2 = _REG_BIT(RCC_AHB1ENR_OFFSET, 1) , RCC_DMA1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 0) , RCC_RNG = _REG_BIT(RCC_AHB2ENR_OFFSET, 18) , RCC_AES = _REG_BIT(RCC_AHB2ENR_OFFSET, 16) , RCC_ADC = _REG_BIT(RCC_AHB2ENR_OFFSET, 13) , RCC_ADC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13) , RCC_OTGFS = _REG_BIT(RCC_AHB2ENR_OFFSET, 12) , RCC_GPIOH = _REG_BIT(RCC_AHB2ENR_OFFSET, 7) , RCC_GPIOG = _REG_BIT(RCC_AHB2ENR_OFFSET, 6) , RCC_GPIOF = _REG_BIT(RCC_AHB2ENR_OFFSET, 5) , RCC_GPIOE = _REG_BIT(RCC_AHB2ENR_OFFSET, 4) , RCC_GPIOD = _REG_BIT(RCC_AHB2ENR_OFFSET, 3) , RCC_GPIOC = _REG_BIT(RCC_AHB2ENR_OFFSET, 2) , RCC_GPIOB = _REG_BIT(RCC_AHB2ENR_OFFSET, 1) , RCC_GPIOA = _REG_BIT(RCC_AHB2ENR_OFFSET, 0) , RCC_QSPI = _REG_BIT(RCC_AHB3ENR_OFFSET, 8) , RCC_FMC = _REG_BIT(RCC_AHB3ENR_OFFSET, 0) , RCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31) , RCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30) , RCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29) , RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28) , RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 26) , RCC_CAN2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 26) , RCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25) , RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 24) , RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23) , RCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22) , RCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21) , RCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20) , RCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19) , RCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18) , RCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17) , RCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15) , RCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14) , RCC_LCD = _REG_BIT(RCC_APB1ENR1_OFFSET, 9) , RCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5) , RCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4) , RCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3) , RCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2) , RCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1) , RCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0) , RCC_LPTIM2 = _REG_BIT(RCC_APB1ENR2_OFFSET, 5) , RCC_SWPMI1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 2) , RCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0) , RCC_DFSDM = _REG_BIT(RCC_APB2ENR_OFFSET, 24) , RCC_SAI2 = _REG_BIT(RCC_APB2ENR_OFFSET, 22) , RCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21) , RCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18) , RCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17) , RCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16) , RCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14) , RCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13) , RCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12) , RCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11) , RCC_SDMMC1 = _REG_BIT(RCC_APB2ENR_OFFSET, 10) , RCC_FW = _REG_BIT(RCC_APB2ENR_OFFSET, 7) , RCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0) , SCC_TSC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 16) , SCC_CRC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 12) , SCC_SRAM1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 9) , SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8) , SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1) , SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0) , SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18) , SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16) , SCC_ADC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13) , SCC_ADC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13) , SCC_OTGFS = _REG_BIT(RCC_AHB2SMENR_OFFSET, 12) , SCC_SRAM2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 9) , SCC_GPIOH = _REG_BIT(RCC_AHB2SMENR_OFFSET, 7) , SCC_GPIOG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 6) , SCC_GPIOF = _REG_BIT(RCC_AHB2SMENR_OFFSET, 5) , SCC_GPIOE = _REG_BIT(RCC_AHB2SMENR_OFFSET, 4) , SCC_GPIOD = _REG_BIT(RCC_AHB2SMENR_OFFSET, 3) , SCC_GPIOC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 2) , SCC_GPIOB = _REG_BIT(RCC_AHB2SMENR_OFFSET, 1) , SCC_GPIOA = _REG_BIT(RCC_AHB2SMENR_OFFSET, 0) , SCC_QSPI = _REG_BIT(RCC_AHB3SMENR_OFFSET, 8) , SCC_FMC = _REG_BIT(RCC_AHB3SMENR_OFFSET, 0) , SCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31) , SCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30) , SCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29) , SCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28) , SCC_CAN2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 26) , SCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25) , SCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23) , SCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22) , SCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21) , SCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20) , SCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19) , SCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18) , SCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17) , SCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15) , SCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14) , SCC_WWDG = _REG_BIT(RCC_APB1ENR1_OFFSET, 11) , SCC_LCD = _REG_BIT(RCC_APB1ENR1_OFFSET, 9) , SCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5) , SCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4) , SCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3) , SCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2) , SCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1) , SCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0) , SCC_LPTIM2 = _REG_BIT(RCC_APB1ENR2_OFFSET, 5) , SCC_SWPMI1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 2) , SCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0) , SCC_DFSDM = _REG_BIT(RCC_APB2ENR_OFFSET, 24) , SCC_SAI2 = _REG_BIT(RCC_APB2ENR_OFFSET, 22) , SCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21) , SCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18) , SCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17) , SCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16) , SCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14) , SCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13) , SCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12) , SCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11) , SCC_SDMMC1 = _REG_BIT(RCC_APB2ENR_OFFSET, 10) , SCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0) }

enum	rcc_periph_rst { RST_TSC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 16) , RST_CRC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 12) , RST_FLASH = _REG_BIT(RCC_AHB1RSTR_OFFSET, 8) , RST_DMA2 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 1) , RST_DMA1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 0) , RST_RNG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 18) , RST_AES = _REG_BIT(RCC_AHB2RSTR_OFFSET, 16) , RST_ADC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13) , RST_ADC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13) , RST_OTGFS = _REG_BIT(RCC_AHB2RSTR_OFFSET, 12) , RST_GPIOH = _REG_BIT(RCC_AHB2RSTR_OFFSET, 7) , RST_GPIOG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 6) , RST_GPIOF = _REG_BIT(RCC_AHB2RSTR_OFFSET, 5) , RST_GPIOE = _REG_BIT(RCC_AHB2RSTR_OFFSET, 4) , RST_GPIOD = _REG_BIT(RCC_AHB2RSTR_OFFSET, 3) , RST_GPIOC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 2) , RST_GPIOB = _REG_BIT(RCC_AHB2RSTR_OFFSET, 1) , RST_GPIOA = _REG_BIT(RCC_AHB2RSTR_OFFSET, 0) , RST_QSPI = _REG_BIT(RCC_AHB3RSTR_OFFSET, 8) , RST_FMC = _REG_BIT(RCC_AHB3RSTR_OFFSET, 0) , RST_LPTIM1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 31) , RST_OPAMP = _REG_BIT(RCC_APB1RSTR1_OFFSET, 30) , RST_DAC1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 29) , RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28) , RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26) , RST_CAN2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26) , RST_CAN1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25) , RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 24) , RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23) , RST_I2C2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 22) , RST_I2C1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 21) , RST_UART5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 20) , RST_UART4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 19) , RST_USART3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 18) , RST_USART2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 17) , RST_SPI3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 15) , RST_SPI2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 14) , RST_LCD = _REG_BIT(RCC_APB1RSTR1_OFFSET, 9) , RST_TIM7 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 5) , RST_TIM6 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 4) , RST_TIM5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 3) , RST_TIM4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 2) , RST_TIM3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 1) , RST_TIM2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 0) , RST_LPTIM2 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 5) , RST_SWPMI1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 2) , RST_LPUART1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 0) , RST_DFSDM = _REG_BIT(RCC_APB2RSTR_OFFSET, 24) , RST_SAI2 = _REG_BIT(RCC_APB2RSTR_OFFSET, 22) , RST_SAI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 21) , RST_TIM17 = _REG_BIT(RCC_APB2RSTR_OFFSET, 18) , RST_TIM16 = _REG_BIT(RCC_APB2RSTR_OFFSET, 17) , RST_TIM15 = _REG_BIT(RCC_APB2RSTR_OFFSET, 16) , RST_USART1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 14) , RST_TIM8 = _REG_BIT(RCC_APB2RSTR_OFFSET, 13) , RST_SPI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 12) , RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11) , RST_SDMMC1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 10) , RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_main_pll (uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)

uint32_t	rcc_system_clock_source (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_set_msi_range (uint32_t msi_range)
	Set the msi run time range. More...

void	rcc_set_msi_range_standby (uint32_t msi_range)
	Set the msi range after reset/standby. More...

void	rcc_pll_output_enable (uint32_t pllout)
	Enable PLL Output. More...

void	rcc_set_clock48_source (uint32_t clksel)
	Set clock source for 48MHz clock. More...

void	rcc_enable_rtc_clock (void)
	Enable the RTC clock. More...

void	rcc_disable_rtc_clock (void)
	Disable the RTC clock. More...

void	rcc_set_rtc_clock_source (enum rcc_osc clk)
	Set the source for the RTC clock. More...

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
const struct rcc_clock_scale	rcc_hsi16_configs [RCC_CLOCK_CONFIG_END]

uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

Detailed Description

Defined Constants and Types for the STM32L4xx Reset and Clock Control

Version: 1.0.0

Author: © 2015 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Date: 12 November 2015

LGPL License Terms libopencm3 License

Author: © 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 782 of file l4/rcc.h.

◆ RCC_AHB1SMENR_CRCSMEN

#define RCC_AHB1SMENR_CRCSMEN (1 << 12)

Definition at line 542 of file l4/rcc.h.

◆ RCC_AHB1SMENR_DMA1SMEN

#define RCC_AHB1SMENR_DMA1SMEN (1 << 0)

Definition at line 546 of file l4/rcc.h.

◆ RCC_AHB1SMENR_DMA2SMEN

#define RCC_AHB1SMENR_DMA2SMEN (1 << 1)

Definition at line 545 of file l4/rcc.h.

◆ RCC_AHB1SMENR_FLASHSMEN

#define RCC_AHB1SMENR_FLASHSMEN (1 << 8)

Definition at line 544 of file l4/rcc.h.

◆ RCC_AHB1SMENR_SRAM1SMEN

#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9)

Definition at line 543 of file l4/rcc.h.

◆ RCC_AHB1SMENR_TSCSMEN

#define RCC_AHB1SMENR_TSCSMEN (1 << 16)

Definition at line 541 of file l4/rcc.h.

◆ RCC_AHB2SMENR_ADCSMEN

#define RCC_AHB2SMENR_ADCSMEN (1 << 13)

Definition at line 552 of file l4/rcc.h.

◆ RCC_AHB2SMENR_AESSMEN

#define RCC_AHB2SMENR_AESSMEN (1 << 16)

Definition at line 551 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOASMEN

#define RCC_AHB2SMENR_GPIOASMEN (1 << 0)

Definition at line 562 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOBSMEN

#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1)

Definition at line 561 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOCSMEN

#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2)

Definition at line 560 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIODSMEN

#define RCC_AHB2SMENR_GPIODSMEN (1 << 3)

Definition at line 559 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOESMEN

#define RCC_AHB2SMENR_GPIOESMEN (1 << 4)

Definition at line 558 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOFSMEN

#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5)

Definition at line 557 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOGSMEN

#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6)

Definition at line 556 of file l4/rcc.h.

◆ RCC_AHB2SMENR_GPIOHSMEN

#define RCC_AHB2SMENR_GPIOHSMEN (1 << 7)

Definition at line 555 of file l4/rcc.h.

◆ RCC_AHB2SMENR_OTGFSSMEN

#define RCC_AHB2SMENR_OTGFSSMEN (1 << 12)

Definition at line 553 of file l4/rcc.h.

◆ RCC_AHB2SMENR_RNGSMEN

#define RCC_AHB2SMENR_RNGSMEN (1 << 18)

Definition at line 550 of file l4/rcc.h.

◆ RCC_AHB2SMENR_SRAM2SMEN

#define RCC_AHB2SMENR_SRAM2SMEN (1 << 9)

Definition at line 554 of file l4/rcc.h.

◆ RCC_AHB3SMENR_FMCSMEN

#define RCC_AHB3SMENR_FMCSMEN (1 << 0)

Definition at line 567 of file l4/rcc.h.

◆ RCC_AHB3SMENR_QSPISMEN

#define RCC_AHB3SMENR_QSPISMEN (1 << 8)

Definition at line 566 of file l4/rcc.h.

◆ RCC_APB1SMENR1_CAN1SMEN

#define RCC_APB1SMENR1_CAN1SMEN (1 << 25)

Definition at line 576 of file l4/rcc.h.

◆ RCC_APB1SMENR1_CAN2SMEN

#define RCC_APB1SMENR1_CAN2SMEN (1 << 26)

Definition at line 575 of file l4/rcc.h.

◆ RCC_APB1SMENR1_DAC1SMEN

#define RCC_APB1SMENR1_DAC1SMEN (1 << 29)

Definition at line 573 of file l4/rcc.h.

◆ RCC_APB1SMENR1_I2C1SMEN

#define RCC_APB1SMENR1_I2C1SMEN (1 << 21)

Definition at line 579 of file l4/rcc.h.

◆ RCC_APB1SMENR1_I2C2SMEN

#define RCC_APB1SMENR1_I2C2SMEN (1 << 22)

Definition at line 578 of file l4/rcc.h.

◆ RCC_APB1SMENR1_I2C3SMEN

#define RCC_APB1SMENR1_I2C3SMEN (1 << 23)

Definition at line 577 of file l4/rcc.h.

◆ RCC_APB1SMENR1_LCDSMEN

#define RCC_APB1SMENR1_LCDSMEN (1 << 9)

Definition at line 587 of file l4/rcc.h.

◆ RCC_APB1SMENR1_LPTIM1SMEN

#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)

Definition at line 571 of file l4/rcc.h.

◆ RCC_APB1SMENR1_OPAMPSMEN

#define RCC_APB1SMENR1_OPAMPSMEN (1 << 30)

Definition at line 572 of file l4/rcc.h.

◆ RCC_APB1SMENR1_PWRSMEN

#define RCC_APB1SMENR1_PWRSMEN (1 << 28)

Definition at line 574 of file l4/rcc.h.

◆ RCC_APB1SMENR1_SPI2SMEN

#define RCC_APB1SMENR1_SPI2SMEN (1 << 14)

Definition at line 585 of file l4/rcc.h.

◆ RCC_APB1SMENR1_SPI3SMEN

#define RCC_APB1SMENR1_SPI3SMEN (1 << 15)

Definition at line 584 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM2SMEN

#define RCC_APB1SMENR1_TIM2SMEN (1 << 0)

Definition at line 593 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM3SMEN

#define RCC_APB1SMENR1_TIM3SMEN (1 << 1)

Definition at line 592 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM4SMEN

#define RCC_APB1SMENR1_TIM4SMEN (1 << 2)

Definition at line 591 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM5SMEN

#define RCC_APB1SMENR1_TIM5SMEN (1 << 3)

Definition at line 590 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM6SMEN

#define RCC_APB1SMENR1_TIM6SMEN (1 << 4)

Definition at line 589 of file l4/rcc.h.

◆ RCC_APB1SMENR1_TIM7SMEN

#define RCC_APB1SMENR1_TIM7SMEN (1 << 5)

Definition at line 588 of file l4/rcc.h.

◆ RCC_APB1SMENR1_UART4SMEN

#define RCC_APB1SMENR1_UART4SMEN (1 << 19)

Definition at line 581 of file l4/rcc.h.

◆ RCC_APB1SMENR1_UART5SMEN

#define RCC_APB1SMENR1_UART5SMEN (1 << 20)

Definition at line 580 of file l4/rcc.h.

◆ RCC_APB1SMENR1_USART2SMEN

#define RCC_APB1SMENR1_USART2SMEN (1 << 17)

Definition at line 583 of file l4/rcc.h.

◆ RCC_APB1SMENR1_USART3SMEN

#define RCC_APB1SMENR1_USART3SMEN (1 << 18)

Definition at line 582 of file l4/rcc.h.

◆ RCC_APB1SMENR1_WWDGSMEN

#define RCC_APB1SMENR1_WWDGSMEN (1 << 11)

Definition at line 586 of file l4/rcc.h.

◆ RCC_APB1SMENR2_LPTIM2SMEN

#define RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)

Definition at line 597 of file l4/rcc.h.

◆ RCC_APB1SMENR2_LPUART1SMEN

#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0)

Definition at line 599 of file l4/rcc.h.

◆ RCC_APB1SMENR2_SWPMI1SMEN

#define RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)

Definition at line 598 of file l4/rcc.h.

◆ RCC_APB2SMENR_DFSDMSMEN

#define RCC_APB2SMENR_DFSDMSMEN (1 << 24)

Definition at line 603 of file l4/rcc.h.

◆ RCC_APB2SMENR_SAI1SMEN

#define RCC_APB2SMENR_SAI1SMEN (1 << 21)

Definition at line 605 of file l4/rcc.h.

◆ RCC_APB2SMENR_SAI2SMEN

#define RCC_APB2SMENR_SAI2SMEN (1 << 22)

Definition at line 604 of file l4/rcc.h.

◆ RCC_APB2SMENR_SDMMC1SMEN

#define RCC_APB2SMENR_SDMMC1SMEN (1 << 10)

Definition at line 613 of file l4/rcc.h.

◆ RCC_APB2SMENR_SPI1SMEN

#define RCC_APB2SMENR_SPI1SMEN (1 << 12)

Definition at line 611 of file l4/rcc.h.

◆ RCC_APB2SMENR_SYSCFGSMEN

#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0)

Definition at line 614 of file l4/rcc.h.

◆ RCC_APB2SMENR_TIM15SMEN

#define RCC_APB2SMENR_TIM15SMEN (1 << 16)

Definition at line 608 of file l4/rcc.h.

◆ RCC_APB2SMENR_TIM16SMEN

#define RCC_APB2SMENR_TIM16SMEN (1 << 17)

Definition at line 607 of file l4/rcc.h.

◆ RCC_APB2SMENR_TIM17SMEN

#define RCC_APB2SMENR_TIM17SMEN (1 << 18)

Definition at line 606 of file l4/rcc.h.

◆ RCC_APB2SMENR_TIM1SMEN

#define RCC_APB2SMENR_TIM1SMEN (1 << 11)

Definition at line 612 of file l4/rcc.h.

◆ RCC_APB2SMENR_TIM8SMEN

#define RCC_APB2SMENR_TIM8SMEN (1 << 13)

Definition at line 610 of file l4/rcc.h.

◆ RCC_APB2SMENR_USART1SMEN

#define RCC_APB2SMENR_USART1SMEN (1 << 14)

Definition at line 609 of file l4/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST (1 << 16)

Definition at line 687 of file l4/rcc.h.

◆ RCC_BDCR_LSCOEN

#define RCC_BDCR_LSCOEN (1 << 24)

Definition at line 686 of file l4/rcc.h.

◆ RCC_BDCR_LSCOSEL

#define RCC_BDCR_LSCOSEL (1 << 25)

Definition at line 685 of file l4/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP (1 << 2)

Definition at line 708 of file l4/rcc.h.

◆ RCC_BDCR_LSECSSD

#define RCC_BDCR_LSECSSD (1 << 6)

Definition at line 698 of file l4/rcc.h.

◆ RCC_BDCR_LSECSSON

#define RCC_BDCR_LSECSSON (1 << 5)

Definition at line 699 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_HIGH

#define RCC_BDCR_LSEDRV_HIGH 3

Definition at line 704 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_LOW

#define RCC_BDCR_LSEDRV_LOW 0

Definition at line 701 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_MASK

#define RCC_BDCR_LSEDRV_MASK 0x3

Definition at line 706 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_MEDHIGH

#define RCC_BDCR_LSEDRV_MEDHIGH 2

Definition at line 703 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_MEDLOW

#define RCC_BDCR_LSEDRV_MEDLOW 1

Definition at line 702 of file l4/rcc.h.

◆ RCC_BDCR_LSEDRV_SHIFT

#define RCC_BDCR_LSEDRV_SHIFT 3

Definition at line 705 of file l4/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON (1 << 0)

Definition at line 710 of file l4/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY (1 << 1)

Definition at line 709 of file l4/rcc.h.

◆ RCC_BDCR_LSESYSDIS

#define RCC_BDCR_LSESYSDIS (1 << 7)

Definition at line 697 of file l4/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN (1 << 15)

Definition at line 688 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_HSEDIV32

#define RCC_BDCR_RTCSEL_HSEDIV32 3

Definition at line 693 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_LSE

#define RCC_BDCR_RTCSEL_LSE 1

Definition at line 691 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_LSI

#define RCC_BDCR_RTCSEL_LSI 2

Definition at line 692 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_MASK

#define RCC_BDCR_RTCSEL_MASK 0x3

Definition at line 695 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_NONE

#define RCC_BDCR_RTCSEL_NONE 0

Definition at line 690 of file l4/rcc.h.

◆ RCC_BDCR_RTCSEL_SHIFT

#define RCC_BDCR_RTCSEL_SHIFT 8

Definition at line 694 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_MASK

#define RCC_CCIPR_ADCSEL_MASK 0x3

Definition at line 625 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_NONE

#define RCC_CCIPR_ADCSEL_NONE 0

Definition at line 621 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_PLLSAI1R

#define RCC_CCIPR_ADCSEL_PLLSAI1R 1

Definition at line 622 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_PLLSAI2R

#define RCC_CCIPR_ADCSEL_PLLSAI2R 2

Definition at line 623 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_SHIFT

#define RCC_CCIPR_ADCSEL_SHIFT 28

Definition at line 626 of file l4/rcc.h.

◆ RCC_CCIPR_ADCSEL_SYSCLK

#define RCC_CCIPR_ADCSEL_SYSCLK 3

Definition at line 624 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_HSI48

#define RCC_CCIPR_CLK48SEL_HSI48 0

Definition at line 628 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_MASK

#define RCC_CCIPR_CLK48SEL_MASK 0x3

Definition at line 632 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_MSI

#define RCC_CCIPR_CLK48SEL_MSI 3

Definition at line 631 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_PLL

#define RCC_CCIPR_CLK48SEL_PLL 2

Definition at line 630 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_PLLSAI1Q

#define RCC_CCIPR_CLK48SEL_PLLSAI1Q 1

Definition at line 629 of file l4/rcc.h.

◆ RCC_CCIPR_CLK48SEL_SHIFT

#define RCC_CCIPR_CLK48SEL_SHIFT 26

Definition at line 633 of file l4/rcc.h.

◆ RCC_CCIPR_DFSDMSEL

#define RCC_CCIPR_DFSDMSEL (1 << 31)

Definition at line 618 of file l4/rcc.h.

◆ RCC_CCIPR_I2C1SEL_SHIFT

#define RCC_CCIPR_I2C1SEL_SHIFT 12

Definition at line 658 of file l4/rcc.h.

◆ RCC_CCIPR_I2C2SEL_SHIFT

#define RCC_CCIPR_I2C2SEL_SHIFT 14

Definition at line 657 of file l4/rcc.h.

◆ RCC_CCIPR_I2C3SEL_SHIFT

#define RCC_CCIPR_I2C3SEL_SHIFT 16

Definition at line 656 of file l4/rcc.h.

◆ RCC_CCIPR_I2C4SEL_SHIFT

#define RCC_CCIPR_I2C4SEL_SHIFT 0

Definition at line 655 of file l4/rcc.h.

◆ RCC_CCIPR_I2CxSEL_APB

#define RCC_CCIPR_I2CxSEL_APB 0

Definition at line 651 of file l4/rcc.h.

◆ RCC_CCIPR_I2CxSEL_HSI16

#define RCC_CCIPR_I2CxSEL_HSI16 2

Definition at line 653 of file l4/rcc.h.

◆ RCC_CCIPR_I2CxSEL_MASK

#define RCC_CCIPR_I2CxSEL_MASK 0x3

Definition at line 654 of file l4/rcc.h.

◆ RCC_CCIPR_I2CxSEL_SYSCLK

#define RCC_CCIPR_I2CxSEL_SYSCLK 1

Definition at line 652 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_SHIFT

#define RCC_CCIPR_LPTIM1SEL_SHIFT 18

Definition at line 649 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIM2SEL_SHIFT

#define RCC_CCIPR_LPTIM2SEL_SHIFT 20

Definition at line 648 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIMxSEL_APB

#define RCC_CCIPR_LPTIMxSEL_APB 0

Definition at line 643 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIMxSEL_HSI16

#define RCC_CCIPR_LPTIMxSEL_HSI16 2

Definition at line 645 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIMxSEL_LSE

#define RCC_CCIPR_LPTIMxSEL_LSE 3

Definition at line 646 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIMxSEL_LSI

#define RCC_CCIPR_LPTIMxSEL_LSI 1

Definition at line 644 of file l4/rcc.h.

◆ RCC_CCIPR_LPTIMxSEL_MASK

#define RCC_CCIPR_LPTIMxSEL_MASK 0x3

Definition at line 647 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_APB

#define RCC_CCIPR_LPUART1SEL_APB 0

Definition at line 660 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_HSI16

#define RCC_CCIPR_LPUART1SEL_HSI16 2

Definition at line 662 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_LSE

#define RCC_CCIPR_LPUART1SEL_LSE 3

Definition at line 663 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_MASK

#define RCC_CCIPR_LPUART1SEL_MASK 0x3

Definition at line 664 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_SHIFT

#define RCC_CCIPR_LPUART1SEL_SHIFT 10

Definition at line 665 of file l4/rcc.h.

◆ RCC_CCIPR_LPUART1SEL_SYS

#define RCC_CCIPR_LPUART1SEL_SYS 1

Definition at line 661 of file l4/rcc.h.

◆ RCC_CCIPR_SAI1SEL_SHIFT

#define RCC_CCIPR_SAI1SEL_SHIFT 22

Definition at line 641 of file l4/rcc.h.

◆ RCC_CCIPR_SAI2SEL_SHIFT

#define RCC_CCIPR_SAI2SEL_SHIFT 24

Definition at line 640 of file l4/rcc.h.

◆ RCC_CCIPR_SAIxSEL_EXT

#define RCC_CCIPR_SAIxSEL_EXT 3

Definition at line 638 of file l4/rcc.h.

◆ RCC_CCIPR_SAIxSEL_MASK

#define RCC_CCIPR_SAIxSEL_MASK 0x3

Definition at line 639 of file l4/rcc.h.

◆ RCC_CCIPR_SAIxSEL_PLL

#define RCC_CCIPR_SAIxSEL_PLL 2

Definition at line 637 of file l4/rcc.h.

◆ RCC_CCIPR_SAIxSEL_PLLSAI1P

#define RCC_CCIPR_SAIxSEL_PLLSAI1P 0

Definition at line 635 of file l4/rcc.h.

◆ RCC_CCIPR_SAIxSEL_PLLSAI2P

#define RCC_CCIPR_SAIxSEL_PLLSAI2P 1

Definition at line 636 of file l4/rcc.h.

◆ RCC_CCIPR_SWPMI1SEL

#define RCC_CCIPR_SWPMI1SEL (1 << 30)

Definition at line 619 of file l4/rcc.h.

◆ RCC_CCIPR_UART4SEL_SHIFT

#define RCC_CCIPR_UART4SEL_SHIFT 6

Definition at line 678 of file l4/rcc.h.

◆ RCC_CCIPR_UART5SEL_SHIFT

#define RCC_CCIPR_UART5SEL_SHIFT 8

Definition at line 677 of file l4/rcc.h.

◆ RCC_CCIPR_UARTxSEL_APB

#define RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APB

Definition at line 672 of file l4/rcc.h.

◆ RCC_CCIPR_UARTxSEL_HSI16

#define RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16

Definition at line 674 of file l4/rcc.h.

◆ RCC_CCIPR_UARTxSEL_LSE

#define RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE

Definition at line 675 of file l4/rcc.h.

◆ RCC_CCIPR_UARTxSEL_MASK

#define RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASK

Definition at line 676 of file l4/rcc.h.

◆ RCC_CCIPR_UARTxSEL_SYSCLK

#define RCC_CCIPR_UARTxSEL_SYSCLK RCC_CCIPR_USARTxSEL_SYSCLK

Definition at line 673 of file l4/rcc.h.

◆ RCC_CCIPR_USART1SEL_SHIFT

#define RCC_CCIPR_USART1SEL_SHIFT 0

Definition at line 681 of file l4/rcc.h.

◆ RCC_CCIPR_USART2SEL_SHIFT

#define RCC_CCIPR_USART2SEL_SHIFT 2

Definition at line 680 of file l4/rcc.h.

◆ RCC_CCIPR_USART3SEL_SHIFT

#define RCC_CCIPR_USART3SEL_SHIFT 4

Definition at line 679 of file l4/rcc.h.

◆ RCC_CCIPR_USARTxSEL_APB

#define RCC_CCIPR_USARTxSEL_APB 0

Definition at line 667 of file l4/rcc.h.

◆ RCC_CCIPR_USARTxSEL_HSI16

#define RCC_CCIPR_USARTxSEL_HSI16 2

Definition at line 669 of file l4/rcc.h.

◆ RCC_CCIPR_USARTxSEL_LSE

#define RCC_CCIPR_USARTxSEL_LSE 3

Definition at line 670 of file l4/rcc.h.

◆ RCC_CCIPR_USARTxSEL_MASK

#define RCC_CCIPR_USARTxSEL_MASK 0x3

Definition at line 671 of file l4/rcc.h.

◆ RCC_CCIPR_USARTxSEL_SYSCLK

#define RCC_CCIPR_USARTxSEL_SYSCLK 1

Definition at line 668 of file l4/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK 0xf

Definition at line 215 of file l4/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT 4

Definition at line 214 of file l4/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE 0x4

Definition at line 187 of file l4/rcc.h.

◆ RCC_CFGR_MCO_HSI16

#define RCC_CFGR_MCO_HSI16 0x3

Definition at line 186 of file l4/rcc.h.

◆ RCC_CFGR_MCO_HSI48

#define RCC_CFGR_MCO_HSI48 0x8

Definition at line 191 of file l4/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE 0x7

Definition at line 190 of file l4/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI 0x6

Definition at line 189 of file l4/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK 0xf

Definition at line 193 of file l4/rcc.h.

◆ RCC_CFGR_MCO_MSI

#define RCC_CFGR_MCO_MSI 0x2

Definition at line 185 of file l4/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK 0x0

Definition at line 183 of file l4/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL 0x5

Definition at line 188 of file l4/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT 24

Definition at line 192 of file l4/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK 0x1

Definition at line 184 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 0

Definition at line 174 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 4

Definition at line 178 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 1

Definition at line 175 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 2

Definition at line 176 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 3

Definition at line 177 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_MASK

#define RCC_CFGR_MCOPRE_MASK 0x7

Definition at line 180 of file l4/rcc.h.

◆ RCC_CFGR_MCOPRE_SHIFT

#define RCC_CFGR_MCOPRE_SHIFT 28

Definition at line 179 of file l4/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK 0x7

Definition at line 200 of file l4/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 199 of file l4/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK 0x7

Definition at line 202 of file l4/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 201 of file l4/rcc.h.

◆ RCC_CFGR_STOPWUCK_HSI16

#define RCC_CFGR_STOPWUCK_HSI16 (1 << 15)

Definition at line 197 of file l4/rcc.h.

◆ RCC_CFGR_STOPWUCK_MSI

#define RCC_CFGR_STOPWUCK_MSI (0 << 15)

Definition at line 196 of file l4/rcc.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE 0x2

Definition at line 240 of file l4/rcc.h.

◆ RCC_CFGR_SW_HSI16

#define RCC_CFGR_SW_HSI16 0x1

Definition at line 239 of file l4/rcc.h.

◆ RCC_CFGR_SW_MASK

#define RCC_CFGR_SW_MASK 0x3

Definition at line 242 of file l4/rcc.h.

◆ RCC_CFGR_SW_MSI

#define RCC_CFGR_SW_MSI 0x0

Definition at line 238 of file l4/rcc.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL 0x3

Definition at line 241 of file l4/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT 0

Definition at line 243 of file l4/rcc.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE 0x2

Definition at line 232 of file l4/rcc.h.

◆ RCC_CFGR_SWS_HSI16

#define RCC_CFGR_SWS_HSI16 0x1

Definition at line 231 of file l4/rcc.h.

◆ RCC_CFGR_SWS_MASK

#define RCC_CFGR_SWS_MASK 0x3

Definition at line 234 of file l4/rcc.h.

◆ RCC_CFGR_SWS_MSI

#define RCC_CFGR_SWS_MSI 0x0

Definition at line 230 of file l4/rcc.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL 0x3

Definition at line 233 of file l4/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT 2

Definition at line 235 of file l4/rcc.h.

◆ RCC_CICR_CSSC

#define RCC_CICR_CSSC (1 << 8)

Definition at line 329 of file l4/rcc.h.

◆ RCC_CICR_HSERDYC

#define RCC_CICR_HSERDYC (1 << 4)

Definition at line 333 of file l4/rcc.h.

◆ RCC_CICR_HSI48RDYC

#define RCC_CICR_HSI48RDYC (1 << 10)

Definition at line 327 of file l4/rcc.h.

◆ RCC_CICR_HSIRDYC

#define RCC_CICR_HSIRDYC (1 << 3)

Definition at line 334 of file l4/rcc.h.

◆ RCC_CICR_LSECSSC

#define RCC_CICR_LSECSSC (1 << 9)

Definition at line 328 of file l4/rcc.h.

◆ RCC_CICR_LSERDYC

#define RCC_CICR_LSERDYC (1 << 1)

Definition at line 336 of file l4/rcc.h.

◆ RCC_CICR_LSIRDYC

#define RCC_CICR_LSIRDYC (1 << 0)

Definition at line 337 of file l4/rcc.h.

◆ RCC_CICR_MSIRDYC

#define RCC_CICR_MSIRDYC (1 << 2)

Definition at line 335 of file l4/rcc.h.

◆ RCC_CICR_PLLRDYC

#define RCC_CICR_PLLRDYC (1 << 5)

Definition at line 332 of file l4/rcc.h.

◆ RCC_CICR_PLLSAI1RDYC

#define RCC_CICR_PLLSAI1RDYC (1 << 6)

Definition at line 331 of file l4/rcc.h.

◆ RCC_CICR_PLLSAI2RDYC

#define RCC_CICR_PLLSAI2RDYC (1 << 7)

Definition at line 330 of file l4/rcc.h.

◆ RCC_CIER_HSERDYIE

#define RCC_CIER_HSERDYIE (1 << 4)

Definition at line 305 of file l4/rcc.h.

◆ RCC_CIER_HSI48RDYIE

#define RCC_CIER_HSI48RDYIE (1 << 10)

Definition at line 299 of file l4/rcc.h.

◆ RCC_CIER_HSIRDYIE

#define RCC_CIER_HSIRDYIE (1 << 3)

Definition at line 306 of file l4/rcc.h.

◆ RCC_CIER_LSE_CSSIE

#define RCC_CIER_LSE_CSSIE (1 << 9)

Definition at line 300 of file l4/rcc.h.

◆ RCC_CIER_LSERDYIE

#define RCC_CIER_LSERDYIE (1 << 1)

Definition at line 308 of file l4/rcc.h.

◆ RCC_CIER_LSIRDYIE

#define RCC_CIER_LSIRDYIE (1 << 0)

Definition at line 309 of file l4/rcc.h.

◆ RCC_CIER_MSIRDYIE

#define RCC_CIER_MSIRDYIE (1 << 2)

Definition at line 307 of file l4/rcc.h.

◆ RCC_CIER_PLLRDYIE

#define RCC_CIER_PLLRDYIE (1 << 5)

Definition at line 304 of file l4/rcc.h.

◆ RCC_CIER_PLLSAI1RDYIE

#define RCC_CIER_PLLSAI1RDYIE (1 << 6)

Definition at line 303 of file l4/rcc.h.

◆ RCC_CIER_PLLSAI2RDYIE

#define RCC_CIER_PLLSAI2RDYIE (1 << 7)

Definition at line 302 of file l4/rcc.h.

◆ RCC_CIFR_CSSF

#define RCC_CIFR_CSSF (1 << 8)

Definition at line 315 of file l4/rcc.h.

◆ RCC_CIFR_HSERDYF

#define RCC_CIFR_HSERDYF (1 << 4)

Definition at line 319 of file l4/rcc.h.

◆ RCC_CIFR_HSI48RDYF

#define RCC_CIFR_HSI48RDYF (1 << 10)

Definition at line 313 of file l4/rcc.h.

◆ RCC_CIFR_HSIRDYF

#define RCC_CIFR_HSIRDYF (1 << 3)

Definition at line 320 of file l4/rcc.h.

◆ RCC_CIFR_LSECSSF

#define RCC_CIFR_LSECSSF (1 << 9)

Definition at line 314 of file l4/rcc.h.

◆ RCC_CIFR_LSERDYF

#define RCC_CIFR_LSERDYF (1 << 1)

Definition at line 322 of file l4/rcc.h.

◆ RCC_CIFR_LSIRDYF

#define RCC_CIFR_LSIRDYF (1 << 0)

Definition at line 323 of file l4/rcc.h.

◆ RCC_CIFR_MSIRDYF

#define RCC_CIFR_MSIRDYF (1 << 2)

Definition at line 321 of file l4/rcc.h.

◆ RCC_CIFR_PLLRDYF

#define RCC_CIFR_PLLRDYF (1 << 5)

Definition at line 318 of file l4/rcc.h.

◆ RCC_CIFR_PLLSAI1RDYF

#define RCC_CIFR_PLLSAI1RDYF (1 << 6)

Definition at line 317 of file l4/rcc.h.

◆ RCC_CIFR_PLLSAI2RDYF

#define RCC_CIFR_PLLSAI2RDYF (1 << 7)

Definition at line 316 of file l4/rcc.h.

◆ RCC_CR_MSION

#define RCC_CR_MSION (1 << 0)

Definition at line 152 of file l4/rcc.h.

◆ RCC_CR_MSIPLLEN

#define RCC_CR_MSIPLLEN (1 << 2)

Definition at line 150 of file l4/rcc.h.

◆ RCC_CR_MSIRDY

#define RCC_CR_MSIRDY (1 << 1)

Definition at line 151 of file l4/rcc.h.

◆ RCC_CR_MSIRGSEL

#define RCC_CR_MSIRGSEL (1 << 3)

Definition at line 149 of file l4/rcc.h.

◆ RCC_CRRCR_HSI48ON

#define RCC_CRRCR_HSI48ON (1 << 0)

Definition at line 156 of file l4/rcc.h.

◆ RCC_CRRCR_HSI48RDY

#define RCC_CRRCR_HSI48RDY (1 << 1)

Definition at line 157 of file l4/rcc.h.

◆ RCC_CSR_BORRSTF

#define RCC_CSR_BORRSTF (1 << 27)

Definition at line 718 of file l4/rcc.h.

◆ RCC_CSR_FWRSTF

#define RCC_CSR_FWRSTF (1 << 24)

Definition at line 721 of file l4/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF (1 << 29)

Definition at line 716 of file l4/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF (1 << 31)

Definition at line 714 of file l4/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION (1 << 0)

Definition at line 741 of file l4/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY (1 << 1)

Definition at line 740 of file l4/rcc.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF (1 << 25)

Definition at line 720 of file l4/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF (1 << 26)

Definition at line 719 of file l4/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS

Value:

                (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
                RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF |\
                RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)

Definition at line 723 of file l4/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF (1 << 23)

Definition at line 722 of file l4/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF (1 << 28)

Definition at line 717 of file l4/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF (1 << 30)

Definition at line 715 of file l4/rcc.h.

◆ RCC_ICSCR_HSICAL_MASK

#define RCC_ICSCR_HSICAL_MASK 0xff

Definition at line 164 of file l4/rcc.h.

◆ RCC_ICSCR_HSICAL_SHIFT

#define RCC_ICSCR_HSICAL_SHIFT 16

Definition at line 163 of file l4/rcc.h.

◆ RCC_ICSCR_HSITRIM_MASK

#define RCC_ICSCR_HSITRIM_MASK 0x1f

Definition at line 162 of file l4/rcc.h.

◆ RCC_ICSCR_HSITRIM_SHIFT

#define RCC_ICSCR_HSITRIM_SHIFT 24

Definition at line 161 of file l4/rcc.h.

◆ RCC_ICSCR_MSICAL_MASK

#define RCC_ICSCR_MSICAL_MASK 0xff

Definition at line 169 of file l4/rcc.h.

◆ RCC_ICSCR_MSICAL_SHIFT

#define RCC_ICSCR_MSICAL_SHIFT 0

Definition at line 168 of file l4/rcc.h.

◆ RCC_ICSCR_MSITRIM_MASK

#define RCC_ICSCR_MSITRIM_MASK 0xff

Definition at line 167 of file l4/rcc.h.

◆ RCC_ICSCR_MSITRIM_SHIFT

#define RCC_ICSCR_MSITRIM_SHIFT 8

Definition at line 166 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP (1 << 17)

Definition at line 263 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLP_DIV17

#define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP

Definition at line 265 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLP_DIV7

#define RCC_PLLCFGR_PLLP_DIV7 0

Definition at line 264 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_DIV2

#define RCC_PLLCFGR_PLLQ_DIV2 0

Definition at line 256 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_DIV4

#define RCC_PLLCFGR_PLLQ_DIV4 1

Definition at line 257 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_DIV6

#define RCC_PLLCFGR_PLLQ_DIV6 2

Definition at line 258 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_DIV8

#define RCC_PLLCFGR_PLLQ_DIV8 3

Definition at line 259 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_MASK

#define RCC_PLLCFGR_PLLQ_MASK 0x3

Definition at line 255 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQ_SHIFT

#define RCC_PLLCFGR_PLLQ_SHIFT 21

Definition at line 254 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLQEN

#define RCC_PLLCFGR_PLLQEN (1 << 20)

Definition at line 260 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_DIV2

#define RCC_PLLCFGR_PLLR_DIV2 0

Definition at line 248 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_DIV4

#define RCC_PLLCFGR_PLLR_DIV4 1

Definition at line 249 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_DIV6

#define RCC_PLLCFGR_PLLR_DIV6 2

Definition at line 250 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_DIV8

#define RCC_PLLCFGR_PLLR_DIV8 3

Definition at line 251 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_MASK

#define RCC_PLLCFGR_PLLR_MASK 0x3

Definition at line 247 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLR_SHIFT

#define RCC_PLLCFGR_PLLR_SHIFT 25

Definition at line 246 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLREN

#define RCC_PLLCFGR_PLLREN (1<<24)

Definition at line 252 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSE 3

Definition at line 290 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_HSI16

#define RCC_PLLCFGR_PLLSRC_HSI16 2

Definition at line 289 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_MASK

#define RCC_PLLCFGR_PLLSRC_MASK 0x3

Definition at line 286 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_MSI

#define RCC_PLLCFGR_PLLSRC_MSI 1

Definition at line 288 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_NONE

#define RCC_PLLCFGR_PLLSRC_NONE 0

Definition at line 287 of file l4/rcc.h.

◆ RCC_PLLCFGR_PLLSRC_SHIFT

#define RCC_PLLCFGR_PLLSRC_SHIFT 0

Definition at line 285 of file l4/rcc.h.

◆ RCC_PLLPEN

#define RCC_PLLPEN (1 << 16)

Definition at line 266 of file l4/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_config_entry

enum rcc_clock_config_entry

Enumerator
RCC_CLOCK_VRANGE1_80MHZ
RCC_CLOCK_CONFIG_END

Definition at line 760 of file l4/rcc.h.

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_PLL
RCC_HSE
RCC_HSI16
RCC_MSI
RCC_LSE
RCC_LSI
RCC_HSI48

Definition at line 777 of file l4/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_TSC
RCC_CRC
RCC_FLASH
RCC_DMA2
RCC_DMA1
RCC_RNG
RCC_AES
RCC_ADC
RCC_ADC1
RCC_OTGFS
RCC_GPIOH
RCC_GPIOG
RCC_GPIOF
RCC_GPIOE
RCC_GPIOD
RCC_GPIOC
RCC_GPIOB
RCC_GPIOA
RCC_QSPI
RCC_FMC
RCC_LPTIM1
RCC_OPAMP
RCC_DAC1
RCC_PWR
RCC_USB
RCC_CAN2
RCC_CAN1
RCC_CRS
RCC_I2C3
RCC_I2C2
RCC_I2C1
RCC_UART5
RCC_UART4
RCC_USART3
RCC_USART2
RCC_SPI3
RCC_SPI2
RCC_LCD
RCC_TIM7
RCC_TIM6
RCC_TIM5
RCC_TIM4
RCC_TIM3
RCC_TIM2
RCC_LPTIM2
RCC_SWPMI1
RCC_LPUART1
RCC_DFSDM
RCC_SAI2
RCC_SAI1
RCC_TIM17
RCC_TIM16
RCC_TIM15
RCC_USART1
RCC_TIM8
RCC_SPI1
RCC_TIM1
RCC_SDMMC1
RCC_FW
RCC_SYSCFG
SCC_TSC
SCC_CRC
SCC_SRAM1
SCC_FLASH
SCC_DMA2
SCC_DMA1
SCC_RNG
SCC_AES
SCC_ADC
SCC_ADC1
SCC_OTGFS
SCC_SRAM2
SCC_GPIOH
SCC_GPIOG
SCC_GPIOF
SCC_GPIOE
SCC_GPIOD
SCC_GPIOC
SCC_GPIOB
SCC_GPIOA
SCC_QSPI
SCC_FMC
SCC_LPTIM1
SCC_OPAMP
SCC_DAC1
SCC_PWR
SCC_CAN2
SCC_CAN1
SCC_I2C3
SCC_I2C2
SCC_I2C1
SCC_UART5
SCC_UART4
SCC_USART3
SCC_USART2
SCC_SPI3
SCC_SPI2
SCC_WWDG
SCC_LCD
SCC_TIM7
SCC_TIM6
SCC_TIM5
SCC_TIM4
SCC_TIM3
SCC_TIM2
SCC_LPTIM2
SCC_SWPMI1
SCC_LPUART1
SCC_DFSDM
SCC_SAI2
SCC_SAI1
SCC_TIM17
SCC_TIM16
SCC_TIM15
SCC_USART1
SCC_TIM8
SCC_SPI1
SCC_TIM1
SCC_SDMMC1
SCC_SYSCFG

Definition at line 784 of file l4/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_TSC
RST_CRC
RST_FLASH
RST_DMA2
RST_DMA1
RST_RNG
RST_AES
RST_ADC
RST_ADC1
RST_OTGFS
RST_GPIOH
RST_GPIOG
RST_GPIOF
RST_GPIOE
RST_GPIOD
RST_GPIOC
RST_GPIOB
RST_GPIOA
RST_QSPI
RST_FMC
RST_LPTIM1
RST_OPAMP
RST_DAC1
RST_PWR
RST_USB
RST_CAN2
RST_CAN1
RST_CRS
RST_I2C3
RST_I2C2
RST_I2C1
RST_UART5
RST_UART4
RST_USART3
RST_USART2
RST_SPI3
RST_SPI2
RST_LCD
RST_TIM7
RST_TIM6
RST_TIM5
RST_TIM4
RST_TIM3
RST_TIM2
RST_LPTIM2
RST_SWPMI1
RST_LPUART1
RST_DFSDM
RST_SAI2
RST_SAI1
RST_TIM17
RST_TIM16
RST_TIM15
RST_USART1
RST_TIM8
RST_SPI1
RST_TIM1
RST_SDMMC1
RST_SYSCFG

Definition at line 929 of file l4/rcc.h.

Function Documentation

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Setup clocks to run from PLL.

The arguments provide the pll source, multipliers, dividers, all that's needed to establish a system clock.

Parameters

clock clock information structure.

Definition at line 374 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, FLASH_ACR_DCEN, FLASH_ACR_ICEN, rcc_clock_scale::flash_config, flash_dcache_disable(), flash_dcache_enable(), flash_icache_disable(), flash_icache_enable(), flash_set_ws(), rcc_clock_scale::hpre, rcc_clock_scale::pll_source, rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI16, rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PLLCFGR_PLLSRC_HSE, RCC_PLLCFGR_PLLSRC_HSI16, RCC_PWR, rcc_set_hpre(), rcc_set_main_pll(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), rcc_wait_for_sysclk_status(), and rcc_clock_scale::voltage_scale.

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 299 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 294 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 179 of file rcc.c.

References RCC_CICR, and RCC_CICR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 184 of file rcc.c.

References RCC_CIFR, and RCC_CIFR_CSSF.

◆ rcc_disable_rtc_clock()

void rcc_disable_rtc_clock ( void )

Disable the RTC clock.

Definition at line 508 of file rcc.c.

References RCC_BDCR.

◆ rcc_enable_rtc_clock()

void rcc_enable_rtc_clock ( void )

Enable the RTC clock.

Definition at line 502 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 612 of file rcc.c.

References I2C1_BASE, I2C2_BASE, I2C3_BASE, rcc_apb1_frequency, RCC_CCIPR, RCC_CCIPR2, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C2SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, RCC_CCIPR_I2C4SEL_SHIFT, and rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 629 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 580 of file rcc.c.

References cm3_assert_not_reached, LPTIM1_BASE, LPTIM2_BASE, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPTIM2SEL_SHIFT, RCC_CCIPR_LPTIMxSEL_APB, RCC_CCIPR_LPTIMxSEL_HSI16, RCC_CCIPR_LPTIMxSEL_LSE, RCC_CCIPR_LPTIMxSEL_LSI, RCC_CCIPR_LPTIMxSEL_MASK, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, RCC_CFGR_PPRE_NODIV, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 558 of file rcc.c.

References LPUART1_BASE, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_UART4SEL_SHIFT, RCC_CCIPR_UART5SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_uart_i2c_clksel_freq_hz(), UART4_BASE, USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 189 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 267 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 240 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_MSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 69 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI48RDYC, RCC_CICR_HSIRDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_MSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 123 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 96 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_HSIRDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_MSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 150 of file rcc.c.

References RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_HSIRDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_MSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), st_usbfs_v2_usbd_init(), and stm32f107_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset().

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◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_pll_output_enable()

void rcc_pll_output_enable ( uint32_t pllout )

Enable PLL Output.

- P (RCC_PLLCFGR_PLLPEN)
- Q (RCC_PLLCFGR_PLLQEN)
- R (RCC_PLLCFGR_PLLREN)

Parameters

pllout One or more of the definitions above

Definition at line 479 of file rcc.c.

References RCC_PLLCFGR.

◆ rcc_set_clock48_source()

void rcc_set_clock48_source ( uint32_t clksel )

Set clock source for 48MHz clock.

The 48 MHz clock is derived from one of the four following sources:

main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
MSI clock (RCC_CCIPR_CLK48SEL_MSI)
HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)

Parameters

clksel One of the definitions above

Definition at line 494 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_CLK48SEL_MASK, and RCC_CCIPR_CLK48SEL_SHIFT.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

Definition at line 340 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll()

void rcc_set_main_pll	(	uint32_t	source,
		uint32_t	pllm,
		uint32_t	plln,
		uint32_t	pllp,
		uint32_t	pllq,
		uint32_t	pllr
	)

Definition at line 349 of file rcc.c.

References rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, RCC_PLLCFGR, RCC_PLLCFGR_PLLM, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_SHIFT, RCC_PLLCFGR_PLLREN, and RCC_PLLCFGR_PLLSRC_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_mco()

void rcc_set_mco ( uint32_t mcosrc )

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in] mcosrc the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_msi_range()

void rcc_set_msi_range ( uint32_t msi_range )

Set the msi run time range.

Can only be called when MSI is either OFF, or when MSI is on and ready. (RCC_CR_MSIRDY bit).

See also: rcc_set_msi_range_standby

Parameters

msi_range range number MSI Range

Definition at line 448 of file rcc.c.

References RCC_CR, RCC_CR_MSIRANGE_MASK, RCC_CR_MSIRANGE_SHIFT, and RCC_CR_MSIRGSEL.

◆ rcc_set_msi_range_standby()

void rcc_set_msi_range_standby ( uint32_t msi_range )

Set the msi range after reset/standby.

Until MSIRGSEl bit is set, this defines the MSI range. Note that not all MSI range values are allowed here!

See also: rcc_set_msi_range

Parameters

msi_range range number valid for post standby MSI Range after standby values

Definition at line 463 of file rcc.c.

References RCC_CSR, RCC_CSR_MSIRANGE_MASK, and RCC_CSR_MSIRANGE_SHIFT.

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t pllsrc )

Definition at line 313 of file rcc.c.

References RCC_PLLCFGR, RCC_PLLCFGR_PLLSRC_MASK, and RCC_PLLCFGR_PLLSRC_SHIFT.

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t ppre1 )

Definition at line 331 of file rcc.c.

References rcc_clock_scale::ppre1, RCC_CFGR, RCC_CFGR_PPRE1_MASK, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t ppre2 )

Definition at line 322 of file rcc.c.

References rcc_clock_scale::ppre2, RCC_CFGR, RCC_CFGR_PPRE2_MASK, and RCC_CFGR_PPRE2_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_rtc_clock_source()

void rcc_set_rtc_clock_source ( enum rcc_osc clk )

Set the source for the RTC clock.

Parameters

[in] clk rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.

Definition at line 516 of file rcc.c.

References RCC_BDCR, RCC_BDCR_RTCSEL_HSEDIV32, RCC_BDCR_RTCSEL_LSE, RCC_BDCR_RTCSEL_LSI, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_SHIFT, RCC_HSE, RCC_LSE, and RCC_LSI.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t clk )

Definition at line 304 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SW_MASK, and RCC_CFGR_SW_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void )

Definition at line 360 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_MASK, and RCC_CFGR_SWS_SHIFT.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc osc )

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Definition at line 210 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_pll().

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◆ rcc_wait_for_sysclk_status()

void rcc_wait_for_sysclk_status ( enum rcc_osc osc )

Definition at line 215 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI16, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_MSI, RCC_CFGR_SWS_PLL, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI16, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency

extern

Definition at line 45 of file rcc.c.

Referenced by rcc_clock_setup_pll(), and rcc_uart_i2c_clksel_freq_hz().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency

extern

Definition at line 46 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency

extern

Definition at line 47 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_hsi16_configs

const struct rcc_clock_scale rcc_hsi16_configs[RCC_CLOCK_CONFIG_END]

extern

Definition at line 49 of file rcc.c.

Data Structures

Modules

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _REG_BIT

◆ RCC_AHB1SMENR_CRCSMEN

◆ RCC_AHB1SMENR_DMA1SMEN

◆ RCC_AHB1SMENR_DMA2SMEN

◆ RCC_AHB1SMENR_FLASHSMEN

◆ RCC_AHB1SMENR_SRAM1SMEN

◆ RCC_AHB1SMENR_TSCSMEN

◆ RCC_AHB2SMENR_ADCSMEN

◆ RCC_AHB2SMENR_AESSMEN

◆ RCC_AHB2SMENR_GPIOASMEN

◆ RCC_AHB2SMENR_GPIOBSMEN

◆ RCC_AHB2SMENR_GPIOCSMEN

◆ RCC_AHB2SMENR_GPIODSMEN

◆ RCC_AHB2SMENR_GPIOESMEN

◆ RCC_AHB2SMENR_GPIOFSMEN

◆ RCC_AHB2SMENR_GPIOGSMEN

◆ RCC_AHB2SMENR_GPIOHSMEN

◆ RCC_AHB2SMENR_OTGFSSMEN

◆ RCC_AHB2SMENR_RNGSMEN

◆ RCC_AHB2SMENR_SRAM2SMEN

◆ RCC_AHB3SMENR_FMCSMEN

◆ RCC_AHB3SMENR_QSPISMEN

◆ RCC_APB1SMENR1_CAN1SMEN

◆ RCC_APB1SMENR1_CAN2SMEN

◆ RCC_APB1SMENR1_DAC1SMEN

◆ RCC_APB1SMENR1_I2C1SMEN

◆ RCC_APB1SMENR1_I2C2SMEN

◆ RCC_APB1SMENR1_I2C3SMEN

◆ RCC_APB1SMENR1_LCDSMEN

◆ RCC_APB1SMENR1_LPTIM1SMEN

◆ RCC_APB1SMENR1_OPAMPSMEN

◆ RCC_APB1SMENR1_PWRSMEN

◆ RCC_APB1SMENR1_SPI2SMEN

◆ RCC_APB1SMENR1_SPI3SMEN

◆ RCC_APB1SMENR1_TIM2SMEN

◆ RCC_APB1SMENR1_TIM3SMEN

◆ RCC_APB1SMENR1_TIM4SMEN

◆ RCC_APB1SMENR1_TIM5SMEN

◆ RCC_APB1SMENR1_TIM6SMEN

◆ RCC_APB1SMENR1_TIM7SMEN

◆ RCC_APB1SMENR1_UART4SMEN

◆ RCC_APB1SMENR1_UART5SMEN

◆ RCC_APB1SMENR1_USART2SMEN

◆ RCC_APB1SMENR1_USART3SMEN

◆ RCC_APB1SMENR1_WWDGSMEN

◆ RCC_APB1SMENR2_LPTIM2SMEN

◆ RCC_APB1SMENR2_LPUART1SMEN

◆ RCC_APB1SMENR2_SWPMI1SMEN

◆ RCC_APB2SMENR_DFSDMSMEN

◆ RCC_APB2SMENR_SAI1SMEN

◆ RCC_APB2SMENR_SAI2SMEN

◆ RCC_APB2SMENR_SDMMC1SMEN

◆ RCC_APB2SMENR_SPI1SMEN

◆ RCC_APB2SMENR_SYSCFGSMEN

◆ RCC_APB2SMENR_TIM15SMEN

◆ RCC_APB2SMENR_TIM16SMEN

◆ RCC_APB2SMENR_TIM17SMEN

◆ RCC_APB2SMENR_TIM1SMEN

◆ RCC_APB2SMENR_TIM8SMEN

◆ RCC_APB2SMENR_USART1SMEN

◆ RCC_BDCR_BDRST

◆ RCC_BDCR_LSCOEN

◆ RCC_BDCR_LSCOSEL

◆ RCC_BDCR_LSEBYP

◆ RCC_BDCR_LSECSSD

◆ RCC_BDCR_LSECSSON

◆ RCC_BDCR_LSEDRV_HIGH

◆ RCC_BDCR_LSEDRV_LOW

◆ RCC_BDCR_LSEDRV_MASK

◆ RCC_BDCR_LSEDRV_MEDHIGH

◆ RCC_BDCR_LSEDRV_MEDLOW

◆ RCC_BDCR_LSEDRV_SHIFT