libopencm3 STM32L4xx Reset and Clock Control More...

Collaboration diagram for RCC peripheral API:

Macros
#define	_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))

#define	_RCC_BIT(i) (1 << ((i) & 0x1f))

Functions
void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_main_pll (uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)

uint32_t	rcc_system_clock_source (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_set_msi_range (uint32_t msi_range)
	Set the msi run time range. More...

void	rcc_set_msi_range_standby (uint32_t msi_range)
	Set the msi range after reset/standby. More...

void	rcc_pll_output_enable (uint32_t pllout)
	Enable PLL Output. More...

void	rcc_set_clock48_source (uint32_t clksel)
	Set clock source for 48MHz clock. More...

void	rcc_enable_rtc_clock (void)
	Enable the RTC clock. More...

void	rcc_disable_rtc_clock (void)
	Disable the RTC clock. More...

void	rcc_set_rtc_clock_source (enum rcc_osc clk)
	Set the source for the RTC clock. More...

static uint32_t	rcc_uart_i2c_clksel_freq_hz (uint32_t apb_clk, uint8_t shift, uint32_t clock_reg)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

Variables
uint32_t	rcc_ahb_frequency = 4000000

uint32_t	rcc_apb1_frequency = 4000000

uint32_t	rcc_apb2_frequency = 4000000

const struct rcc_clock_scale	rcc_hsi16_configs [RCC_CLOCK_CONFIG_END]

Detailed Description

libopencm3 STM32L4xx Reset and Clock Control

Reset and Clock Control API.

Author: © 2016 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Date: 12 Feb 2016

This library supports the Reset and Clock Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ _RCC_BIT

#define _RCC_BIT ( i ) (1 << ((i) & 0x1f))

Definition at line 117 of file rcc_common_all.c.

◆ _RCC_REG

#define _RCC_REG ( i ) MMIO32(RCC_BASE + ((i) >> 5))

Definition at line 116 of file rcc_common_all.c.

Function Documentation

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Setup clocks to run from PLL.

The arguments provide the pll source, multipliers, dividers, all that's needed to establish a system clock.

Parameters

clock clock information structure.

Definition at line 374 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, FLASH_ACR_DCEN, FLASH_ACR_ICEN, rcc_clock_scale::flash_config, flash_dcache_disable(), flash_dcache_enable(), flash_icache_disable(), flash_icache_enable(), flash_set_ws(), rcc_clock_scale::hpre, rcc_clock_scale::pll_source, rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI16, rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PLLCFGR_PLLSRC_HSE, RCC_PLLCFGR_PLLSRC_HSI16, RCC_PWR, rcc_set_hpre(), rcc_set_main_pll(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), rcc_wait_for_sysclk_status(), and rcc_clock_scale::voltage_scale.

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 299 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 294 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 179 of file rcc.c.

References RCC_CICR, and RCC_CICR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 184 of file rcc.c.

References RCC_CIFR, and RCC_CIFR_CSSF.

◆ rcc_disable_rtc_clock()

void rcc_disable_rtc_clock ( void )

Disable the RTC clock.

Definition at line 508 of file rcc.c.

References RCC_BDCR.

◆ rcc_enable_rtc_clock()

void rcc_enable_rtc_clock ( void )

Enable the RTC clock.

Definition at line 502 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 612 of file rcc.c.

References I2C1_BASE, I2C2_BASE, I2C3_BASE, rcc_apb1_frequency, RCC_CCIPR, RCC_CCIPR2, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C2SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, RCC_CCIPR_I2C4SEL_SHIFT, and rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 629 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 580 of file rcc.c.

References cm3_assert_not_reached, LPTIM1_BASE, LPTIM2_BASE, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPTIM2SEL_SHIFT, RCC_CCIPR_LPTIMxSEL_APB, RCC_CCIPR_LPTIMxSEL_HSI16, RCC_CCIPR_LPTIMxSEL_LSE, RCC_CCIPR_LPTIMxSEL_LSI, RCC_CCIPR_LPTIMxSEL_MASK, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, RCC_CFGR_PPRE_NODIV, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 558 of file rcc.c.

References LPUART1_BASE, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_UART4SEL_SHIFT, RCC_CCIPR_UART5SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_uart_i2c_clksel_freq_hz(), UART4_BASE, USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 189 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 267 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 240 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_MSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 69 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI48RDYC, RCC_CICR_HSIRDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_MSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 123 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 96 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_HSIRDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_MSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 150 of file rcc.c.

References RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_HSIRDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_MSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), st_usbfs_v2_usbd_init(), and stm32f107_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset().

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◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_pll_output_enable()

void rcc_pll_output_enable ( uint32_t pllout )

Enable PLL Output.

- P (RCC_PLLCFGR_PLLPEN)
- Q (RCC_PLLCFGR_PLLQEN)
- R (RCC_PLLCFGR_PLLREN)

Parameters

pllout One or more of the definitions above

Definition at line 479 of file rcc.c.

References RCC_PLLCFGR.

◆ rcc_set_clock48_source()

void rcc_set_clock48_source ( uint32_t clksel )

Set clock source for 48MHz clock.

The 48 MHz clock is derived from one of the four following sources:

main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
MSI clock (RCC_CCIPR_CLK48SEL_MSI)
HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)

Parameters

clksel One of the definitions above

Definition at line 494 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_CLK48SEL_MASK, and RCC_CCIPR_CLK48SEL_SHIFT.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

Definition at line 340 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll()

void rcc_set_main_pll	(	uint32_t	source,
		uint32_t	pllm,
		uint32_t	plln,
		uint32_t	pllp,
		uint32_t	pllq,
		uint32_t	pllr
	)

Definition at line 349 of file rcc.c.

References rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, RCC_PLLCFGR, RCC_PLLCFGR_PLLM, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_SHIFT, RCC_PLLCFGR_PLLREN, and RCC_PLLCFGR_PLLSRC_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_mco()

void rcc_set_mco ( uint32_t mcosrc )

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in] mcosrc the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_msi_range()

void rcc_set_msi_range ( uint32_t msi_range )

Set the msi run time range.

Can only be called when MSI is either OFF, or when MSI is on and ready. (RCC_CR_MSIRDY bit).

See also: rcc_set_msi_range_standby

Parameters

msi_range range number MSI Range

Definition at line 448 of file rcc.c.

References RCC_CR, RCC_CR_MSIRANGE_MASK, RCC_CR_MSIRANGE_SHIFT, and RCC_CR_MSIRGSEL.

◆ rcc_set_msi_range_standby()

void rcc_set_msi_range_standby ( uint32_t msi_range )

Set the msi range after reset/standby.

Until MSIRGSEl bit is set, this defines the MSI range. Note that not all MSI range values are allowed here!

See also: rcc_set_msi_range

Parameters

msi_range range number valid for post standby MSI Range after standby values

Definition at line 463 of file rcc.c.

References RCC_CSR, RCC_CSR_MSIRANGE_MASK, and RCC_CSR_MSIRANGE_SHIFT.

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t pllsrc )

Definition at line 313 of file rcc.c.

References RCC_PLLCFGR, RCC_PLLCFGR_PLLSRC_MASK, and RCC_PLLCFGR_PLLSRC_SHIFT.

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t ppre1 )

Definition at line 331 of file rcc.c.

References rcc_clock_scale::ppre1, RCC_CFGR, RCC_CFGR_PPRE1_MASK, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t ppre2 )

Definition at line 322 of file rcc.c.

References rcc_clock_scale::ppre2, RCC_CFGR, RCC_CFGR_PPRE2_MASK, and RCC_CFGR_PPRE2_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_rtc_clock_source()

void rcc_set_rtc_clock_source ( enum rcc_osc clk )

Set the source for the RTC clock.

Parameters

[in] clk rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.

Definition at line 516 of file rcc.c.

References RCC_BDCR, RCC_BDCR_RTCSEL_HSEDIV32, RCC_BDCR_RTCSEL_LSE, RCC_BDCR_RTCSEL_LSI, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_SHIFT, RCC_HSE, RCC_LSE, and RCC_LSI.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t clk )

Definition at line 304 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SW_MASK, and RCC_CFGR_SW_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void )

Definition at line 360 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_MASK, and RCC_CFGR_SWS_SHIFT.

◆ rcc_uart_i2c_clksel_freq_hz()

static uint32_t rcc_uart_i2c_clksel_freq_hz	(	uint32_t	apb_clk,
		uint8_t	shift,
		uint32_t	clock_reg
	)

static

Definition at line 538 of file rcc.c.

References cm3_assert_not_reached, rcc_clock_scale::hpre, rcc_ahb_frequency, RCC_CCIPR_USARTxSEL_APB, RCC_CCIPR_USARTxSEL_HSI16, RCC_CCIPR_USARTxSEL_LSE, RCC_CCIPR_USARTxSEL_MASK, RCC_CCIPR_USARTxSEL_SYSCLK, RCC_CFGR, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().

Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clk_freq().

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◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc osc )

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Definition at line 210 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_pll().

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◆ rcc_wait_for_sysclk_status()

void rcc_wait_for_sysclk_status ( enum rcc_osc osc )

Definition at line 215 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI16, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_MSI, RCC_CFGR_SWS_PLL, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI16, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency = 4000000

Definition at line 45 of file rcc.c.

Referenced by rcc_clock_setup_pll(), and rcc_uart_i2c_clksel_freq_hz().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency = 4000000

Definition at line 46 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency = 4000000

Definition at line 47 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_hsi16_configs

const struct rcc_clock_scale rcc_hsi16_configs[RCC_CLOCK_CONFIG_END]

Initial value:

= {
        { 
                .pllm = 4,
                .plln = 40,
                .pllp = RCC_PLLCFGR_PLLP_DIV7,
                .pllq = RCC_PLLCFGR_PLLQ_DIV6,
                .pllr = RCC_PLLCFGR_PLLR_DIV2,
                .pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
                .hpre = RCC_CFGR_HPRE_NODIV,
                .ppre1 = RCC_CFGR_PPRE_NODIV,
                .ppre2 = RCC_CFGR_PPRE_NODIV,
                .voltage_scale = PWR_SCALE1,
                .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
                FLASH_ACR_LATENCY_4WS,
                .ahb_frequency  = 80000000,
                .apb1_frequency = 80000000,
                .apb2_frequency = 80000000,
        },
}

Definition at line 49 of file rcc.c.

Macros

Functions

Variables

Detailed Description

Reset and Clock Control API.

Macro Definition Documentation

◆ _RCC_BIT

◆ _RCC_REG

Function Documentation

◆ rcc_clock_setup_pll()

◆ rcc_css_disable()

◆ rcc_css_enable()

◆ rcc_css_int_clear()

◆ rcc_css_int_flag()

◆ rcc_disable_rtc_clock()

◆ rcc_enable_rtc_clock()

◆ rcc_get_div_from_hpre()

◆ rcc_get_i2c_clk_freq()

◆ rcc_get_spi_clk_freq()

◆ rcc_get_timer_clk_freq()

◆ rcc_get_usart_clk_freq()

◆ rcc_is_osc_ready()

◆ rcc_osc_bypass_disable()

◆ rcc_osc_bypass_enable()

◆ rcc_osc_off()

◆ rcc_osc_on()

◆ rcc_osc_ready_int_clear()

◆ rcc_osc_ready_int_disable()

◆ rcc_osc_ready_int_enable()

◆ rcc_osc_ready_int_flag()

◆ rcc_periph_clock_disable()

◆ rcc_periph_clock_enable()

◆ rcc_periph_reset_hold()

◆ rcc_periph_reset_pulse()

◆ rcc_periph_reset_release()

◆ rcc_peripheral_clear_reset()

◆ rcc_peripheral_disable_clock()

◆ rcc_peripheral_enable_clock()

◆ rcc_peripheral_reset()

◆ rcc_pll_output_enable()

◆ rcc_set_clock48_source()

◆ rcc_set_hpre()

◆ rcc_set_main_pll()

◆ rcc_set_mco()

◆ rcc_set_msi_range()

◆ rcc_set_msi_range_standby()

◆ rcc_set_pll_source()

◆ rcc_set_ppre1()

◆ rcc_set_ppre2()

◆ rcc_set_rtc_clock_source()

◆ rcc_set_sysclk_source()

◆ rcc_system_clock_source()

◆ rcc_uart_i2c_clksel_freq_hz()

◆ rcc_wait_for_osc_ready()

◆ rcc_wait_for_sysclk_status()

Variable Documentation

◆ rcc_ahb_frequency

◆ rcc_apb1_frequency

◆ rcc_apb2_frequency

◆ rcc_hsi16_configs