Defined Constants and Types for the GD32F1x0 Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	USBPRE: USB prescaler (RCC_CFGR[23:22])

	PLLMUL: PLL multiplication factor

	PLLXTPRE: HSE divider for PLL entry

	PLLSRC: PLL entry clock source

	ADCPRE: ADC prescaler

	RCC_CFGR APBx prescale factors
	These can be used for both APB1 and APB2 prescaling.

	HPRE: AHB prescaler

	SW: System clock switch

	RCC_CFGR Deprecated dividers
	Older compatible definitions to ease migration.

	RCC_APB2RSTR reset values values

	RCC_APB1RSTR reset values values

	RCC_AHBENR enable values

	RCC_APB2ENR enable values

	RCC_APB1ENR enable values

	RCC_AHBRSTR reset values values

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)

#define	RCC_CFGR MMIO32(RCC_BASE + 0x04)

#define	RCC_CIR MMIO32(RCC_BASE + 0x08)

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)

#define	RCC_AHBENR MMIO32(RCC_BASE + 0x14)

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x18)

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)

#define	RCC_BDCR MMIO32(RCC_BASE + 0x20)

#define	RCC_CSR MMIO32(RCC_BASE + 0x24)

#define	RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)

#define	RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)

#define	RCC_CFGR3 MMIO32(RCC_BASE + 0x30)

#define	RCC_CR2 MMIO32(RCC_BASE + 0x34)

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_CSSON (1 << 19)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_HSIRDY (1 << 1)

#define	RCC_CR_HSION (1 << 0)

#define	RCC_CFGR_PLLNODIV (1 << 31)

#define	RCC_CFGR_MCOPRE_SHIFT 28

#define	RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)

#define	RCC_CFGR_PLLMUL_4_SHIFT 27

#define	RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT)

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0x7

#define	RCC_CFGR_MCO_NOCLK 0

#define	RCC_CFGR_MCO_HSI14 1

#define	RCC_CFGR_MCO_LSI 2

#define	RCC_CFGR_MCO_LSE 3

#define	RCC_CFGR_MCO_SYSCLK 4

#define	RCC_CFGR_MCO_HSI 5

#define	RCC_CFGR_MCO_HSE 6

#define	RCC_CFGR_MCO_PLL 7

#define	RCC_CFGR_USBPRE_SHIFT 22

#define	RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT)

#define	RCC_CFGR_PLLMUL_0_3_SHIFT 18

#define	RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT)

#define	RCC_CFGR_PLLXTPRE (1 << 17)

#define	RCC_CFGR_PLLSRC (1 << 16)

#define	RCC_CFGR_ADCPRE_SHIFT 14

#define	RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT)

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT)

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0

#define	RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1

#define	RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2

#define	RCC_CIR_CSSC (1 << 23)

#define	RCC_CIR_HSI14RDYC (1 << 21)

#define	RCC_CIR_PLLRDYC (1 << 20)

#define	RCC_CIR_HSERDYC (1 << 19)

#define	RCC_CIR_HSIRDYC (1 << 18)

#define	RCC_CIR_LSERDYC (1 << 17)

#define	RCC_CIR_LSIRDYC (1 << 16)

#define	RCC_CIR_HSI14RDYIE (1 << 13)

#define	RCC_CIR_PLLRDYIE (1 << 12)

#define	RCC_CIR_HSERDYIE (1 << 11)

#define	RCC_CIR_HSIRDYIE (1 << 10)

#define	RCC_CIR_LSERDYIE (1 << 9)

#define	RCC_CIR_LSIRDYIE (1 << 8)

#define	RCC_CIR_CSSF (1 << 7)

#define	RCC_CIR_HSI14RDYF (1 << 5)

#define	RCC_CIR_PLLRDYF (1 << 4)

#define	RCC_CIR_HSERDYF (1 << 3)

#define	RCC_CIR_HSIRDYF (1 << 2)

#define	RCC_CIR_LSERDYF (1 << 1)

#define	RCC_CIR_LSIRDYF (1 << 0)

#define	RCC_BDCR_BDRST (1 << 16)

#define	RCC_BDCR_RTCEN (1 << 15)

#define	RCC_BDCR_LSEBYP (1 << 2)

#define	RCC_BDCR_LSERDY (1 << 1)

#define	RCC_BDCR_LSEON (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_RMVF (1 << 24)

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	RCC_CFGR2_PREDIV 0xf

#define	RCC_CFGR2_PREDIV_NODIV 0x0

#define	RCC_CFGR2_PREDIV_DIV2 0x1

#define	RCC_CFGR2_PREDIV_DIV3 0x2

#define	RCC_CFGR2_PREDIV_DIV4 0x3

#define	RCC_CFGR2_PREDIV_DIV5 0x4

#define	RCC_CFGR2_PREDIV_DIV6 0x5

#define	RCC_CFGR2_PREDIV_DIV7 0x6

#define	RCC_CFGR2_PREDIV_DIV8 0x7

#define	RCC_CFGR2_PREDIV_DIV9 0x8

#define	RCC_CFGR2_PREDIV_DIV10 0x9

#define	RCC_CFGR2_PREDIV_DIV11 0xa

#define	RCC_CFGR2_PREDIV_DIV12 0xb

#define	RCC_CFGR2_PREDIV_DIV13 0xc

#define	RCC_CFGR2_PREDIV_DIV14 0xd

#define	RCC_CFGR2_PREDIV_DIV15 0xe

#define	RCC_CFGR2_PREDIV_DIV16 0xf

#define	RCC_CFGR3_USART2SW_SHIFT 16

#define	RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT)

#define	RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)

#define	RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)

#define	RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)

#define	RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)

#define	RCC_CFGR3_ADCSW (1 << 8)

#define	RCC_CFGR3_CECSW (1 << 6)

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_hsi { RCC_CLOCK_HSI_48MHZ , RCC_CLOCK_HSI_64MHZ , RCC_CLOCK_HSI_END }

enum	rcc_clock_hse8 { RCC_CLOCK_HSE8_72MHZ , RCC_CLOCK_HSE8_END }

enum	rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_DMA = _REG_BIT(0x14, 0) , RCC_SRAM = _REG_BIT(0x14, 2) , RCC_FLTF = _REG_BIT(0x14, 4) , RCC_CRC = _REG_BIT(0x14, 6) , RCC_GPIOA = _REG_BIT(0x14, 17) , RCC_GPIOB = _REG_BIT(0x14, 18) , RCC_GPIOC = _REG_BIT(0x14, 19) , RCC_GPIOD = _REG_BIT(0x14, 20) , RCC_GPIOF = _REG_BIT(0x14, 22) , RCC_TSC = _REG_BIT(0x14, 24) , RCC_SYSCFG_COMP = _REG_BIT(0x18, 0) , RCC_ADC = _REG_BIT(0x18, 9) , RCC_TIM1 = _REG_BIT(0x18, 11) , RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_USART1 = _REG_BIT(0x18, 14) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) , RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) , RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_WWDG = _REG_BIT(0x1C, 11) , RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_SPI3 = _REG_BIT(0x1C, 15) , RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) , RCC_PWR = _REG_BIT(0x1C, 28) , RCC_DAC = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30) }

enum	rcc_periph_rst { RST_BACKUPDOMAIN = _REG_BIT(0x20, 16) , RST_GPIOA = _REG_BIT(0x28, 17) , RST_GPIOB = _REG_BIT(0x28, 18) , RST_GPIOC = _REG_BIT(0x28, 19) , RST_GPIOD = _REG_BIT(0x28, 20) , RST_GPIOE = _REG_BIT(0x28, 21) , RST_GPIOF = _REG_BIT(0x28, 22) , RST_TSC = _REG_BIT(0x28, 24) , RST_SYSCFG = _REG_BIT(0x0C, 0) , RST_ADC = _REG_BIT(0x0C, 9) , RST_TIM1 = _REG_BIT(0x0C, 11) , RST_SPI1 = _REG_BIT(0x0C, 12) , RST_USART1 = _REG_BIT(0x0C, 14) , RST_TIM15 = _REG_BIT(0x0C, 16) , RST_TIM16 = _REG_BIT(0x0C, 17) , RST_TIM17 = _REG_BIT(0x0C, 18) , RST_TIM2 = _REG_BIT(0x10, 0) , RST_TIM3 = _REG_BIT(0x10, 1) , RST_TIM6 = _REG_BIT(0x10, 4) , RST_TIM14 = _REG_BIT(0x10, 8) , RST_WWDG = _REG_BIT(0x10, 11) , RST_SPI2 = _REG_BIT(0x10, 14) , RST_SPI3 = _REG_BIT(0x10, 15) , RST_USART2 = _REG_BIT(0x10, 17) , RST_I2C1 = _REG_BIT(0x10, 21) , RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC = _REG_BIT(0x10, 29) , RST_CEC = _REG_BIT(0x10, 30) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)
	RCC Clear the Oscillator Ready Interrupt Flag. More...

void	rcc_osc_ready_int_enable (enum rcc_osc osc)
	RCC Enable the Oscillator Ready Interrupt. More...

void	rcc_osc_ready_int_disable (enum rcc_osc osc)
	RCC Disable the Oscillator Ready Interrupt. More...

int	rcc_osc_ready_int_flag (enum rcc_osc osc)
	RCC Read the Oscillator Ready Interrupt Flag. More...

void	rcc_css_int_clear (void)
	RCC Clear the Clock Security System Interrupt Flag. More...

int	rcc_css_int_flag (void)
	RCC Read the Clock Security System Interrupt Flag. More...

void	rcc_osc_on (enum rcc_osc osc)
	RCC Turn on an Oscillator. More...

void	rcc_osc_off (enum rcc_osc osc)
	RCC Turn off an Oscillator. More...

void	rcc_css_enable (void)
	RCC Enable the Clock Security System. More...

void	rcc_css_disable (void)
	RCC Disable the Clock Security System. More...

void	rcc_set_sysclk_source (uint32_t clk)
	RCC Set the Source for the System Clock. More...

void	rcc_set_pll_multiplication_factor (uint32_t mul)
	RCC Set the PLL Multiplication Factor. More...

void	rcc_set_pll_source (uint32_t pllsrc)
	RCC Set the PLL Clock Source. More...

void	rcc_set_pllxtpre (uint32_t pllxtpre)
	RCC Set the HSE Frequency Divider used as PLL Clock Source. More...

uint32_t	rcc_rtc_clock_enabled_flag (void)
	RCC RTC Clock Enabled Flag. More...

void	rcc_enable_rtc_clock (void)
	RCC Enable the RTC clock. More...

void	rcc_set_rtc_clock_source (enum rcc_osc clock_source)
	RCC Set the Source for the RTC clock. More...

void	rcc_set_adcpre (uint32_t adcpre)
	ADC Setup the A/D Clock. More...

void	rcc_set_ppre2 (uint32_t ppre1)
	RCC Set the APB2 Prescale Factor. More...

void	rcc_set_ppre1 (uint32_t ppre1)
	RCC Set the APB1 Prescale Factor. More...

void	rcc_set_hpre (uint32_t hpre)
	RCC Set the AHB Prescale Factor. More...

void	rcc_set_usbpre (uint32_t usbpre)
	RCC Set the USB Prescale Factor. More...

void	rcc_set_prediv (uint32_t prediv)

uint32_t	rcc_system_clock_source (void)
	RCC Get the System Clock Source. More...

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_backupdomain_reset (void)
	RCC Reset the Backup Domain. More...

void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency
	Set the default clock frequencies. More...

uint32_t	rcc_apb2_frequency

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_HSI_END]

const struct rcc_clock_scale	rcc_hse8_configs [RCC_CLOCK_HSE8_END]

Detailed Description

Defined Constants and Types for the GD32F1x0 Reset and Clock Control

Version: 1.0.0

Author: © 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>; © 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de

Date: 18 August 2012

LGPL License Terms libopencm3 License

Author: © 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 463 of file gd32/f1x0/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)

Definition at line 51 of file gd32/f1x0/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)

Definition at line 56 of file gd32/f1x0/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)

Definition at line 53 of file gd32/f1x0/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)

Definition at line 50 of file gd32/f1x0/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)

Definition at line 52 of file gd32/f1x0/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)

Definition at line 49 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR MMIO32(RCC_BASE + 0x20)

Definition at line 54 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST (1 << 16)

Definition at line 367 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP (1 << 2)

Definition at line 370 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON (1 << 0)

Definition at line 372 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY (1 << 1)

Definition at line 371 of file gd32/f1x0/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN (1 << 15)

Definition at line 368 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR MMIO32(RCC_BASE + 0x04)

Definition at line 47 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2

#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)

Definition at line 57 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV

#define RCC_CFGR2_PREDIV 0xf

Definition at line 394 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV10

#define RCC_CFGR2_PREDIV_DIV10 0x9

Definition at line 404 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV11

#define RCC_CFGR2_PREDIV_DIV11 0xa

Definition at line 405 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV12

#define RCC_CFGR2_PREDIV_DIV12 0xb

Definition at line 406 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV13

#define RCC_CFGR2_PREDIV_DIV13 0xc

Definition at line 407 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV14

#define RCC_CFGR2_PREDIV_DIV14 0xd

Definition at line 408 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV15

#define RCC_CFGR2_PREDIV_DIV15 0xe

Definition at line 409 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV16

#define RCC_CFGR2_PREDIV_DIV16 0xf

Definition at line 410 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV2

#define RCC_CFGR2_PREDIV_DIV2 0x1

Definition at line 396 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV3

#define RCC_CFGR2_PREDIV_DIV3 0x2

Definition at line 397 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV4

#define RCC_CFGR2_PREDIV_DIV4 0x3

Definition at line 398 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV5

#define RCC_CFGR2_PREDIV_DIV5 0x4

Definition at line 399 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV6

#define RCC_CFGR2_PREDIV_DIV6 0x5

Definition at line 400 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV7

#define RCC_CFGR2_PREDIV_DIV7 0x6

Definition at line 401 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV8

#define RCC_CFGR2_PREDIV_DIV8 0x7

Definition at line 402 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV9

#define RCC_CFGR2_PREDIV_DIV9 0x8

Definition at line 403 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR2_PREDIV_NODIV

#define RCC_CFGR2_PREDIV_NODIV 0x0

Definition at line 395 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3

#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)

Definition at line 58 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_ADCSW

#define RCC_CFGR3_ADCSW (1 << 8)

Definition at line 421 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_CECSW

#define RCC_CFGR3_CECSW (1 << 6)

Definition at line 422 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW

#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT)

Definition at line 415 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW_HSI

#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)

Definition at line 419 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW_LSE

#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)

Definition at line 418 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW_PCLK

#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)

Definition at line 416 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW_SHIFT

#define RCC_CFGR3_USART2SW_SHIFT 16

Definition at line 414 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR3_USART2SW_SYSCLK

#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)

Definition at line 417 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_ADCPRE

#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT)

Definition at line 114 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_ADCPRE_SHIFT

#define RCC_CFGR_ADCPRE_SHIFT 14

Definition at line 113 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT)

Definition at line 123 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT 4

Definition at line 122 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE 6

Definition at line 101 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI 5

Definition at line 100 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_HSI14

#define RCC_CFGR_MCO_HSI14 1

Definition at line 96 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE 3

Definition at line 98 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI 2

Definition at line 97 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK 0x7

Definition at line 94 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK 0

Definition at line 95 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL 7

Definition at line 102 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT 24

Definition at line 93 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK 4

Definition at line 99 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 80 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 81 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV128

#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 88 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 85 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 82 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV32

#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 86 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 83 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV64

#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 87 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 84 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_MCOPRE_SHIFT

#define RCC_CFGR_MCOPRE_SHIFT 28

Definition at line 79 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLMUL_0_3

#define RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT)

Definition at line 108 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLMUL_0_3_SHIFT

#define RCC_CFGR_PLLMUL_0_3_SHIFT 18

Definition at line 107 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLMUL_4

#define RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT)

Definition at line 91 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLMUL_4_SHIFT

#define RCC_CFGR_PLLMUL_4_SHIFT 27

Definition at line 90 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLNODIV

#define RCC_CFGR_PLLNODIV (1 << 31)

Definition at line 77 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC (1 << 16)

Definition at line 111 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLXTPRE (1 << 17)

Definition at line 110 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)

Definition at line 120 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK 0x7

Definition at line 186 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT [1/2]

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 185 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT [2/2]

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 185 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)

Definition at line 117 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK 0x7

Definition at line 184 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT [1/2]

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 183 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT [2/2]

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 183 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SW

#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)

Definition at line 129 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT 0

Definition at line 128 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)

Definition at line 126 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT 2

Definition at line 125 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSECLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1

Definition at line 214 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSICLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0

Definition at line 213 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_PLLCLK

#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2

Definition at line 215 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_USBPRE

#define RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT)

Definition at line 105 of file gd32/f1x0/rcc.h.

◆ RCC_CFGR_USBPRE_SHIFT

#define RCC_CFGR_USBPRE_SHIFT 22

Definition at line 104 of file gd32/f1x0/rcc.h.

◆ RCC_CIR

#define RCC_CIR MMIO32(RCC_BASE + 0x08)

Definition at line 48 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC (1 << 23)

Definition at line 261 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF (1 << 7)

Definition at line 280 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC (1 << 19)

Definition at line 266 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF (1 << 3)

Definition at line 285 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE (1 << 11)

Definition at line 274 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSI14RDYC

#define RCC_CIR_HSI14RDYC (1 << 21)

Definition at line 264 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSI14RDYF

#define RCC_CIR_HSI14RDYF (1 << 5)

Definition at line 283 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSI14RDYIE

#define RCC_CIR_HSI14RDYIE (1 << 13)

Definition at line 272 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC (1 << 18)

Definition at line 267 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF (1 << 2)

Definition at line 286 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE (1 << 10)

Definition at line 275 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC (1 << 17)

Definition at line 268 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF (1 << 1)

Definition at line 287 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE (1 << 9)

Definition at line 276 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC (1 << 16)

Definition at line 269 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF (1 << 0)

Definition at line 288 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE (1 << 8)

Definition at line 277 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC (1 << 20)

Definition at line 265 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF (1 << 4)

Definition at line 284 of file gd32/f1x0/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE (1 << 12)

Definition at line 273 of file gd32/f1x0/rcc.h.

◆ RCC_CR

#define RCC_CR MMIO32(RCC_BASE + 0x00)

Definition at line 46 of file gd32/f1x0/rcc.h.

◆ RCC_CR2

#define RCC_CR2 MMIO32(RCC_BASE + 0x34)

Definition at line 59 of file gd32/f1x0/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON (1 << 19)

Definition at line 66 of file gd32/f1x0/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP (1 << 18)

Definition at line 67 of file gd32/f1x0/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON (1 << 16)

Definition at line 69 of file gd32/f1x0/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY (1 << 17)

Definition at line 68 of file gd32/f1x0/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION (1 << 0)

Definition at line 73 of file gd32/f1x0/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY (1 << 1)

Definition at line 72 of file gd32/f1x0/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON (1 << 24)

Definition at line 65 of file gd32/f1x0/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY (1 << 25)

Definition at line 64 of file gd32/f1x0/rcc.h.

◆ RCC_CSR

#define RCC_CSR MMIO32(RCC_BASE + 0x24)

Definition at line 55 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF (1 << 29)

Definition at line 378 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF (1 << 31)

Definition at line 376 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION (1 << 0)

Definition at line 384 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY (1 << 1)

Definition at line 383 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF (1 << 26)

Definition at line 381 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF (1 << 27)

Definition at line 380 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF (1 << 24)

Definition at line 382 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF (1 << 28)

Definition at line 379 of file gd32/f1x0/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF (1 << 30)

Definition at line 377 of file gd32/f1x0/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_hse8

enum rcc_clock_hse8

Enumerator
RCC_CLOCK_HSE8_72MHZ
RCC_CLOCK_HSE8_END

Definition at line 437 of file gd32/f1x0/rcc.h.

◆ rcc_clock_hsi

enum rcc_clock_hsi

Enumerator
RCC_CLOCK_HSI_48MHZ
RCC_CLOCK_HSI_64MHZ
RCC_CLOCK_HSI_END

Definition at line 431 of file gd32/f1x0/rcc.h.

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_PLL
RCC_HSE
RCC_HSI
RCC_LSE
RCC_LSI

Definition at line 459 of file gd32/f1x0/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_DMA
RCC_SRAM
RCC_FLTF
RCC_CRC
RCC_GPIOA
RCC_GPIOB
RCC_GPIOC
RCC_GPIOD
RCC_GPIOF
RCC_TSC
RCC_SYSCFG_COMP
RCC_ADC
RCC_TIM1
RCC_SPI1
RCC_USART1
RCC_TIM15
RCC_TIM16
RCC_TIM17
RCC_TIM2
RCC_TIM3
RCC_TIM6
RCC_TIM14
RCC_WWDG
RCC_SPI2
RCC_SPI3
RCC_USART2
RCC_I2C1
RCC_I2C2
RCC_USB
RCC_PWR
RCC_DAC
RCC_CEC

Definition at line 469 of file gd32/f1x0/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_BACKUPDOMAIN
RST_GPIOA
RST_GPIOB
RST_GPIOC
RST_GPIOD
RST_GPIOE
RST_GPIOF
RST_TSC
RST_SYSCFG
RST_ADC
RST_TIM1
RST_SPI1
RST_USART1
RST_TIM15
RST_TIM16
RST_TIM17
RST_TIM2
RST_TIM3
RST_TIM6
RST_TIM14
RST_WWDG
RST_SPI2
RST_SPI3
RST_USART2
RST_I2C1
RST_I2C2
RST_USB
RST_PWR
RST_DAC
RST_CEC

Definition at line 510 of file gd32/f1x0/rcc.h.

Function Documentation

◆ rcc_backupdomain_reset()

void rcc_backupdomain_reset ( void )

RCC Reset the Backup Domain.

The backup domain registers are reset to disable RTC controls and clear user data.

Definition at line 644 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_BDRST.

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Setup clocks to run from PLL.

The arguments provide the pll source, multipliers, dividers, all that's needed to establish a system clock.

Parameters

clock clock information structure

Definition at line 581 of file rcc.c.

References rcc_clock_scale::adcpre, rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, rcc_clock_scale::hpre, rcc_clock_scale::pll_hse_prediv, rcc_clock_scale::pllmul, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_PLLSRC_HSE_CLK, RCC_CFGR_PLLSRC_HSI_CLK_DIV2, RCC_CFGR_SW_SYSCLKSEL_HSECLK, RCC_CFGR_SW_SYSCLKSEL_HSICLK, RCC_CFGR_SW_SYSCLKSEL_PLLCLK, RCC_HSE, RCC_HSI, rcc_osc_on(), RCC_PLL, rcc_set_adcpre(), rcc_set_hpre(), rcc_set_pll_multiplication_factor(), rcc_set_pll_source(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_prediv(), rcc_set_sysclk_source(), rcc_set_usbpre(), rcc_wait_for_osc_ready(), rcc_clock_scale::usbpre, and rcc_clock_scale::use_hse.

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◆ rcc_css_disable()

void rcc_css_disable ( void )

RCC Disable the Clock Security System.

Definition at line 351 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

RCC Enable the Clock Security System.

Definition at line 341 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

RCC Clear the Clock Security System Interrupt Flag.

Definition at line 222 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

RCC Read the Clock Security System Interrupt Flag.

Returns: int. Boolean value for flag set.

Definition at line 233 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_enable_rtc_clock()

void rcc_enable_rtc_clock ( void )

RCC Enable the RTC clock.

Definition at line 427 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

RCC Turn off an Oscillator.

Disable an oscillator and power off.

Note: An oscillator cannot be turned off if it is selected as the system clock.; The LSE clock is in the backup domain and cannot be disabled until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID

Definition at line 315 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

RCC Turn on an Oscillator.

Enable an oscillator and power on. Each oscillator requires an amount of time to settle to a usable state. Refer to datasheets for time delay information. A status flag is available to indicate when the oscillator becomes ready (see rcc_osc_ready_int_flag and rcc_wait_for_osc_ready).

Note: The LSE clock is in the backup domain and cannot be enabled until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID

Definition at line 280 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

RCC Clear the Oscillator Ready Interrupt Flag.

Clear the interrupt flag that was set when a clock oscillator became ready to use.

Parameters

[in] osc Oscillator ID

Definition at line 112 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

RCC Disable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 166 of file rcc.c.

References RCC_CIR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

RCC Enable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 139 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

RCC Read the Oscillator Ready Interrupt Flag.

Parameters

[in] osc Oscillator ID

Returns: int. Boolean value for flag set.

Definition at line 194 of file rcc.c.

References cm3_assert_not_reached, RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_rtc_clock_enabled_flag()

uint32_t rcc_rtc_clock_enabled_flag ( void )

RCC RTC Clock Enabled Flag.

Returns: uint32_t. Nonzero if the RTC Clock is enabled.

Definition at line 417 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

◆ rcc_set_adcpre()

void rcc_set_adcpre ( uint32_t adcpre )

ADC Setup the A/D Clock.

The ADC's have a common clock prescale setting.

Parameters

[in] adcpre Prescale divider taken from ADCPRE: ADC prescaler

Definition at line 487 of file rcc.c.

References rcc_clock_scale::adcpre, RCC_CFGR, and RCC_CFGR_ADCPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

RCC Set the AHB Prescale Factor.

Parameters

[in] hpre AHB prescale factor HPRE: AHB prescaler

Definition at line 526 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_mco()

void rcc_set_mco ( uint32_t mcosrc )

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in] mcosrc the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_pll_multiplication_factor()

void rcc_set_pll_multiplication_factor ( uint32_t mul )

RCC Set the PLL Multiplication Factor.

Note: This only has effect when the PLL is disabled.

Parameters

[in] mul PLL multiplication factor PLLMUL: PLL multiplication factor

Definition at line 376 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLMUL_0_3_SHIFT, and RCC_CFGR_PLLMUL_4_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t pllsrc )

RCC Set the PLL Clock Source.

Note: This only has effect when the PLL is disabled.

Parameters

[in] pllsrc PLL clock source PLLSRC: PLL entry clock source

Definition at line 391 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_pllxtpre()

void rcc_set_pllxtpre ( uint32_t pllxtpre )

RCC Set the HSE Frequency Divider used as PLL Clock Source.

Note: This only has effect when the PLL is disabled.

Parameters

[in] pllxtpre HSE division factor PLLXTPRE: HSE divider for PLL entry

Definition at line 405 of file rcc.c.

References RCC_CFGR.

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t ppre1 )

RCC Set the APB1 Prescale Factor.

Note: The APB1 clock frequency must not exceed 36MHz.

Parameters

[in] ppre1 APB1 prescale factor rcc_cfgr_apb1pre

Definition at line 513 of file rcc.c.

References rcc_clock_scale::ppre1, RCC_CFGR, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t ppre2 )

RCC Set the APB2 Prescale Factor.

Parameters

[in] ppre2 APB2 prescale factor rcc_cfgr_apb2pre

Definition at line 499 of file rcc.c.

References rcc_clock_scale::ppre2, RCC_CFGR, and RCC_CFGR_PPRE2_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_prediv()

void rcc_set_prediv ( uint32_t prediv )

Definition at line 549 of file rcc.c.

References RCC_CFGR2.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_rtc_clock_source()

void rcc_set_rtc_clock_source ( enum rcc_osc clock_source )

RCC Set the Source for the RTC clock.

Parameters

[in] clock_source RTC clock source. Only HSE/128, LSE and LSI.

Definition at line 438 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSEON, RCC_CR_HSERDY, RCC_CSR, RCC_CSR_LSION, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t clk )

RCC Set the Source for the System Clock.

Parameters

[in] clk System Clock Selection SW: System clock switch

Definition at line 362 of file rcc.c.

References RCC_CFGR, and RCC_CFGR_SW_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_usbpre()

void rcc_set_usbpre ( uint32_t usbpre )

RCC Set the USB Prescale Factor.

The prescale factor can be set to 1 (no prescale) for use when the PLL clock is 48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock.

Note: This bit cannot be reset while the USB clock is enabled.

Parameters

[in] usbpre USB prescale factor USBPRE: USB prescaler (RCC_CFGR[23:22])

Definition at line 544 of file rcc.c.

References RCC_CFGR, and rcc_clock_scale::usbpre.

Referenced by rcc_clock_setup_pll().

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◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void )

RCC Get the System Clock Source.

Returns

Unsigned int32. System clock source:

00 indicates HSE
01 indicates LSE
02 indicates PLL

Definition at line 563 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS, and RCC_CFGR_SWS_SHIFT.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc osc )

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Wait for Oscillator Ready.

Parameters

[in] osc Oscillator ID

Definition at line 244 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency

extern

Definition at line 60 of file rcc.c.

Referenced by rcc_clock_setup_pll().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency

extern

Set the default clock frequencies.

Definition at line 58 of file rcc.c.

Referenced by rcc_clock_setup_pll().

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency

extern

Definition at line 59 of file rcc.c.

Referenced by rcc_clock_setup_pll().

◆ rcc_hse8_configs

const struct rcc_clock_scale rcc_hse8_configs[RCC_CLOCK_HSE8_END]

extern

Definition at line 87 of file rcc.c.

◆ rcc_hsi_configs

const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END]

extern

Definition at line 62 of file rcc.c.

Data Structures

Modules

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _REG_BIT

◆ RCC_AHBENR

◆ RCC_AHBRSTR

◆ RCC_APB1ENR

◆ RCC_APB1RSTR

◆ RCC_APB2ENR

◆ RCC_APB2RSTR

◆ RCC_BDCR

◆ RCC_BDCR_BDRST

◆ RCC_BDCR_LSEBYP

◆ RCC_BDCR_LSEON

◆ RCC_BDCR_LSERDY

◆ RCC_BDCR_RTCEN

◆ RCC_CFGR

◆ RCC_CFGR2

◆ RCC_CFGR2_PREDIV

◆ RCC_CFGR2_PREDIV_DIV10

◆ RCC_CFGR2_PREDIV_DIV11

◆ RCC_CFGR2_PREDIV_DIV12

◆ RCC_CFGR2_PREDIV_DIV13

◆ RCC_CFGR2_PREDIV_DIV14

◆ RCC_CFGR2_PREDIV_DIV15

◆ RCC_CFGR2_PREDIV_DIV16

◆ RCC_CFGR2_PREDIV_DIV2

◆ RCC_CFGR2_PREDIV_DIV3

◆ RCC_CFGR2_PREDIV_DIV4

◆ RCC_CFGR2_PREDIV_DIV5

◆ RCC_CFGR2_PREDIV_DIV6

◆ RCC_CFGR2_PREDIV_DIV7

◆ RCC_CFGR2_PREDIV_DIV8

◆ RCC_CFGR2_PREDIV_DIV9

◆ RCC_CFGR2_PREDIV_NODIV

◆ RCC_CFGR3

◆ RCC_CFGR3_ADCSW

◆ RCC_CFGR3_CECSW

◆ RCC_CFGR3_USART2SW

◆ RCC_CFGR3_USART2SW_HSI

◆ RCC_CFGR3_USART2SW_LSE

◆ RCC_CFGR3_USART2SW_PCLK

◆ RCC_CFGR3_USART2SW_SHIFT

◆ RCC_CFGR3_USART2SW_SYSCLK

◆ RCC_CFGR_ADCPRE

◆ RCC_CFGR_ADCPRE_SHIFT

◆ RCC_CFGR_HPRE

◆ RCC_CFGR_HPRE_SHIFT

◆ RCC_CFGR_MCO_HSE

◆ RCC_CFGR_MCO_HSI

◆ RCC_CFGR_MCO_HSI14

◆ RCC_CFGR_MCO_LSE

◆ RCC_CFGR_MCO_LSI

◆ RCC_CFGR_MCO_MASK

◆ RCC_CFGR_MCO_NOCLK

◆ RCC_CFGR_MCO_PLL

◆ RCC_CFGR_MCO_SHIFT

◆ RCC_CFGR_MCO_SYSCLK

◆ RCC_CFGR_MCOPRE

◆ RCC_CFGR_MCOPRE_DIV1

◆ RCC_CFGR_MCOPRE_DIV128

◆ RCC_CFGR_MCOPRE_DIV16

◆ RCC_CFGR_MCOPRE_DIV2

◆ RCC_CFGR_MCOPRE_DIV32

◆ RCC_CFGR_MCOPRE_DIV4

◆ RCC_CFGR_MCOPRE_DIV64

◆ RCC_CFGR_MCOPRE_DIV8

◆ RCC_CFGR_MCOPRE_SHIFT

◆ RCC_CFGR_PLLMUL_0_3

◆ RCC_CFGR_PLLMUL_0_3_SHIFT

◆ RCC_CFGR_PLLMUL_4

◆ RCC_CFGR_PLLMUL_4_SHIFT

◆ RCC_CFGR_PLLNODIV

◆ RCC_CFGR_PLLSRC

◆ RCC_CFGR_PLLXTPRE