libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Go to the source code of this file.
Data Structures | |
struct | usb_transfer_descriptor_t |
struct | usb_queue_head_t |
Typedefs | |
typedef struct usb_transfer_descriptor_t | usb_transfer_descriptor_t |
#define BIT_MASK | ( | base_name | ) | (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) |
#define USB0_ASYNCLISTADDR_ASYBASE31_5 | ( | x | ) | ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) |
#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) |
#define USB0_BINTERVAL_BINT | ( | x | ) | ((x) << USB0_BINTERVAL_BINT_SHIFT) |
#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) |
#define USB0_BURSTSIZE_RXPBURST | ( | x | ) | ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) |
#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) |
#define USB0_BURSTSIZE_TXPBURST | ( | x | ) | ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) |
#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) |
#define USB0_CAPLENGTH_CAPLENGTH | ( | x | ) | ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) |
#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) |
#define USB0_CAPLENGTH_HCIVERSION | ( | x | ) | ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) |
#define USB0_CAPLENGTH_HCIVERSION_MASK (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) |
#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) |
#define USB0_DCCPARAMS_DEN | ( | x | ) | ((x) << USB0_DCCPARAMS_DEN_SHIFT) |
#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) |
#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) |
#define USB0_DEVICEADDR_USBADR | ( | x | ) | ((x) << USB0_DEVICEADDR_USBADR_SHIFT) |
#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) |
#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) |
#define USB0_ENDPOINTLISTADDR_EPBASE31_11 | ( | x | ) | ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) |
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) |
#define USB0_ENDPTCOMPLETE_ERCE | ( | x | ) | ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) |
#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) |
#define USB0_ENDPTCOMPLETE_ETCE | ( | x | ) | ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) |
#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) |
#define USB0_ENDPTCTRL | ( | logical_ep | ) |
#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) |
#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) |
#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) |
#define USB0_ENDPTCTRL0_RXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) |
#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) |
#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) |
#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) |
#define USB0_ENDPTCTRL0_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) |
#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) |
#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) |
#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) |
#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) |
#define USB0_ENDPTCTRL1_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) |
#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) |
#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) |
#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) |
#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) |
#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) |
#define USB0_ENDPTCTRL1_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) |
#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) |
#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) |
#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) |
#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) |
#define USB0_ENDPTCTRL2_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) |
#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) |
#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) |
#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) |
#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) |
#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) |
#define USB0_ENDPTCTRL2_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) |
#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) |
#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) |
#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) |
#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) |
#define USB0_ENDPTCTRL3_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) |
#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) |
#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) |
#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) |
#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) |
#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) |
#define USB0_ENDPTCTRL3_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) |
#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) |
#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) |
#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) |
#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) |
#define USB0_ENDPTCTRL4_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) |
#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) |
#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) |
#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) |
#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) |
#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) |
#define USB0_ENDPTCTRL4_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) |
#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) |
#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) |
#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) |
#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) |
#define USB0_ENDPTCTRL5_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) |
#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) |
#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) |
#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) |
#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) |
#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) |
#define USB0_ENDPTCTRL5_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT) |
#define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT) |
#define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT) |
#define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT) |
#define USB0_ENDPTCTRL_RXT | ( | x | ) | ((x) << USB0_ENDPTCTRL_RXT_SHIFT) |
#define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT) |
#define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT) |
#define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT) |
#define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT) |
#define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT) |
#define USB0_ENDPTCTRL_TXT1_0 | ( | x | ) | ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT) |
#define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT) |
#define USB0_ENDPTFLUSH_FERB | ( | x | ) | ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) |
#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) |
#define USB0_ENDPTFLUSH_FETB | ( | x | ) | ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) |
#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) |
#define USB0_ENDPTNAK_EPRN | ( | x | ) | ((x) << USB0_ENDPTNAK_EPRN_SHIFT) |
#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) |
#define USB0_ENDPTNAK_EPTN | ( | x | ) | ((x) << USB0_ENDPTNAK_EPTN_SHIFT) |
#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) |
#define USB0_ENDPTNAKEN_EPRNE | ( | x | ) | ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) |
#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) |
#define USB0_ENDPTNAKEN_EPTNE | ( | x | ) | ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) |
#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) |
#define USB0_ENDPTPRIME_PERB | ( | x | ) | ((x) << USB0_ENDPTPRIME_PERB_SHIFT) |
#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) |
#define USB0_ENDPTPRIME_PETB | ( | x | ) | ((x) << USB0_ENDPTPRIME_PETB_SHIFT) |
#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) |
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT | ( | x | ) | ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) |
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) |
#define USB0_ENDPTSTAT_ERBR | ( | x | ) | ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) |
#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) |
#define USB0_ENDPTSTAT_ETBR | ( | x | ) | ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) |
#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) |
#define USB0_FRINDEX_D_FRINDEX13_3 | ( | x | ) | ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) |
#define USB0_FRINDEX_D_FRINDEX13_3_MASK (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) |
#define USB0_FRINDEX_D_FRINDEX2_0 | ( | x | ) | ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) |
#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) |
#define USB0_FRINDEX_H_FRINDEX12_3 | ( | x | ) | ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) |
#define USB0_FRINDEX_H_FRINDEX12_3_MASK (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) |
#define USB0_FRINDEX_H_FRINDEX2_0 | ( | x | ) | ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) |
#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) |
#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) |
#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) |
#define USB0_HCCPARAMS_EECP | ( | x | ) | ((x) << USB0_HCCPARAMS_EECP_SHIFT) |
#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) |
#define USB0_HCCPARAMS_IST | ( | x | ) | ((x) << USB0_HCCPARAMS_IST_SHIFT) |
#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) |
#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) |
#define USB0_HCSPARAMS_N_CC | ( | x | ) | ((x) << USB0_HCSPARAMS_N_CC_SHIFT) |
#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) |
#define USB0_HCSPARAMS_N_PCC | ( | x | ) | ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) |
#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) |
#define USB0_HCSPARAMS_N_PORTS | ( | x | ) | ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) |
#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) |
#define USB0_HCSPARAMS_N_PTT | ( | x | ) | ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) |
#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) |
#define USB0_HCSPARAMS_N_TT | ( | x | ) | ((x) << USB0_HCSPARAMS_N_TT_SHIFT) |
#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) |
#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) |
#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) |
#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) |
#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) |
#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) |
#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) |
#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) |
#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) |
#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) |
#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) |
#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) |
#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) |
#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) |
#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) |
#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) |
#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) |
#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) |
#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) |
#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) |
#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) |
#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) |
#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) |
#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) |
#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) |
#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) |
#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) |
#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) |
#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) |
#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) |
#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) |
#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) |
#define USB0_PERIODICLISTBASE_PERBASE31_12 | ( | x | ) | ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) |
#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) |
#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) |
#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) |
#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) |
#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) |
#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) |
#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) |
#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) |
#define USB0_PORTSC1_D_PIC1_0 | ( | x | ) | ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) |
#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) |
#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) |
#define USB0_PORTSC1_D_PSPD | ( | x | ) | ((x) << USB0_PORTSC1_D_PSPD_SHIFT) |
#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) |
#define USB0_PORTSC1_D_PTC3_0 | ( | x | ) | ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) |
#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) |
#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) |
#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) |
#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) |
#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) |
#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) |
#define USB0_PORTSC1_H_LS | ( | x | ) | ((x) << USB0_PORTSC1_H_LS_SHIFT) |
#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) |
#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) |
#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) |
#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) |
#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) |
#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) |
#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) |
#define USB0_PORTSC1_H_PIC1_0 | ( | x | ) | ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) |
#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) |
#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) |
#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) |
#define USB0_PORTSC1_H_PSPD | ( | x | ) | ((x) << USB0_PORTSC1_H_PSPD_SHIFT) |
#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) |
#define USB0_PORTSC1_H_PTC3_0 | ( | x | ) | ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) |
#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) |
#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) |
#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) |
#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) |
#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) |
#define USB0_TTCTRL_TTHA | ( | x | ) | ((x) << USB0_TTCTRL_TTHA_SHIFT) |
#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) |
#define USB0_TXFILLTUNING_TXFIFOTHRES | ( | x | ) | ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) |
#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) |
#define USB0_TXFILLTUNING_TXSCHEATLTH | ( | x | ) | ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) |
#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) |
#define USB0_TXFILLTUNING_TXSCHOH | ( | x | ) | ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) |
#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) |
#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) |
#define USB0_USBCMD_D_ITC | ( | x | ) | ((x) << USB0_USBCMD_D_ITC_SHIFT) |
#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) |
#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) |
#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) |
#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) |
#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) |
#define USB0_USBCMD_H_ASP1_0 | ( | x | ) | ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) |
#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) |
#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) |
#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) |
#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) |
#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) |
#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) |
#define USB0_USBCMD_H_ITC | ( | x | ) | ((x) << USB0_USBCMD_H_ITC_SHIFT) |
#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) |
#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) |
#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) |
#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) |
#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) |
#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) |
#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) |
#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) |
#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) |
#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) |
#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) |
#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) |
#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) |
#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) |
#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) |
#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) |
#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) |
#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) |
#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) |
#define USB0_USBMODE_D_CM1_0 | ( | x | ) | ((x) << USB0_USBMODE_D_CM1_0_SHIFT) |
#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) |
#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) |
#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) |
#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) |
#define USB0_USBMODE_H_CM | ( | x | ) | ((x) << USB0_USBMODE_H_CM_SHIFT) |
#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) |
#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) |
#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) |
#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) |
#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) |
#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) |
#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) |
#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) |
#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) |
#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) |
#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) |
#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) |
#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) |
#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) |
#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) |
#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) |
#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) |
#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) |
#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) |
#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) |
#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) |
#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) |
#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) |
#define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) |
#define USB_QH_CAPABILITIES_MPL | ( | x | ) | BIT_ARG(USB_QH_CAPABILITIES_MPL, (x)) |
#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) |
#define USB_QH_CAPABILITIES_MULT | ( | x | ) | BIT_ARG(USB_QH_CAPABILITIES_MULT, (x)) |
#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) |
#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) |
#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) |
#define USB_TD_DTD_TOKEN_MULTO | ( | x | ) | BIT_ARG(USB_TD_DTD_TOKEN_MULTO, (x)) |
#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) |
#define USB_TD_DTD_TOKEN_STATUS_ACTIVE (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) |
#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) |
#define USB_TD_DTD_TOKEN_STATUS_HALTED (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) |
#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) |
#define USB_TD_DTD_TOKEN_TOTAL_BYTES | ( | x | ) | BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, (x)) |
#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) |
#define USB_TD_NEXT_DTD_POINTER_TERMINATE |
typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t |