libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
f0/rcc.h
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1/** @defgroup rcc_defines RCC Defines
2 *
3 * @brief <b>Defined Constants and Types for the STM32F0xx Reset and Clock
4Control</b>
5 *
6 * @ingroup STM32F0xx_defines
7 *
8 * @author @htmlonly &copy; @endhtmlonly 2013
9 * Frantisek Burian <BuFran@seznam.cz>
10 *
11 * @version 1.0.0
12 *
13 * @date 29 Jun 2013
14 *
15 * LGPL License Terms @ref lgpl_license
16 */
17/*
18 * This file is part of the libopencm3 project.
19 *
20 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
21 *
22 * This library is free software: you can redistribute it and/or modify
23 * it under the terms of the GNU Lesser General Public License as published by
24 * the Free Software Foundation, either version 3 of the License, or
25 * (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public License
33 * along with this library. If not, see <http://www.gnu.org/licenses/>.
34 */
35/**@{*/
36
37#ifndef LIBOPENCM3_RCC_H
38#define LIBOPENCM3_RCC_H
39
40/*****************************************************************************/
41/* Module definitions */
42/*****************************************************************************/
43
44/*****************************************************************************/
45/* Register definitions */
46/*****************************************************************************/
47
48#define RCC_CR MMIO32(RCC_BASE + 0x00)
49#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
50#define RCC_CIR MMIO32(RCC_BASE + 0x08)
51#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
52#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
53#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
54#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
55#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
56#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
57#define RCC_CSR MMIO32(RCC_BASE + 0x24)
58#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)
59#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)
60#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)
61#define RCC_CR2 MMIO32(RCC_BASE + 0x34)
62
63/*****************************************************************************/
64/* Register values */
65/*****************************************************************************/
66
67/* --- RCC_CR values ------------------------------------------------------- */
68
69#define RCC_CR_PLLRDY (1 << 25)
70#define RCC_CR_PLLON (1 << 24)
71#define RCC_CR_CSSON (1 << 19)
72#define RCC_CR_HSEBYP (1 << 18)
73#define RCC_CR_HSERDY (1 << 17)
74#define RCC_CR_HSEON (1 << 16)
75#define RCC_CR_HSICAL_SHIFT 8
76#define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT)
77#define RCC_CR_HSITRIM_SHIFT 3
78#define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT)
79#define RCC_CR_HSIRDY (1 << 1)
80#define RCC_CR_HSION (1 << 0)
81
82/* --- RCC_CFGR values ----------------------------------------------------- */
83
84#define RCC_CFGR_PLLNODIV (1 << 31)
85
86#define RCC_CFGR_MCOPRE_SHIFT 28
87#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)
88#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)
89#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)
90#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)
91#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)
92#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)
93#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)
94#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)
95#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)
96
97#define RCC_CFGR_MCO_SHIFT 24
98#define RCC_CFGR_MCO_MASK 0xf
99#define RCC_CFGR_MCO_NOCLK 0
100#define RCC_CFGR_MCO_HSI14 1
101#define RCC_CFGR_MCO_LSI 2
102#define RCC_CFGR_MCO_LSE 3
103#define RCC_CFGR_MCO_SYSCLK 4
104#define RCC_CFGR_MCO_HSI 5
105#define RCC_CFGR_MCO_HSE 6
106#define RCC_CFGR_MCO_PLL 7
107#define RCC_CFGR_MCO_HSI48 8
108
109#define RCC_CFGR_PLLMUL_SHIFT 18
110#define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT)
111/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor
112 * @{
113 */
114#define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT)
115#define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT)
116#define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT)
117#define RCC_CFGR_PLLMUL_MUL5 (0x03 << RCC_CFGR_PLLMUL_SHIFT)
118#define RCC_CFGR_PLLMUL_MUL6 (0x04 << RCC_CFGR_PLLMUL_SHIFT)
119#define RCC_CFGR_PLLMUL_MUL7 (0x05 << RCC_CFGR_PLLMUL_SHIFT)
120#define RCC_CFGR_PLLMUL_MUL8 (0x06 << RCC_CFGR_PLLMUL_SHIFT)
121#define RCC_CFGR_PLLMUL_MUL9 (0x07 << RCC_CFGR_PLLMUL_SHIFT)
122#define RCC_CFGR_PLLMUL_MUL10 (0x08 << RCC_CFGR_PLLMUL_SHIFT)
123#define RCC_CFGR_PLLMUL_MUL11 (0x09 << RCC_CFGR_PLLMUL_SHIFT)
124#define RCC_CFGR_PLLMUL_MUL12 (0x0A << RCC_CFGR_PLLMUL_SHIFT)
125#define RCC_CFGR_PLLMUL_MUL13 (0x0B << RCC_CFGR_PLLMUL_SHIFT)
126#define RCC_CFGR_PLLMUL_MUL14 (0x0C << RCC_CFGR_PLLMUL_SHIFT)
127#define RCC_CFGR_PLLMUL_MUL15 (0x0D << RCC_CFGR_PLLMUL_SHIFT)
128#define RCC_CFGR_PLLMUL_MUL16 (0x0E << RCC_CFGR_PLLMUL_SHIFT)
129/**@}*/
130
131#define RCC_CFGR_PLLXTPRE (1<<17)
132/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL source
133 * @{
134 */
135#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
136#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
137/**@}*/
138
139#define RCC_CFGR_PLLSRC (1<<16)
140/** @defgroup rcc_cfgr_pcs PLLSRC: PLL Clock source
141 * @{
142 */
143#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
144#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
145/**@}*/
146
147#define RCC_CFGR_PLLSRC0 (1<<15)
148#define RCC_CFGR_ADCPRE (1<<14)
149
150#define RCC_CFGR_PPRE_SHIFT 8
151#define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT)
152#define RCC_CFGR_PPRE_MASK 0x7
153/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB prescale Factors
154@{*/
155#define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT)
156#define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT)
157#define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT)
158#define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT)
159#define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT)
160/**@}*/
161
162#define RCC_CFGR_HPRE_SHIFT 4
163#define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT)
164#define RCC_CFGR_HPRE_MASK 0xf
165/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors
166@{*/
167#define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT)
168#define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT)
169#define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT)
170#define RCC_CFGR_HPRE_DIV8 (0xa << RCC_CFGR_HPRE_SHIFT)
171#define RCC_CFGR_HPRE_DIV16 (0xb << RCC_CFGR_HPRE_SHIFT)
172#define RCC_CFGR_HPRE_DIV64 (0xc << RCC_CFGR_HPRE_SHIFT)
173#define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT)
174#define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT)
175#define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT)
176/**@}*/
177
178#define RCC_CFGR_SWS_SHIFT 2
179#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)
180#define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT)
181#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT)
182#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT)
183#define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT)
184
185#define RCC_CFGR_SW_SHIFT 0
186#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)
187#define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT)
188#define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT)
189#define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT)
190#define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT)
191
192/* --- RCC_CIR values ------------------------------------------------------ */
193
194#define RCC_CIR_CSSC (1 << 23)
195#define RCC_CIR_HSI48RDYC (1 << 22)
196#define RCC_CIR_HSI14RDYC (1 << 21)
197#define RCC_CIR_PLLRDYC (1 << 20)
198#define RCC_CIR_HSERDYC (1 << 19)
199#define RCC_CIR_HSIRDYC (1 << 18)
200#define RCC_CIR_LSERDYC (1 << 17)
201#define RCC_CIR_LSIRDYC (1 << 16)
202#define RCC_CIR_HSI48RDYIE (1 << 14)
203#define RCC_CIR_HSI14RDYIE (1 << 13)
204#define RCC_CIR_PLLRDYIE (1 << 12)
205#define RCC_CIR_HSERDYIE (1 << 11)
206#define RCC_CIR_HSIRDYIE (1 << 10)
207#define RCC_CIR_LSERDYIE (1 << 9)
208#define RCC_CIR_LSIRDYIE (1 << 8)
209#define RCC_CIR_CSSF (1 << 7)
210#define RCC_CIR_HSI48RDYF (1 << 6)
211#define RCC_CIR_HSI14RDYF (1 << 5)
212#define RCC_CIR_PLLRDYF (1 << 4)
213#define RCC_CIR_HSERDYF (1 << 3)
214#define RCC_CIR_HSIRDYF (1 << 2)
215#define RCC_CIR_LSERDYF (1 << 1)
216#define RCC_CIR_LSIRDYF (1 << 0)
217
218/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
219@{*/
220#define RCC_APB2RSTR_DBGMCURST (1 << 22)
221#define RCC_APB2RSTR_TIM17RST (1 << 18)
222#define RCC_APB2RSTR_TIM16RST (1 << 17)
223#define RCC_APB2RSTR_TIM15RST (1 << 16)
224#define RCC_APB2RSTR_USART1RST (1 << 14)
225#define RCC_APB2RSTR_SPI1RST (1 << 12)
226#define RCC_APB2RSTR_TIM1RST (1 << 11)
227#define RCC_APB2RSTR_ADCRST (1 << 9)
228#define RCC_APB2RSTR_USART8RST (1 << 7)
229#define RCC_APB2RSTR_USART7RST (1 << 6)
230#define RCC_APB2RSTR_USART6RST (1 << 5)
231#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
232/**@}*/
233
234
235/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
236@{*/
237#define RCC_APB1RSTR_CECRST (1 << 30)
238#define RCC_APB1RSTR_DACRST (1 << 29)
239#define RCC_APB1RSTR_PWRRST (1 << 28)
240#define RCC_APB1RSTR_CRSRST (1 << 27)
241#define RCC_APB1RSTR_CANRST (1 << 25)
242#define RCC_APB1RSTR_USBRST (1 << 23)
243#define RCC_APB1RSTR_I2C2RST (1 << 22)
244#define RCC_APB1RSTR_I2C1RST (1 << 21)
245#define RCC_APB1RSTR_USART5RST (1 << 20)
246#define RCC_APB1RSTR_USART4RST (1 << 19)
247#define RCC_APB1RSTR_USART3RST (1 << 18)
248#define RCC_APB1RSTR_USART2RST (1 << 17)
249#define RCC_APB1RSTR_SPI2RST (1 << 14)
250#define RCC_APB1RSTR_WWDGRST (1 << 11)
251#define RCC_APB1RSTR_TIM14RST (1 << 8)
252#define RCC_APB1RSTR_TIM7RST (1 << 5)
253#define RCC_APB1RSTR_TIM6RST (1 << 4)
254#define RCC_APB1RSTR_TIM3RST (1 << 1)
255#define RCC_APB1RSTR_TIM2RST (1 << 0)
256/**@}*/
257
258/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values
259@{*/
260#define RCC_AHBENR_TSCEN (1 << 24)
261#define RCC_AHBENR_GPIOFEN (1 << 22)
262#define RCC_AHBENR_GPIOEEN (1 << 21)
263#define RCC_AHBENR_GPIODEN (1 << 20)
264#define RCC_AHBENR_GPIOCEN (1 << 19)
265#define RCC_AHBENR_GPIOBEN (1 << 18)
266#define RCC_AHBENR_GPIOAEN (1 << 17)
267#define RCC_AHBENR_CRCEN (1 << 6)
268#define RCC_AHBENR_FLTFEN (1 << 4)
269#define RCC_AHBENR_SRAMEN (1 << 2)
270#define RCC_AHBENR_DMA2EN (1 << 1)
271#define RCC_AHBENR_DMA1EN (1 << 0)
272#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1EN /* compatibility alias */
273/**@}*/
274
275/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values
276@{*/
277#define RCC_APB2ENR_DBGMCUEN (1 << 22)
278#define RCC_APB2ENR_TIM17EN (1 << 18)
279#define RCC_APB2ENR_TIM16EN (1 << 17)
280#define RCC_APB2ENR_TIM15EN (1 << 16)
281#define RCC_APB2ENR_USART1EN (1 << 14)
282#define RCC_APB2ENR_SPI1EN (1 << 12)
283#define RCC_APB2ENR_TIM1EN (1 << 11)
284#define RCC_APB2ENR_ADCEN (1 << 9)
285#define RCC_APB2ENR_USART8EN (1 << 7)
286#define RCC_APB2ENR_USART7EN (1 << 6)
287#define RCC_APB2ENR_USART6EN (1 << 5)
288#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0)
289/**@}*/
290
291/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
292@{*/
293#define RCC_APB1ENR_CECEN (1 << 30)
294#define RCC_APB1ENR_DACEN (1 << 29)
295#define RCC_APB1ENR_PWREN (1 << 28)
296#define RCC_APB1ENR_CRSEN (1 << 27)
297#define RCC_APB1ENR_CANEN (1 << 25)
298#define RCC_APB1ENR_USBEN (1 << 23)
299#define RCC_APB1ENR_I2C2EN (1 << 22)
300#define RCC_APB1ENR_I2C1EN (1 << 21)
301#define RCC_APB1ENR_USART5EN (1 << 20)
302#define RCC_APB1ENR_USART4EN (1 << 19)
303#define RCC_APB1ENR_USART3EN (1 << 18)
304#define RCC_APB1ENR_USART2EN (1 << 17)
305#define RCC_APB1ENR_SPI2EN (1 << 14)
306#define RCC_APB1ENR_WWDGEN (1 << 11)
307#define RCC_APB1ENR_TIM14EN (1 << 8)
308#define RCC_APB1ENR_TIM7EN (1 << 5)
309#define RCC_APB1ENR_TIM6EN (1 << 4)
310#define RCC_APB1ENR_TIM3EN (1 << 1)
311#define RCC_APB1ENR_TIM2EN (1 << 0)
312/**@}*/
313
314/* --- RCC_BDCR values ----------------------------------------------------- */
315
316#define RCC_BDCR_BDRST (1 << 16)
317#define RCC_BDCR_RTCEN (1 << 15)
318#define RCC_BDCR_RTCSEL_SHIFT 8
319#define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT)
320#define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT)
321#define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT)
322#define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT)
323#define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT)
324#define RCC_BDCR_LSEDRV_SHIFT 3
325#define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT)
326#define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT)
327#define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT)
328#define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT)
329#define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT)
330#define RCC_BDCR_LSEBYP (1 << 2)
331#define RCC_BDCR_LSERDY (1 << 1)
332#define RCC_BDCR_LSEON (1 << 0)
333
334/* --- RCC_CSR values ------------------------------------------------------ */
335
336#define RCC_CSR_LPWRRSTF (1 << 31)
337#define RCC_CSR_WWDGRSTF (1 << 30)
338#define RCC_CSR_IWDGRSTF (1 << 29)
339#define RCC_CSR_SFTRSTF (1 << 28)
340#define RCC_CSR_PORRSTF (1 << 27)
341#define RCC_CSR_PINRSTF (1 << 26)
342#define RCC_CSR_OBLRSTF (1 << 25)
343#define RCC_CSR_RMVF (1 << 24)
344#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
345 RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
346 RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF)
347#define RCC_CSR_V18PWRRSTF (1 << 23)
348#define RCC_CSR_LSIRDY (1 << 1)
349#define RCC_CSR_LSION (1 << 0)
350
351/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
352@{*/
353#define RCC_AHBRSTR_TSCRST (1 << 24)
354#define RCC_AHBRSTR_IOPFRST (1 << 22)
355#define RCC_AHBRSTR_IOPERST (1 << 21)
356#define RCC_AHBRSTR_IOPDRST (1 << 20)
357#define RCC_AHBRSTR_IOPCRST (1 << 19)
358#define RCC_AHBRSTR_IOPBRST (1 << 18)
359#define RCC_AHBRSTR_IOPARST (1 << 17)
360/**@}*/
361
362
363/* --- RCC_CFGR2 values ---------------------------------------------------- */
364
365#define RCC_CFGR2_PREDIV 0xf
366/** @defgroup rcc_cfgr2_prediv PLL source predividers
367@ingroup rcc_defines
368@{*/
369#define RCC_CFGR2_PREDIV_NODIV 0x0
370#define RCC_CFGR2_PREDIV_DIV2 0x1
371#define RCC_CFGR2_PREDIV_DIV3 0x2
372#define RCC_CFGR2_PREDIV_DIV4 0x3
373#define RCC_CFGR2_PREDIV_DIV5 0x4
374#define RCC_CFGR2_PREDIV_DIV6 0x5
375#define RCC_CFGR2_PREDIV_DIV7 0x6
376#define RCC_CFGR2_PREDIV_DIV8 0x7
377#define RCC_CFGR2_PREDIV_DIV9 0x8
378#define RCC_CFGR2_PREDIV_DIV10 0x9
379#define RCC_CFGR2_PREDIV_DIV11 0xa
380#define RCC_CFGR2_PREDIV_DIV12 0xb
381#define RCC_CFGR2_PREDIV_DIV13 0xc
382#define RCC_CFGR2_PREDIV_DIV14 0xd
383#define RCC_CFGR2_PREDIV_DIV15 0xe
384#define RCC_CFGR2_PREDIV_DIV16 0xf
385/**@}*/
386
387/* --- RCC_CFGR3 values ---------------------------------------------------- */
388#define RCC_CFGR3_USART3SW_SHIFT 18
389#define RCC_CFGR3_USART3SW (3 << RCC_CFGR3_USART2SW_SHIFT)
390#define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)
391#define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
392#define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)
393#define RCC_CFGR3_USART3SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)
394
395#define RCC_CFGR3_USART2SW_SHIFT 16
396#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT)
397#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)
398#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
399#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)
400#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)
401
402#define RCC_CFGR3_ADCSW (1 << 8)
403#define RCC_CFGR3_USBSW (1 << 7)
404#define RCC_CFGR3_CECSW (1 << 6)
405#define RCC_CFGR3_I2C1SW (1 << 4)
406
407#define RCC_CFGR3_USART1SW_SHIFT 0
408#define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT)
409#define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT)
410#define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT)
411#define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT)
412#define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT)
413
414#define RCC_CFGR3_USARTxSW_MASK 3
415
416/* --- RCC_CFGR3 values ---------------------------------------------------- */
417
418#define RCC_CR2_HSI48CAL_SHIFT 24
419#define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT)
420#define RCC_CR2_HSI48RDY (1 << 17)
421#define RCC_CR2_HSI48ON (1 << 16)
422#define RCC_CR2_HSI14CAL_SHIFT 8
423#define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT)
424#define RCC_CR2_HSI14TRIM_SHIFT 3
425#define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT)
426#define RCC_CR2_HSI14DIS (1 << 2)
427#define RCC_CR2_HSI14RDY (1 << 1)
428#define RCC_CR2_HSI14ON (1 << 0)
429
430/*****************************************************************************/
431/* API definitions */
432/*****************************************************************************/
433
434/* --- Variable definitions ------------------------------------------------ */
435extern uint32_t rcc_ahb_frequency;
436extern uint32_t rcc_apb1_frequency;
437/** F0 doens't _realllly_ have apb2, but it has a bunch of things
438 * enabled via the "APB2" enable register. Fake it out.
439 */
440#define rcc_apb2_frequency rcc_apb1_frequency
441
445
446#define _REG_BIT(base, bit) (((base) << 5) + (bit))
447
449 /* AHB peripherals */
450 RCC_DMA = _REG_BIT(0x14, 0),
451 RCC_DMA1 = _REG_BIT(0x14, 0), /* Compatibility alias */
452 RCC_DMA2 = _REG_BIT(0x14, 1),
453 RCC_SRAM = _REG_BIT(0x14, 2),
454 RCC_FLTIF = _REG_BIT(0x14, 4),
455 RCC_CRC = _REG_BIT(0x14, 6),
456 RCC_GPIOA = _REG_BIT(0x14, 17),
457 RCC_GPIOB = _REG_BIT(0x14, 18),
458 RCC_GPIOC = _REG_BIT(0x14, 19),
459 RCC_GPIOD = _REG_BIT(0x14, 20),
460 RCC_GPIOE = _REG_BIT(0x14, 21),
461 RCC_GPIOF = _REG_BIT(0x14, 22),
462 RCC_TSC = _REG_BIT(0x14, 24),
463
464 /* APB2 peripherals */
469 RCC_ADC = _REG_BIT(0x18, 9),
470 RCC_ADC1 = _REG_BIT(0x18, 9), /* Compatibility alias */
471 RCC_TIM1 = _REG_BIT(0x18, 11),
472 RCC_SPI1 = _REG_BIT(0x18, 12),
473 RCC_USART1 = _REG_BIT(0x18, 14),
474 RCC_TIM15 = _REG_BIT(0x18, 16),
475 RCC_TIM16 = _REG_BIT(0x18, 17),
476 RCC_TIM17 = _REG_BIT(0x18, 18),
477 RCC_DBGMCU = _REG_BIT(0x18, 22),
478
479 /* APB1 peripherals */
480 RCC_TIM2 = _REG_BIT(0x1C, 0),
481 RCC_TIM3 = _REG_BIT(0x1C, 1),
482 RCC_TIM6 = _REG_BIT(0x1C, 4),
483 RCC_TIM7 = _REG_BIT(0x1C, 5),
484 RCC_TIM14 = _REG_BIT(0x1C, 8),
485 RCC_WWDG = _REG_BIT(0x1C, 11),
486 RCC_SPI2 = _REG_BIT(0x1C, 14),
487 RCC_USART2 = _REG_BIT(0x1C, 17),
488 RCC_USART3 = _REG_BIT(0x1C, 18),
489 RCC_USART4 = _REG_BIT(0x1C, 19),
490 RCC_USART5 = _REG_BIT(0x1C, 20),
491 RCC_I2C1 = _REG_BIT(0x1C, 21),
492 RCC_I2C2 = _REG_BIT(0x1C, 22),
493 RCC_USB = _REG_BIT(0x1C, 23),
494 RCC_CAN = _REG_BIT(0x1C, 25),
495 RCC_CAN1 = _REG_BIT(0x1C, 25), /* Compatibility alias */
496 RCC_CRS = _REG_BIT(0x1C, 27),
497 RCC_PWR = _REG_BIT(0x1C, 28),
498 RCC_DAC = _REG_BIT(0x1C, 29),
499 RCC_DAC1 = _REG_BIT(0x1C, 29), /* Compatibility alias */
500 RCC_CEC = _REG_BIT(0x1C, 30),
501
502 /* Advanced peripherals */
503 RCC_RTC = _REG_BIT(0x20, 15),/* BDCR[15] */
504};
505
507 /* APB2 peripherals */
509 RST_ADC = _REG_BIT(0x0C, 9),
510 RST_ADC1 = _REG_BIT(0x0C, 9), /* Compatibility alias */
511 RST_TIM1 = _REG_BIT(0x0C, 11),
512 RST_SPI1 = _REG_BIT(0x0C, 12),
513 RST_USART1 = _REG_BIT(0x0C, 14),
514 RST_TIM15 = _REG_BIT(0x0C, 16),
515 RST_TIM16 = _REG_BIT(0x0C, 17),
516 RST_TIM17 = _REG_BIT(0x0C, 18),
517 RST_DBGMCU = _REG_BIT(0x0C, 22),
518
519 /* APB1 peripherals */
520 RST_TIM2 = _REG_BIT(0x10, 0),
521 RST_TIM3 = _REG_BIT(0x10, 1),
522 RST_TIM6 = _REG_BIT(0x10, 4),
523 RST_TIM7 = _REG_BIT(0x10, 5),
524 RST_TIM14 = _REG_BIT(0x10, 8),
525 RST_WWDG = _REG_BIT(0x10, 11),
526 RST_SPI2 = _REG_BIT(0x10, 14),
527 RST_USART2 = _REG_BIT(0x10, 17),
528 RST_USART3 = _REG_BIT(0x10, 18),
529 RST_USART4 = _REG_BIT(0x10, 19),
530 RST_I2C1 = _REG_BIT(0x10, 21),
531 RST_I2C2 = _REG_BIT(0x10, 22),
532 RST_USB = _REG_BIT(0x10, 23),
533 RST_CAN = _REG_BIT(0x10, 25),
534 RST_CAN1 = _REG_BIT(0x10, 25), /* Compatibility alias */
535 RST_CRS = _REG_BIT(0x10, 27),
536 RST_PWR = _REG_BIT(0x10, 28),
537 RST_DAC = _REG_BIT(0x10, 29),
538 RST_DAC1 = _REG_BIT(0x10, 29), /* Compatibility alias */
539 RST_CEC = _REG_BIT(0x10, 30),
540
541 /* Backup domain control */
542 RST_BDCR = _REG_BIT(0x20, 16),/* BDCR[16] */
543
544 /* AHB peripherals */
545 RST_GPIOA = _REG_BIT(0x28, 17),
546 RST_GPIOB = _REG_BIT(0x28, 18),
547 RST_GPIOC = _REG_BIT(0x28, 19),
548 RST_GPIOD = _REG_BIT(0x28, 20),
549 RST_GPIOE = _REG_BIT(0x28, 21),
550 RST_GPIOF = _REG_BIT(0x28, 22),
551 RST_TSC = _REG_BIT(0x28, 24),
552};
553#undef _REG_BIT
554
555/*****************************************************************************/
556/* API Functions */
557/*****************************************************************************/
558
560
562
563void rcc_osc_ready_int_clear(enum rcc_osc osc);
564void rcc_osc_ready_int_enable(enum rcc_osc osc);
566int rcc_osc_ready_int_flag(enum rcc_osc osc);
567void rcc_osc_on(enum rcc_osc osc);
568void rcc_osc_off(enum rcc_osc osc);
569void rcc_css_enable(void);
570void rcc_css_disable(void);
571void rcc_css_int_clear(void);
572int rcc_css_int_flag(void);
573void rcc_set_sysclk_source(enum rcc_osc clk);
574void rcc_set_usbclk_source(enum rcc_osc clk);
575void rcc_set_rtc_clock_source(enum rcc_osc clk);
576void rcc_enable_rtc_clock(void);
577void rcc_disable_rtc_clock(void);
578void rcc_set_pll_multiplication_factor(uint32_t mul);
579void rcc_set_pll_source(uint32_t pllsrc);
580void rcc_set_pllxtpre(uint32_t pllxtpre);
581void rcc_set_ppre(uint32_t ppre);
582void rcc_set_hpre(uint32_t hpre);
583void rcc_set_prediv(uint32_t prediv);
585void rcc_set_i2c_clock_hsi(uint32_t i2c);
586void rcc_set_i2c_clock_sysclk(uint32_t i2c);
587uint32_t rcc_get_i2c_clocks(void);
592uint32_t rcc_get_usart_clk_freq(uint32_t usart);
593uint32_t rcc_get_timer_clk_freq(uint32_t timer);
594uint32_t rcc_get_i2c_clk_freq(uint32_t i2c);
595uint32_t rcc_get_spi_clk_freq(uint32_t spi);
596
598
599#endif
600/**@}*/
601
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
int rcc_osc_ready_int_flag(enum rcc_osc osc)
RCC Read the Oscillator Ready Interrupt Flag.
Definition: rcc.c:157
void rcc_set_ppre(uint32_t ppre)
RCC Set the APB Prescale Factor.
Definition: rcc.c:473
void rcc_set_sysclk_source(enum rcc_osc clk)
RCC Set the Source for the System Clock.
Definition: rcc.c:334
int rcc_css_int_flag(void)
RCC Read the Clock Security System Interrupt Flag.
Definition: rcc.c:201
void rcc_set_i2c_clock_sysclk(uint32_t i2c)
Definition: rcc.c:531
void rcc_osc_ready_int_clear(enum rcc_osc osc)
RCC Clear the Oscillator Ready Interrupt Flag.
Definition: rcc.c:57
void rcc_css_disable(void)
RCC Disable the Clock Security System.
Definition: rcc.c:322
enum rcc_osc rcc_system_clock_source(void)
RCC Get the System Clock Source.
Definition: rcc.c:507
uint32_t rcc_get_spi_clk_freq(uint32_t spi)
Get the peripheral clock speed for the SPI device at base specified.
Definition: rcc.c:693
void rcc_set_pll_source(uint32_t pllsrc)
RCC Set the PLL Clock Source.
Definition: rcc.c:447
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
Get the peripheral clock speed for the Timer at base specified.
Definition: rcc.c:664
enum rcc_osc rcc_usb_clock_source(void)
RCC Get the USB Clock Source.
Definition: rcc.c:549
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
Get the peripheral clock speed for the USART at base specified.
Definition: rcc.c:647
rcc_periph_rst
Definition: f0/rcc.h:506
void rcc_set_usbclk_source(enum rcc_osc clk)
RCC Set the Source for the USB Clock.
Definition: rcc.c:363
rcc_periph_clken
Definition: f0/rcc.h:448
void rcc_set_prediv(uint32_t prediv)
Set PLL Source pre-divider CAUTION.
Definition: rcc.c:495
void rcc_osc_ready_int_enable(enum rcc_osc osc)
RCC Enable the Oscillator Ready Interrupt.
Definition: rcc.c:90
void rcc_set_rtc_clock_source(enum rcc_osc clk)
RCC Set the Source for the RTC clock.
Definition: rcc.c:408
rcc_osc
Definition: f0/rcc.h:442
void rcc_clock_setup_in_hse_8mhz_out_48mhz(void)
Set System Clock PLL at 48MHz from HSE at 8MHz.
Definition: rcc.c:557
void rcc_disable_rtc_clock(void)
RCC Disable the RTC clock.
Definition: rcc.c:397
void rcc_osc_ready_int_disable(enum rcc_osc osc)
RCC Disable the Oscillator Ready Interrupt.
Definition: rcc.c:123
void rcc_osc_on(enum rcc_osc osc)
RCC Turn on an Oscillator.
Definition: rcc.c:244
#define _REG_BIT(base, bit)
Definition: f0/rcc.h:446
uint32_t rcc_ahb_frequency
Definition: rcc.c:45
void rcc_osc_off(enum rcc_osc osc)
RCC Turn off an Oscillator.
Definition: rcc.c:282
void rcc_clock_setup_in_hsi48_out_48mhz(void)
Set System Clock HSI48 at 48MHz.
Definition: rcc.c:612
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
Get the peripheral clock speed for the I2C device at base specified.
Definition: rcc.c:675
void rcc_set_pll_multiplication_factor(uint32_t mul)
RCC Set the PLL Multiplication Factor.
Definition: rcc.c:434
uint32_t rcc_apb1_frequency
Definition: rcc.c:46
uint32_t rcc_get_i2c_clocks(void)
Definition: rcc.c:538
void rcc_css_int_clear(void)
RCC Clear the Clock Security System Interrupt Flag.
Definition: rcc.c:190
void rcc_enable_rtc_clock(void)
RCC Enable the RTC clock.
Definition: rcc.c:387
void rcc_set_i2c_clock_hsi(uint32_t i2c)
Definition: rcc.c:524
void rcc_clock_setup_in_hsi_out_48mhz(void)
Set System Clock PLL at 48MHz from HSI.
Definition: rcc.c:585
void rcc_css_enable(void)
RCC Enable the Clock Security System.
Definition: rcc.c:313
void rcc_set_hpre(uint32_t hpre)
RCC Set the AHB Prescale Factor.
Definition: rcc.c:484
void rcc_set_pllxtpre(uint32_t pllxtpre)
RCC Set the HSE Frequency Divider used as PLL Clock Source.
Definition: rcc.c:461
@ RST_CRS
Definition: f0/rcc.h:535
@ RST_SPI1
Definition: f0/rcc.h:512
@ RST_CEC
Definition: f0/rcc.h:539
@ RST_ADC1
Definition: f0/rcc.h:510
@ RST_TIM16
Definition: f0/rcc.h:515
@ RST_TSC
Definition: f0/rcc.h:551
@ RST_TIM14
Definition: f0/rcc.h:524
@ RST_GPIOF
Definition: f0/rcc.h:550
@ RST_DBGMCU
Definition: f0/rcc.h:517
@ RST_BDCR
Definition: f0/rcc.h:542
@ RST_SPI2
Definition: f0/rcc.h:526
@ RST_TIM15
Definition: f0/rcc.h:514
@ RST_TIM3
Definition: f0/rcc.h:521
@ RST_TIM17
Definition: f0/rcc.h:516
@ RST_GPIOA
Definition: f0/rcc.h:545
@ RST_GPIOC
Definition: f0/rcc.h:547
@ RST_TIM6
Definition: f0/rcc.h:522
@ RST_GPIOB
Definition: f0/rcc.h:546
@ RST_TIM1
Definition: f0/rcc.h:511
@ RST_USART3
Definition: f0/rcc.h:528
@ RST_DAC
Definition: f0/rcc.h:537
@ RST_ADC
Definition: f0/rcc.h:509
@ RST_TIM7
Definition: f0/rcc.h:523
@ RST_TIM2
Definition: f0/rcc.h:520
@ RST_GPIOD
Definition: f0/rcc.h:548
@ RST_USB
Definition: f0/rcc.h:532
@ RST_CAN
Definition: f0/rcc.h:533
@ RST_USART4
Definition: f0/rcc.h:529
@ RST_SYSCFG
Definition: f0/rcc.h:508
@ RST_GPIOE
Definition: f0/rcc.h:549
@ RST_I2C2
Definition: f0/rcc.h:531
@ RST_CAN1
Definition: f0/rcc.h:534
@ RST_PWR
Definition: f0/rcc.h:536
@ RST_USART1
Definition: f0/rcc.h:513
@ RST_WWDG
Definition: f0/rcc.h:525
@ RST_I2C1
Definition: f0/rcc.h:530
@ RST_DAC1
Definition: f0/rcc.h:538
@ RST_USART2
Definition: f0/rcc.h:527
@ RCC_CRS
Definition: f0/rcc.h:496
@ RCC_CAN
Definition: f0/rcc.h:494
@ RCC_SPI2
Definition: f0/rcc.h:486
@ RCC_WWDG
Definition: f0/rcc.h:485
@ RCC_TIM3
Definition: f0/rcc.h:481
@ RCC_TIM1
Definition: f0/rcc.h:471
@ RCC_SYSCFG_COMP
Definition: f0/rcc.h:465
@ RCC_USART5
Definition: f0/rcc.h:490
@ RCC_GPIOA
Definition: f0/rcc.h:456
@ RCC_CEC
Definition: f0/rcc.h:500
@ RCC_DMA
Definition: f0/rcc.h:450
@ RCC_TIM17
Definition: f0/rcc.h:476
@ RCC_RTC
Definition: f0/rcc.h:503
@ RCC_TIM2
Definition: f0/rcc.h:480
@ RCC_CAN1
Definition: f0/rcc.h:495
@ RCC_PWR
Definition: f0/rcc.h:497
@ RCC_CRC
Definition: f0/rcc.h:455
@ RCC_TIM14
Definition: f0/rcc.h:484
@ RCC_USART1
Definition: f0/rcc.h:473
@ RCC_DAC1
Definition: f0/rcc.h:499
@ RCC_I2C1
Definition: f0/rcc.h:491
@ RCC_USART7
Definition: f0/rcc.h:467
@ RCC_USART4
Definition: f0/rcc.h:489
@ RCC_SRAM
Definition: f0/rcc.h:453
@ RCC_ADC1
Definition: f0/rcc.h:470
@ RCC_TSC
Definition: f0/rcc.h:462
@ RCC_DBGMCU
Definition: f0/rcc.h:477
@ RCC_USB
Definition: f0/rcc.h:493
@ RCC_USART2
Definition: f0/rcc.h:487
@ RCC_TIM16
Definition: f0/rcc.h:475
@ RCC_USART3
Definition: f0/rcc.h:488
@ RCC_SPI1
Definition: f0/rcc.h:472
@ RCC_USART8
Definition: f0/rcc.h:468
@ RCC_I2C2
Definition: f0/rcc.h:492
@ RCC_GPIOB
Definition: f0/rcc.h:457
@ RCC_TIM7
Definition: f0/rcc.h:483
@ RCC_FLTIF
Definition: f0/rcc.h:454
@ RCC_GPIOF
Definition: f0/rcc.h:461
@ RCC_GPIOC
Definition: f0/rcc.h:458
@ RCC_TIM6
Definition: f0/rcc.h:482
@ RCC_DMA1
Definition: f0/rcc.h:451
@ RCC_DAC
Definition: f0/rcc.h:498
@ RCC_GPIOD
Definition: f0/rcc.h:459
@ RCC_TIM15
Definition: f0/rcc.h:474
@ RCC_GPIOE
Definition: f0/rcc.h:460
@ RCC_ADC
Definition: f0/rcc.h:469
@ RCC_USART6
Definition: f0/rcc.h:466
@ RCC_DMA2
Definition: f0/rcc.h:452
@ RCC_HSI
Definition: f0/rcc.h:443
@ RCC_HSI48
Definition: f0/rcc.h:443
@ RCC_LSI
Definition: f0/rcc.h:443
@ RCC_PLL
Definition: f0/rcc.h:443
@ RCC_LSE
Definition: f0/rcc.h:443
@ RCC_HSE
Definition: f0/rcc.h:443
@ RCC_HSI14
Definition: f0/rcc.h:443