Defined Constants and Types for the STM32F0xx Reset and Clock Control More...
Enumerations | |
| enum | rcc_osc { RCC_HSI14 , RCC_HSI , RCC_HSE , RCC_PLL , RCC_LSI , RCC_LSE , RCC_HSI48 } |
| enum | rcc_periph_clken { RCC_DMA = _REG_BIT(0x14, 0) , RCC_DMA1 = _REG_BIT(0x14, 0) , RCC_DMA2 = _REG_BIT(0x14, 1) , RCC_SRAM = _REG_BIT(0x14, 2) , RCC_FLTIF = _REG_BIT(0x14, 4) , RCC_CRC = _REG_BIT(0x14, 6) , RCC_GPIOA = _REG_BIT(0x14, 17) , RCC_GPIOB = _REG_BIT(0x14, 18) , RCC_GPIOC = _REG_BIT(0x14, 19) , RCC_GPIOD = _REG_BIT(0x14, 20) , RCC_GPIOE = _REG_BIT(0x14, 21) , RCC_GPIOF = _REG_BIT(0x14, 22) , RCC_TSC = _REG_BIT(0x14, 24) , RCC_SYSCFG_COMP = _REG_BIT(0x18, 0) , RCC_USART6 = _REG_BIT(0x18, 5) , RCC_USART7 = _REG_BIT(0x18, 6) , RCC_USART8 = _REG_BIT(0x18, 7) , RCC_ADC = _REG_BIT(0x18, 9) , RCC_ADC1 = _REG_BIT(0x18, 9) , RCC_TIM1 = _REG_BIT(0x18, 11) , RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_USART1 = _REG_BIT(0x18, 14) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) , RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_DBGMCU = _REG_BIT(0x18, 22) , RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) , RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM7 = _REG_BIT(0x1C, 5) , RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_WWDG = _REG_BIT(0x1C, 11) , RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_USART3 = _REG_BIT(0x1C, 18) , RCC_USART4 = _REG_BIT(0x1C, 19) , RCC_USART5 = _REG_BIT(0x1C, 20) , RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) , RCC_CAN = _REG_BIT(0x1C, 25) , RCC_CAN1 = _REG_BIT(0x1C, 25) , RCC_CRS = _REG_BIT(0x1C, 27) , RCC_PWR = _REG_BIT(0x1C, 28) , RCC_DAC = _REG_BIT(0x1C, 29) , RCC_DAC1 = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30) , RCC_RTC = _REG_BIT(0x20, 15) } |
| enum | rcc_periph_rst { RST_SYSCFG = _REG_BIT(0x0C, 0) , RST_ADC = _REG_BIT(0x0C, 9) , RST_ADC1 = _REG_BIT(0x0C, 9) , RST_TIM1 = _REG_BIT(0x0C, 11) , RST_SPI1 = _REG_BIT(0x0C, 12) , RST_USART1 = _REG_BIT(0x0C, 14) , RST_TIM15 = _REG_BIT(0x0C, 16) , RST_TIM16 = _REG_BIT(0x0C, 17) , RST_TIM17 = _REG_BIT(0x0C, 18) , RST_DBGMCU = _REG_BIT(0x0C, 22) , RST_TIM2 = _REG_BIT(0x10, 0) , RST_TIM3 = _REG_BIT(0x10, 1) , RST_TIM6 = _REG_BIT(0x10, 4) , RST_TIM7 = _REG_BIT(0x10, 5) , RST_TIM14 = _REG_BIT(0x10, 8) , RST_WWDG = _REG_BIT(0x10, 11) , RST_SPI2 = _REG_BIT(0x10, 14) , RST_USART2 = _REG_BIT(0x10, 17) , RST_USART3 = _REG_BIT(0x10, 18) , RST_USART4 = _REG_BIT(0x10, 19) , RST_I2C1 = _REG_BIT(0x10, 21) , RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_CAN = _REG_BIT(0x10, 25) , RST_CAN1 = _REG_BIT(0x10, 25) , RST_CRS = _REG_BIT(0x10, 27) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC = _REG_BIT(0x10, 29) , RST_DAC1 = _REG_BIT(0x10, 29) , RST_CEC = _REG_BIT(0x10, 30) , RST_BDCR = _REG_BIT(0x20, 16) , RST_GPIOA = _REG_BIT(0x28, 17) , RST_GPIOB = _REG_BIT(0x28, 18) , RST_GPIOC = _REG_BIT(0x28, 19) , RST_GPIOD = _REG_BIT(0x28, 20) , RST_GPIOE = _REG_BIT(0x28, 21) , RST_GPIOF = _REG_BIT(0x28, 22) , RST_TSC = _REG_BIT(0x28, 24) } |
Functions | |
| void | rcc_osc_ready_int_clear (enum rcc_osc osc) |
| RCC Clear the Oscillator Ready Interrupt Flag. More... | |
| void | rcc_osc_ready_int_enable (enum rcc_osc osc) |
| RCC Enable the Oscillator Ready Interrupt. More... | |
| void | rcc_osc_ready_int_disable (enum rcc_osc osc) |
| RCC Disable the Oscillator Ready Interrupt. More... | |
| int | rcc_osc_ready_int_flag (enum rcc_osc osc) |
| RCC Read the Oscillator Ready Interrupt Flag. More... | |
| void | rcc_osc_on (enum rcc_osc osc) |
| RCC Turn on an Oscillator. More... | |
| void | rcc_osc_off (enum rcc_osc osc) |
| RCC Turn off an Oscillator. More... | |
| void | rcc_css_enable (void) |
| RCC Enable the Clock Security System. More... | |
| void | rcc_css_disable (void) |
| RCC Disable the Clock Security System. More... | |
| void | rcc_css_int_clear (void) |
| RCC Clear the Clock Security System Interrupt Flag. More... | |
| int | rcc_css_int_flag (void) |
| RCC Read the Clock Security System Interrupt Flag. More... | |
| void | rcc_set_sysclk_source (enum rcc_osc clk) |
| RCC Set the Source for the System Clock. More... | |
| void | rcc_set_usbclk_source (enum rcc_osc clk) |
| RCC Set the Source for the USB Clock. More... | |
| void | rcc_set_rtc_clock_source (enum rcc_osc clk) |
| RCC Set the Source for the RTC clock. More... | |
| void | rcc_enable_rtc_clock (void) |
| RCC Enable the RTC clock. More... | |
| void | rcc_disable_rtc_clock (void) |
| RCC Disable the RTC clock. More... | |
| void | rcc_set_pll_multiplication_factor (uint32_t mul) |
| RCC Set the PLL Multiplication Factor. More... | |
| void | rcc_set_pll_source (uint32_t pllsrc) |
| RCC Set the PLL Clock Source. More... | |
| void | rcc_set_pllxtpre (uint32_t pllxtpre) |
| RCC Set the HSE Frequency Divider used as PLL Clock Source. More... | |
| void | rcc_set_ppre (uint32_t ppre) |
| RCC Set the APB Prescale Factor. More... | |
| void | rcc_set_hpre (uint32_t hpre) |
| RCC Set the AHB Prescale Factor. More... | |
| void | rcc_set_prediv (uint32_t prediv) |
| Set PLL Source pre-divider CAUTION. More... | |
| enum rcc_osc | rcc_system_clock_source (void) |
| RCC Get the System Clock Source. More... | |
| void | rcc_set_i2c_clock_hsi (uint32_t i2c) |
| void | rcc_set_i2c_clock_sysclk (uint32_t i2c) |
| uint32_t | rcc_get_i2c_clocks (void) |
| enum rcc_osc | rcc_usb_clock_source (void) |
| RCC Get the USB Clock Source. More... | |
| void | rcc_clock_setup_in_hse_8mhz_out_48mhz (void) |
| Set System Clock PLL at 48MHz from HSE at 8MHz. More... | |
| void | rcc_clock_setup_in_hsi_out_48mhz (void) |
| Set System Clock PLL at 48MHz from HSI. More... | |
| void | rcc_clock_setup_in_hsi48_out_48mhz (void) |
| Set System Clock HSI48 at 48MHz. More... | |
| uint32_t | rcc_get_usart_clk_freq (uint32_t usart) |
| Get the peripheral clock speed for the USART at base specified. More... | |
| uint32_t | rcc_get_timer_clk_freq (uint32_t timer) |
| Get the peripheral clock speed for the Timer at base specified. More... | |
| uint32_t | rcc_get_i2c_clk_freq (uint32_t i2c) |
| Get the peripheral clock speed for the I2C device at base specified. More... | |
| uint32_t | rcc_get_spi_clk_freq (uint32_t spi) |
| Get the peripheral clock speed for the SPI device at base specified. More... | |
| void | rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en) |
| RCC Enable Peripheral Clocks. More... | |
| void | rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en) |
| RCC Disable Peripheral Clocks. More... | |
| void | rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset) |
| RCC Reset Peripherals. More... | |
| void | rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset) |
| RCC Remove Reset on Peripherals. More... | |
| void | rcc_periph_clock_enable (enum rcc_periph_clken clken) |
| Enable Peripheral Clock in running mode. More... | |
| void | rcc_periph_clock_disable (enum rcc_periph_clken clken) |
| Disable Peripheral Clock in running mode. More... | |
| void | rcc_periph_reset_pulse (enum rcc_periph_rst rst) |
| Reset Peripheral, pulsed. More... | |
| void | rcc_periph_reset_hold (enum rcc_periph_rst rst) |
| Reset Peripheral, hold. More... | |
| void | rcc_periph_reset_release (enum rcc_periph_rst rst) |
| Reset Peripheral, release. More... | |
| void | rcc_set_mco (uint32_t mcosrc) |
| Select the source of Microcontroller Clock Output. More... | |
| void | rcc_osc_bypass_enable (enum rcc_osc osc) |
| RCC Enable Bypass. More... | |
| void | rcc_osc_bypass_disable (enum rcc_osc osc) |
| RCC Disable Bypass. More... | |
| bool | rcc_is_osc_ready (enum rcc_osc osc) |
| Is the given oscillator ready? More... | |
| void | rcc_wait_for_osc_ready (enum rcc_osc osc) |
| Wait for Oscillator Ready. More... | |
| uint16_t | rcc_get_div_from_hpre (uint8_t div_val) |
| This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More... | |
Variables | |
| uint32_t | rcc_ahb_frequency |
| uint32_t | rcc_apb1_frequency |
Detailed Description
Defined Constants and Types for the STM32F0xx Reset and Clock Control
- Version
- 1.0.0
- Date
- 29 Jun 2013
LGPL License Terms libopencm3 License
Macro Definition Documentation
◆ _REG_BIT
◆ RCC_AHBENR
◆ RCC_AHBRSTR
◆ RCC_APB1ENR
◆ RCC_APB1RSTR
◆ rcc_apb2_frequency
| #define rcc_apb2_frequency rcc_apb1_frequency |
◆ RCC_APB2ENR
◆ RCC_APB2RSTR
◆ RCC_BDCR
◆ RCC_BDCR_BDRST
◆ RCC_BDCR_LSEBYP
◆ RCC_BDCR_LSEDRV
| #define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT) |
◆ RCC_BDCR_LSEDRV_HIGH
| #define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) |
◆ RCC_BDCR_LSEDRV_LOW
| #define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) |
◆ RCC_BDCR_LSEDRV_MEDHI
| #define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) |
◆ RCC_BDCR_LSEDRV_MEDLO
| #define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) |
◆ RCC_BDCR_LSEDRV_SHIFT
◆ RCC_BDCR_LSEON
◆ RCC_BDCR_LSERDY
◆ RCC_BDCR_RTCEN
◆ RCC_BDCR_RTCSEL
| #define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT) |
◆ RCC_BDCR_RTCSEL_HSE
| #define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) |
◆ RCC_BDCR_RTCSEL_LSE
| #define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) |
◆ RCC_BDCR_RTCSEL_LSI
| #define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) |
◆ RCC_BDCR_RTCSEL_NOCLK
| #define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) |
◆ RCC_BDCR_RTCSEL_SHIFT
◆ RCC_CFGR
◆ RCC_CFGR2
◆ RCC_CFGR2_PREDIV
◆ RCC_CFGR3
◆ RCC_CFGR3_ADCSW
◆ RCC_CFGR3_CECSW
◆ RCC_CFGR3_I2C1SW
◆ RCC_CFGR3_USARTxSW_MASK
◆ RCC_CFGR3_USBSW
◆ RCC_CFGR_ADCPRE
◆ RCC_CFGR_HPRE
| #define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT) |
◆ RCC_CFGR_HPRE_MASK
◆ RCC_CFGR_HPRE_SHIFT
◆ RCC_CFGR_MCO_HSE
◆ RCC_CFGR_MCO_HSI
◆ RCC_CFGR_MCO_HSI14
◆ RCC_CFGR_MCO_HSI48
◆ RCC_CFGR_MCO_LSE
◆ RCC_CFGR_MCO_LSI
◆ RCC_CFGR_MCO_MASK
◆ RCC_CFGR_MCO_NOCLK
◆ RCC_CFGR_MCO_PLL
◆ RCC_CFGR_MCO_SHIFT
◆ RCC_CFGR_MCO_SYSCLK
◆ RCC_CFGR_MCOPRE
| #define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV1
| #define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV128
| #define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV16
| #define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV2
| #define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV32
| #define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV4
| #define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV64
| #define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_DIV8
| #define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) |
◆ RCC_CFGR_MCOPRE_SHIFT
◆ RCC_CFGR_PLLMUL
| #define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) |
◆ RCC_CFGR_PLLMUL_SHIFT
◆ RCC_CFGR_PLLNODIV
◆ RCC_CFGR_PLLSRC
◆ RCC_CFGR_PLLSRC0
◆ RCC_CFGR_PLLXTPRE
◆ RCC_CFGR_PPRE
| #define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) |
◆ RCC_CFGR_PPRE_MASK
◆ RCC_CFGR_PPRE_SHIFT
◆ RCC_CFGR_SW
| #define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) |
◆ RCC_CFGR_SW_HSE
| #define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) |
◆ RCC_CFGR_SW_HSI
| #define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) |
◆ RCC_CFGR_SW_HSI48
| #define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) |
◆ RCC_CFGR_SW_PLL
| #define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) |
◆ RCC_CFGR_SW_SHIFT
◆ RCC_CFGR_SWS
| #define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) |
◆ RCC_CFGR_SWS_HSE
| #define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) |
◆ RCC_CFGR_SWS_HSI
| #define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) |
◆ RCC_CFGR_SWS_HSI48
| #define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) |
◆ RCC_CFGR_SWS_PLL
| #define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) |
◆ RCC_CFGR_SWS_SHIFT
◆ RCC_CIR
◆ RCC_CIR_CSSC
◆ RCC_CIR_CSSF
◆ RCC_CIR_HSERDYC
◆ RCC_CIR_HSERDYF
◆ RCC_CIR_HSERDYIE
◆ RCC_CIR_HSI14RDYC
◆ RCC_CIR_HSI14RDYF
◆ RCC_CIR_HSI14RDYIE
◆ RCC_CIR_HSI48RDYC
◆ RCC_CIR_HSI48RDYF
◆ RCC_CIR_HSI48RDYIE
◆ RCC_CIR_HSIRDYC
◆ RCC_CIR_HSIRDYF
◆ RCC_CIR_HSIRDYIE
◆ RCC_CIR_LSERDYC
◆ RCC_CIR_LSERDYF
◆ RCC_CIR_LSERDYIE
◆ RCC_CIR_LSIRDYC
◆ RCC_CIR_LSIRDYF
◆ RCC_CIR_LSIRDYIE
◆ RCC_CIR_PLLRDYC
◆ RCC_CIR_PLLRDYF
◆ RCC_CIR_PLLRDYIE
◆ RCC_CR
◆ RCC_CR2
◆ RCC_CR2_HSI14CAL
| #define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT) |
◆ RCC_CR2_HSI14CAL_SHIFT
◆ RCC_CR2_HSI14DIS
◆ RCC_CR2_HSI14ON
◆ RCC_CR2_HSI14RDY
◆ RCC_CR2_HSI14TRIM
| #define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT) |
◆ RCC_CR2_HSI14TRIM_SHIFT
◆ RCC_CR2_HSI48CAL
| #define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT) |
◆ RCC_CR2_HSI48CAL_SHIFT
◆ RCC_CR2_HSI48ON
◆ RCC_CR2_HSI48RDY
◆ RCC_CR_CSSON
◆ RCC_CR_HSEBYP
◆ RCC_CR_HSEON
◆ RCC_CR_HSERDY
◆ RCC_CR_HSICAL
| #define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT) |
◆ RCC_CR_HSICAL_SHIFT
◆ RCC_CR_HSION
◆ RCC_CR_HSIRDY
◆ RCC_CR_HSITRIM
| #define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT) |
◆ RCC_CR_HSITRIM_SHIFT
◆ RCC_CR_PLLON
◆ RCC_CR_PLLRDY
◆ RCC_CSR
◆ RCC_CSR_IWDGRSTF
◆ RCC_CSR_LPWRRSTF
◆ RCC_CSR_LSION
◆ RCC_CSR_LSIRDY
◆ RCC_CSR_OBLRSTF
◆ RCC_CSR_PINRSTF
◆ RCC_CSR_PORRSTF
◆ RCC_CSR_RESET_FLAGS
| #define RCC_CSR_RESET_FLAGS |
◆ RCC_CSR_RMVF
◆ RCC_CSR_SFTRSTF
◆ RCC_CSR_V18PWRRSTF
◆ RCC_CSR_WWDGRSTF
Enumeration Type Documentation
◆ rcc_osc
| enum rcc_osc |
◆ rcc_periph_clken
| enum rcc_periph_clken |
◆ rcc_periph_rst
| enum rcc_periph_rst |
Function Documentation
◆ rcc_clock_setup_in_hse_8mhz_out_48mhz()
| void rcc_clock_setup_in_hse_8mhz_out_48mhz | ( | void | ) |
Set System Clock PLL at 48MHz from HSE at 8MHz.
Definition at line 557 of file rcc.c.
References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PLLMUL_MUL6, RCC_CFGR_PLLSRC_HSE_CLK, RCC_CFGR_PLLXTPRE_HSE_CLK, RCC_CFGR_PPRE_NODIV, RCC_HSE, rcc_osc_on(), RCC_PLL, rcc_set_hpre(), rcc_set_pll_multiplication_factor(), rcc_set_pll_source(), rcc_set_pllxtpre(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().
◆ rcc_clock_setup_in_hsi48_out_48mhz()
| void rcc_clock_setup_in_hsi48_out_48mhz | ( | void | ) |
Set System Clock HSI48 at 48MHz.
Definition at line 612 of file rcc.c.
References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PPRE_NODIV, RCC_HSI48, rcc_osc_on(), rcc_set_hpre(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().
◆ rcc_clock_setup_in_hsi_out_48mhz()
| void rcc_clock_setup_in_hsi_out_48mhz | ( | void | ) |
Set System Clock PLL at 48MHz from HSI.
Definition at line 585 of file rcc.c.
References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PLLMUL_MUL12, RCC_CFGR_PLLSRC_HSI_CLK_DIV2, RCC_CFGR_PPRE_NODIV, RCC_HSI, rcc_osc_on(), RCC_PLL, rcc_set_hpre(), rcc_set_pll_multiplication_factor(), rcc_set_pll_source(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().
◆ rcc_css_disable()
| void rcc_css_disable | ( | void | ) |
◆ rcc_css_enable()
| void rcc_css_enable | ( | void | ) |
RCC Enable the Clock Security System.
Definition at line 313 of file rcc.c.
References RCC_CR, and RCC_CR_CSSON.
◆ rcc_css_int_clear()
| void rcc_css_int_clear | ( | void | ) |
RCC Clear the Clock Security System Interrupt Flag.
Definition at line 190 of file rcc.c.
References RCC_CIR, and RCC_CIR_CSSC.
◆ rcc_css_int_flag()
| int rcc_css_int_flag | ( | void | ) |
RCC Read the Clock Security System Interrupt Flag.
- Returns
- int. Boolean value for flag set.
Definition at line 201 of file rcc.c.
References RCC_CIR, and RCC_CIR_CSSF.
◆ rcc_disable_rtc_clock()
| void rcc_disable_rtc_clock | ( | void | ) |
◆ rcc_enable_rtc_clock()
| void rcc_enable_rtc_clock | ( | void | ) |
RCC Enable the RTC clock.
Definition at line 387 of file rcc.c.
References RCC_BDCR, and RCC_BDCR_RTCEN.
◆ rcc_get_div_from_hpre()
| uint16_t rcc_get_div_from_hpre | ( | uint8_t | div_val | ) |
This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.
- Parameters
-
div_val Masked and shifted divider value from register (e.g. RCC_CFGR)
Definition at line 260 of file rcc_common_all.c.
Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clksel_freq().
◆ rcc_get_i2c_clk_freq()
| uint32_t rcc_get_i2c_clk_freq | ( | uint32_t | i2c | ) |
Get the peripheral clock speed for the I2C device at base specified.
- Parameters
-
i2c Base address of I2C to get clock frequency for.
Definition at line 677 of file rcc.c.
References I2C1_BASE, rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR, RCC_CFGR3, RCC_CFGR3_I2C1SW, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().
◆ rcc_get_i2c_clocks()
| uint32_t rcc_get_i2c_clocks | ( | void | ) |
Definition at line 538 of file rcc.c.
References RCC_CFGR3, and RCC_CFGR3_I2C1SW.
◆ rcc_get_spi_clk_freq()
| uint32_t rcc_get_spi_clk_freq | ( | uint32_t | spi | ) |
Get the peripheral clock speed for the SPI device at base specified.
- Parameters
-
spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
Definition at line 695 of file rcc.c.
References rcc_apb1_frequency.
◆ rcc_get_timer_clk_freq()
| uint32_t rcc_get_timer_clk_freq | ( | uint32_t | timer | ) |
Get the peripheral clock speed for the Timer at base specified.
- Parameters
-
timer Base address of TIM to get clock frequency for.
Definition at line 666 of file rcc.c.
References rcc_apb1_frequency, RCC_CFGR, RCC_CFGR_PPRE_MASK, RCC_CFGR_PPRE_NODIV, and RCC_CFGR_PPRE_SHIFT.
◆ rcc_get_usart_clk_freq()
| uint32_t rcc_get_usart_clk_freq | ( | uint32_t | usart | ) |
Get the peripheral clock speed for the USART at base specified.
- Parameters
-
usart Base address of USART to get clock frequency for.
Definition at line 649 of file rcc.c.
References rcc_apb1_frequency, RCC_CFGR3_USART1SW_SHIFT, RCC_CFGR3_USART2SW_SHIFT, RCC_CFGR3_USART3SW_SHIFT, rcc_get_usart_clksel_freq(), USART1_BASE, USART2_BASE, and USART3_BASE.
Referenced by usart_set_baudrate().
◆ rcc_is_osc_ready()
| bool rcc_is_osc_ready | ( | enum rcc_osc | osc | ) |
Is the given oscillator ready?
- Parameters
-
osc Oscillator ID
- Returns
- true if the hardware indicates the oscillator is ready.
Definition at line 206 of file rcc.c.
References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR2, RCC_CR2_HSI14RDY, RCC_CR2_HSI48RDY, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_wait_for_osc_ready().
◆ rcc_osc_bypass_disable()
| void rcc_osc_bypass_disable | ( | enum rcc_osc | osc | ) |
RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.
- Note
- The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
- Parameters
-
[in] osc Oscillator ID. Only HSE and LSE have effect.
Definition at line 238 of file rcc_common_all.c.
◆ rcc_osc_bypass_enable()
| void rcc_osc_bypass_enable | ( | enum rcc_osc | osc | ) |
RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.
- Note
- The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
- Parameters
-
[in] osc Oscillator ID. Only HSE and LSE have effect.
Definition at line 208 of file rcc_common_all.c.
References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.
◆ rcc_osc_off()
| void rcc_osc_off | ( | enum rcc_osc | osc | ) |
RCC Turn off an Oscillator.
Disable an oscillator and power off.
- Note
- An oscillator cannot be turned off if it is selected as the system clock.
- Parameters
-
osc Oscillator ID
Definition at line 282 of file rcc.c.
References RCC_BDCR, RCC_CR, RCC_CR2, RCC_CSR, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
◆ rcc_osc_on()
| void rcc_osc_on | ( | enum rcc_osc | osc | ) |
RCC Turn on an Oscillator.
Enable an oscillator and power on. Each oscillator requires an amount of time to settle to a usable state. Refer to datasheets for time delay information. A status flag is available to indicate when the oscillator becomes ready (see rcc_osc_ready_int_flag and rcc_wait_for_osc_ready).
- Parameters
-
osc Oscillator ID
Definition at line 244 of file rcc.c.
References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR2, RCC_CR2_HSI14ON, RCC_CR2_HSI48ON, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_osc_ready_int_clear()
| void rcc_osc_ready_int_clear | ( | enum rcc_osc | osc | ) |
RCC Clear the Oscillator Ready Interrupt Flag.
Clear the interrupt flag that was set when a clock oscillator became ready to use.
- Parameters
-
osc Oscillator ID
Definition at line 57 of file rcc.c.
References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSI14RDYC, RCC_CIR_HSI48RDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
◆ rcc_osc_ready_int_disable()
| void rcc_osc_ready_int_disable | ( | enum rcc_osc | osc | ) |
◆ rcc_osc_ready_int_enable()
| void rcc_osc_ready_int_enable | ( | enum rcc_osc | osc | ) |
RCC Enable the Oscillator Ready Interrupt.
- Parameters
-
osc Oscillator ID
Definition at line 90 of file rcc.c.
References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSI14RDYIE, RCC_CIR_HSI48RDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
◆ rcc_osc_ready_int_flag()
| int rcc_osc_ready_int_flag | ( | enum rcc_osc | osc | ) |
RCC Read the Oscillator Ready Interrupt Flag.
- Parameters
-
osc Oscillator ID
- Returns
- int. Boolean value for flag set.
Definition at line 157 of file rcc.c.
References cm3_assert_not_reached, RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSI14RDYF, RCC_CIR_HSI48RDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
◆ rcc_periph_clock_disable()
| void rcc_periph_clock_disable | ( | enum rcc_periph_clken | clken | ) |
Disable Peripheral Clock in running mode.
Disable the clock on particular peripheral.
- Parameters
-
[in] clken rcc_periph_clken Peripheral RCC
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 139 of file rcc_common_all.c.
References _RCC_REG.
◆ rcc_periph_clock_enable()
| void rcc_periph_clock_enable | ( | enum rcc_periph_clken | clken | ) |
Enable Peripheral Clock in running mode.
Enable the clock on particular peripheral.
- Parameters
-
[in] clken rcc_periph_clken Peripheral RCC
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 127 of file rcc_common_all.c.
References _RCC_BIT, and _RCC_REG.
Referenced by crs_autotrim_usb_enable(), and st_usbfs_v2_usbd_init().
◆ rcc_periph_reset_hold()
| void rcc_periph_reset_hold | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, hold.
Reset particular peripheral, and hold in reset state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 166 of file rcc_common_all.c.
◆ rcc_periph_reset_pulse()
| void rcc_periph_reset_pulse | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, pulsed.
Reset particular peripheral, and restore to working state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 152 of file rcc_common_all.c.
References _RCC_BIT, and _RCC_REG.
Referenced by can_reset().
◆ rcc_periph_reset_release()
| void rcc_periph_reset_release | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, release.
Restore peripheral from reset state to working state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 179 of file rcc_common_all.c.
References _RCC_REG.
◆ rcc_peripheral_clear_reset()
| void rcc_peripheral_clear_reset | ( | volatile uint32_t * | reg, |
| uint32_t | clear_reset | ||
| ) |
RCC Remove Reset on Peripherals.
Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
- rcc_periph_reset_pulse if you are only going to toggle reset anyway.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] clear_reset Unsigned int32. Logical OR of all resets to be removed: - If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values
- If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values
- If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values
Definition at line 111 of file rcc_common_all.c.
◆ rcc_peripheral_disable_clock()
| void rcc_peripheral_disable_clock | ( | volatile uint32_t * | reg, |
| uint32_t | en | ||
| ) |
RCC Disable Peripheral Clocks.
Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] en Unsigned int32. Logical OR of all enables to be used for disabling. - If register is RCC_AHBENR, from RCC_APHBENR enable values
- If register is RCC_APB1ENR, from RCC_APB1ENR enable values
- If register is RCC_APB2ENR, from RCC_APPB2ENR enable values
Definition at line 66 of file rcc_common_all.c.
◆ rcc_peripheral_enable_clock()
| void rcc_peripheral_enable_clock | ( | volatile uint32_t * | reg, |
| uint32_t | en | ||
| ) |
RCC Enable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] en Unsigned int32. Logical OR of all enables to be set - If register is RCC_AHBENR, from RCC_APHBENR enable values
- If register is RCC_APB1ENR, from RCC_APB1ENR enable values
- If register is RCC_APB2ENR, from RCC_APPB2ENR enable values
Definition at line 44 of file rcc_common_all.c.
◆ rcc_peripheral_reset()
| void rcc_peripheral_reset | ( | volatile uint32_t * | reg, |
| uint32_t | reset | ||
| ) |
RCC Reset Peripherals.
Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
- rcc_periph_reset_pulse if you are only going to toggle reset anyway.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] reset Unsigned int32. Logical OR of all resets. - If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values
- If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values
- If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values
Definition at line 88 of file rcc_common_all.c.
◆ rcc_set_hpre()
| void rcc_set_hpre | ( | uint32_t | hpre | ) |
RCC Set the AHB Prescale Factor.
- Parameters
-
[in] hpre Unsigned int32. AHB prescale factor RCC_CFGR AHB prescale Factors
Definition at line 484 of file rcc.c.
References RCC_CFGR.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_set_i2c_clock_hsi()
| void rcc_set_i2c_clock_hsi | ( | uint32_t | i2c | ) |
◆ rcc_set_i2c_clock_sysclk()
| void rcc_set_i2c_clock_sysclk | ( | uint32_t | i2c | ) |
Definition at line 531 of file rcc.c.
References I2C1, RCC_CFGR3, and RCC_CFGR3_I2C1SW.
◆ rcc_set_mco()
| void rcc_set_mco | ( | uint32_t | mcosrc | ) |
Select the source of Microcontroller Clock Output.
Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1
- Parameters
-
[in] mcosrc the unshifted source bits
Definition at line 191 of file rcc_common_all.c.
References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.
◆ rcc_set_pll_multiplication_factor()
| void rcc_set_pll_multiplication_factor | ( | uint32_t | mul | ) |
RCC Set the PLL Multiplication Factor.
- Note
- This only has effect when the PLL is disabled.
- Parameters
-
[in] mul Unsigned int32. PLL multiplication factor PLLMUL: PLL multiplication factor
Definition at line 434 of file rcc.c.
References RCC_CFGR.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_set_pll_source()
| void rcc_set_pll_source | ( | uint32_t | pllsrc | ) |
RCC Set the PLL Clock Source.
- Note
- This only has effect when the PLL is disabled.
- Parameters
-
[in] pllsrc Unsigned int32. PLL clock source PLLSRC: PLL Clock source
Definition at line 447 of file rcc.c.
References RCC_CFGR.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_set_pllxtpre()
| void rcc_set_pllxtpre | ( | uint32_t | pllxtpre | ) |
RCC Set the HSE Frequency Divider used as PLL Clock Source.
- Note
- This only has effect when the PLL is disabled.
- Parameters
-
[in] pllxtpre Unsigned int32. HSE division factor PLLXTPRE: HSE divider for PLL source
Definition at line 461 of file rcc.c.
References RCC_CFGR.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz().
◆ rcc_set_ppre()
| void rcc_set_ppre | ( | uint32_t | ppre | ) |
RCC Set the APB Prescale Factor.
- Parameters
-
[in] ppre Unsigned int32. APB prescale factor RCC_CFGR APB prescale Factors
Definition at line 473 of file rcc.c.
References RCC_CFGR.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_set_prediv()
| void rcc_set_prediv | ( | uint32_t | prediv | ) |
Set PLL Source pre-divider CAUTION.
On F03x and F05, prediv only applies to HSE source. On others, this is after source selection. See also f3.
- Parameters
-
[in] prediv division by prediv+1 PLL source predividers
Definition at line 495 of file rcc.c.
References RCC_CFGR2.
◆ rcc_set_rtc_clock_source()
| void rcc_set_rtc_clock_source | ( | enum rcc_osc | clk | ) |
RCC Set the Source for the RTC clock.
- Parameters
-
[in] clk RTC clock source. Only HSE/32, LSE and LSI.
Definition at line 408 of file rcc.c.
References RCC_BDCR, RCC_BDCR_RTCSEL_HSE, RCC_BDCR_RTCSEL_LSE, RCC_BDCR_RTCSEL_LSI, RCC_HSE, RCC_LSE, and RCC_LSI.
◆ rcc_set_sysclk_source()
| void rcc_set_sysclk_source | ( | enum rcc_osc | clk | ) |
RCC Set the Source for the System Clock.
- Parameters
-
clk Oscillator ID. Only HSE, LSE and PLL have effect.
Definition at line 334 of file rcc.c.
References RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSI, RCC_CFGR_SW_HSI48, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
◆ rcc_set_usbclk_source()
| void rcc_set_usbclk_source | ( | enum rcc_osc | clk | ) |
◆ rcc_system_clock_source()
| enum rcc_osc rcc_system_clock_source | ( | void | ) |
RCC Get the System Clock Source.
- Returns
- current system clock source
Definition at line 507 of file rcc.c.
References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI, RCC_CFGR_SWS_HSI48, RCC_CFGR_SWS_PLL, RCC_HSE, RCC_HSI, RCC_HSI48, and RCC_PLL.
◆ rcc_usb_clock_source()
| enum rcc_osc rcc_usb_clock_source | ( | void | ) |
◆ rcc_wait_for_osc_ready()
| void rcc_wait_for_osc_ready | ( | enum rcc_osc | osc | ) |
Wait for Oscillator Ready.
Block until the hardware indicates that the Oscillator is ready.
- Parameters
-
osc Oscillator ID
Definition at line 227 of file rcc.c.
References rcc_is_osc_ready().
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().
Variable Documentation
◆ rcc_ahb_frequency
|
extern |
Definition at line 45 of file rcc.c.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_get_i2c_clk_freq(), and rcc_get_usart_clksel_freq().
◆ rcc_apb1_frequency
|
extern |
Definition at line 46 of file rcc.c.
Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), rcc_get_usart_clk_freq(), and rcc_get_usart_clksel_freq().
