libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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RCC Defines
STM32F0xx Defines

Defined Constants and Types for the STM32F0xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Modules

 PLLMUL: PLL multiplication factor
 
 PLLXTPRE: HSE divider for PLL source
 
 PLLSRC: PLL Clock source
 
 RCC_CFGR APB prescale Factors
 
 RCC_CFGR AHB prescale Factors
 
 RCC_APB2RSTR reset values
 
 RCC_APB1RSTR reset values
 
 RCC_APHBENR enable values
 
 RCC_APPB2ENR enable values
 
 RCC_APB1ENR enable values
 
 RCC_AHBRSTR reset values
 
 PLL source predividers
 
 UART for clock source selecting
 
 UART Clock source selections
 

Macros

#define RCC_CR   MMIO32(RCC_BASE + 0x00)
 
#define RCC_CFGR   MMIO32(RCC_BASE + 0x04)
 
#define RCC_CIR   MMIO32(RCC_BASE + 0x08)
 
#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x0c)
 
#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x10)
 
#define RCC_AHBENR   MMIO32(RCC_BASE + 0x14)
 
#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x18)
 
#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x1c)
 
#define RCC_BDCR   MMIO32(RCC_BASE + 0x20)
 
#define RCC_CSR   MMIO32(RCC_BASE + 0x24)
 
#define RCC_AHBRSTR   MMIO32(RCC_BASE + 0x28)
 
#define RCC_CFGR2   MMIO32(RCC_BASE + 0x2c)
 
#define RCC_CFGR3   MMIO32(RCC_BASE + 0x30)
 
#define RCC_CR2   MMIO32(RCC_BASE + 0x34)
 
#define RCC_CR_PLLRDY   (1 << 25)
 
#define RCC_CR_PLLON   (1 << 24)
 
#define RCC_CR_CSSON   (1 << 19)
 
#define RCC_CR_HSEBYP   (1 << 18)
 
#define RCC_CR_HSERDY   (1 << 17)
 
#define RCC_CR_HSEON   (1 << 16)
 
#define RCC_CR_HSICAL_SHIFT   8
 
#define RCC_CR_HSICAL   (0xFF << RCC_CR_HSICAL_SHIFT)
 
#define RCC_CR_HSITRIM_SHIFT   3
 
#define RCC_CR_HSITRIM   (0x1F << RCC_CR_HSITRIM_SHIFT)
 
#define RCC_CR_HSIRDY   (1 << 1)
 
#define RCC_CR_HSION   (1 << 0)
 
#define RCC_CFGR_PLLNODIV   (1 << 31)
 
#define RCC_CFGR_MCOPRE_SHIFT   28
 
#define RCC_CFGR_MCOPRE   (7 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV1   (0 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV2   (1 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV4   (2 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV8   (3 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV16   (4 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV32   (5 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV64   (6 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCOPRE_DIV128   (7 << RCC_CFGR_MCOPRE_SHIFT)
 
#define RCC_CFGR_MCO_SHIFT   24
 
#define RCC_CFGR_MCO_MASK   0xf
 
#define RCC_CFGR_MCO_NOCLK   0
 
#define RCC_CFGR_MCO_HSI14   1
 
#define RCC_CFGR_MCO_LSI   2
 
#define RCC_CFGR_MCO_LSE   3
 
#define RCC_CFGR_MCO_SYSCLK   4
 
#define RCC_CFGR_MCO_HSI   5
 
#define RCC_CFGR_MCO_HSE   6
 
#define RCC_CFGR_MCO_PLL   7
 
#define RCC_CFGR_MCO_HSI48   8
 
#define RCC_CFGR_PLLMUL_SHIFT   18
 
#define RCC_CFGR_PLLMUL   (0x0F << RCC_CFGR_PLLMUL_SHIFT)
 
#define RCC_CFGR_PLLXTPRE   (1<<17)
 
#define RCC_CFGR_PLLSRC   (1<<16)
 
#define RCC_CFGR_PLLSRC0   (1<<15)
 
#define RCC_CFGR_ADCPRE   (1<<14)
 
#define RCC_CFGR_PPRE_SHIFT   8
 
#define RCC_CFGR_PPRE   (7 << RCC_CFGR_PPRE_SHIFT)
 
#define RCC_CFGR_PPRE_MASK   0x7
 
#define RCC_CFGR_HPRE_SHIFT   4
 
#define RCC_CFGR_HPRE   (0xf << RCC_CFGR_HPRE_SHIFT)
 
#define RCC_CFGR_HPRE_MASK   0xf
 
#define RCC_CFGR_SWS_SHIFT   2
 
#define RCC_CFGR_SWS   (3 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SWS_HSI   (0 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SWS_HSE   (1 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SWS_PLL   (2 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SWS_HSI48   (3 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SW_SHIFT   0
 
#define RCC_CFGR_SW   (3 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CFGR_SW_HSI   (0 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CFGR_SW_HSE   (1 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CFGR_SW_PLL   (2 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CFGR_SW_HSI48   (3 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CIR_CSSC   (1 << 23)
 
#define RCC_CIR_HSI48RDYC   (1 << 22)
 
#define RCC_CIR_HSI14RDYC   (1 << 21)
 
#define RCC_CIR_PLLRDYC   (1 << 20)
 
#define RCC_CIR_HSERDYC   (1 << 19)
 
#define RCC_CIR_HSIRDYC   (1 << 18)
 
#define RCC_CIR_LSERDYC   (1 << 17)
 
#define RCC_CIR_LSIRDYC   (1 << 16)
 
#define RCC_CIR_HSI48RDYIE   (1 << 14)
 
#define RCC_CIR_HSI14RDYIE   (1 << 13)
 
#define RCC_CIR_PLLRDYIE   (1 << 12)
 
#define RCC_CIR_HSERDYIE   (1 << 11)
 
#define RCC_CIR_HSIRDYIE   (1 << 10)
 
#define RCC_CIR_LSERDYIE   (1 << 9)
 
#define RCC_CIR_LSIRDYIE   (1 << 8)
 
#define RCC_CIR_CSSF   (1 << 7)
 
#define RCC_CIR_HSI48RDYF   (1 << 6)
 
#define RCC_CIR_HSI14RDYF   (1 << 5)
 
#define RCC_CIR_PLLRDYF   (1 << 4)
 
#define RCC_CIR_HSERDYF   (1 << 3)
 
#define RCC_CIR_HSIRDYF   (1 << 2)
 
#define RCC_CIR_LSERDYF   (1 << 1)
 
#define RCC_CIR_LSIRDYF   (1 << 0)
 
#define RCC_BDCR_BDRST   (1 << 16)
 
#define RCC_BDCR_RTCEN   (1 << 15)
 
#define RCC_BDCR_RTCSEL_SHIFT   8
 
#define RCC_BDCR_RTCSEL   (3 << RCC_BDCR_RTCSEL_SHIFT)
 
#define RCC_BDCR_RTCSEL_NOCLK   (0 << RCC_BDCR_RTCSEL_SHIFT)
 
#define RCC_BDCR_RTCSEL_LSE   (1 << RCC_BDCR_RTCSEL_SHIFT)
 
#define RCC_BDCR_RTCSEL_LSI   (2 << RCC_BDCR_RTCSEL_SHIFT)
 
#define RCC_BDCR_RTCSEL_HSE   (3 << RCC_BDCR_RTCSEL_SHIFT)
 
#define RCC_BDCR_LSEDRV_SHIFT   3
 
#define RCC_BDCR_LSEDRV   (3 << RCC_BDCR_LSEDRV_SHIFT)
 
#define RCC_BDCR_LSEDRV_LOW   (0 << RCC_BDCR_LSEDRV_SHIFT)
 
#define RCC_BDCR_LSEDRV_MEDLO   (1 << RCC_BDCR_LSEDRV_SHIFT)
 
#define RCC_BDCR_LSEDRV_MEDHI   (2 << RCC_BDCR_LSEDRV_SHIFT)
 
#define RCC_BDCR_LSEDRV_HIGH   (3 << RCC_BDCR_LSEDRV_SHIFT)
 
#define RCC_BDCR_LSEBYP   (1 << 2)
 
#define RCC_BDCR_LSERDY   (1 << 1)
 
#define RCC_BDCR_LSEON   (1 << 0)
 
#define RCC_CSR_LPWRRSTF   (1 << 31)
 
#define RCC_CSR_WWDGRSTF   (1 << 30)
 
#define RCC_CSR_IWDGRSTF   (1 << 29)
 
#define RCC_CSR_SFTRSTF   (1 << 28)
 
#define RCC_CSR_PORRSTF   (1 << 27)
 
#define RCC_CSR_PINRSTF   (1 << 26)
 
#define RCC_CSR_OBLRSTF   (1 << 25)
 
#define RCC_CSR_RMVF   (1 << 24)
 
#define RCC_CSR_RESET_FLAGS
 
#define RCC_CSR_V18PWRRSTF   (1 << 23)
 
#define RCC_CSR_LSIRDY   (1 << 1)
 
#define RCC_CSR_LSION   (1 << 0)
 
#define RCC_CFGR2_PREDIV   0xf
 
#define RCC_CFGR3_USARTxSW_MASK   0x3
 
#define RCC_CFGR3_ADCSW   (1 << 8)
 
#define RCC_CFGR3_USBSW   (1 << 7)
 
#define RCC_CFGR3_CECSW   (1 << 6)
 
#define RCC_CFGR3_I2C1SW   (1 << 4)
 
#define RCC_CR2_HSI48CAL_SHIFT   24
 
#define RCC_CR2_HSI48CAL   (0xFF << RCC_CR2_HSI48CAL_SHIFT)
 
#define RCC_CR2_HSI48RDY   (1 << 17)
 
#define RCC_CR2_HSI48ON   (1 << 16)
 
#define RCC_CR2_HSI14CAL_SHIFT   8
 
#define RCC_CR2_HSI14CAL   (0xFF << RCC_CR2_HSI14CAL_SHIFT)
 
#define RCC_CR2_HSI14TRIM_SHIFT   3
 
#define RCC_CR2_HSI14TRIM   (31 << RCC_CR2_HSI14TRIM_SHIFT)
 
#define RCC_CR2_HSI14DIS   (1 << 2)
 
#define RCC_CR2_HSI14RDY   (1 << 1)
 
#define RCC_CR2_HSI14ON   (1 << 0)
 
#define rcc_apb2_frequency   rcc_apb1_frequency
 F0 doens't realllly have apb2, but it has a bunch of things enabled via the "APB2" enable register. More...
 
#define _REG_BIT(base, bit)   (((base) << 5) + (bit))
 

Enumerations

enum  rcc_osc {
  RCC_HSI14 , RCC_HSI , RCC_HSE , RCC_PLL ,
  RCC_LSI , RCC_LSE , RCC_HSI48
}
 
enum  rcc_periph_clken {
  RCC_DMA = _REG_BIT(0x14, 0) , RCC_DMA1 = _REG_BIT(0x14, 0) , RCC_DMA2 = _REG_BIT(0x14, 1) , RCC_SRAM = _REG_BIT(0x14, 2) ,
  RCC_FLTIF = _REG_BIT(0x14, 4) , RCC_CRC = _REG_BIT(0x14, 6) , RCC_GPIOA = _REG_BIT(0x14, 17) , RCC_GPIOB = _REG_BIT(0x14, 18) ,
  RCC_GPIOC = _REG_BIT(0x14, 19) , RCC_GPIOD = _REG_BIT(0x14, 20) , RCC_GPIOE = _REG_BIT(0x14, 21) , RCC_GPIOF = _REG_BIT(0x14, 22) ,
  RCC_TSC = _REG_BIT(0x14, 24) , RCC_SYSCFG_COMP = _REG_BIT(0x18, 0) , RCC_USART6 = _REG_BIT(0x18, 5) , RCC_USART7 = _REG_BIT(0x18, 6) ,
  RCC_USART8 = _REG_BIT(0x18, 7) , RCC_ADC = _REG_BIT(0x18, 9) , RCC_ADC1 = _REG_BIT(0x18, 9) , RCC_TIM1 = _REG_BIT(0x18, 11) ,
  RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_USART1 = _REG_BIT(0x18, 14) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) ,
  RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_DBGMCU = _REG_BIT(0x18, 22) , RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) ,
  RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM7 = _REG_BIT(0x1C, 5) , RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_WWDG = _REG_BIT(0x1C, 11) ,
  RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_USART3 = _REG_BIT(0x1C, 18) , RCC_USART4 = _REG_BIT(0x1C, 19) ,
  RCC_USART5 = _REG_BIT(0x1C, 20) , RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) ,
  RCC_CAN = _REG_BIT(0x1C, 25) , RCC_CAN1 = _REG_BIT(0x1C, 25) , RCC_CRS = _REG_BIT(0x1C, 27) , RCC_PWR = _REG_BIT(0x1C, 28) ,
  RCC_DAC = _REG_BIT(0x1C, 29) , RCC_DAC1 = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30) , RCC_RTC = _REG_BIT(0x20, 15)
}
 
enum  rcc_periph_rst {
  RST_SYSCFG = _REG_BIT(0x0C, 0) , RST_ADC = _REG_BIT(0x0C, 9) , RST_ADC1 = _REG_BIT(0x0C, 9) , RST_TIM1 = _REG_BIT(0x0C, 11) ,
  RST_SPI1 = _REG_BIT(0x0C, 12) , RST_USART1 = _REG_BIT(0x0C, 14) , RST_TIM15 = _REG_BIT(0x0C, 16) , RST_TIM16 = _REG_BIT(0x0C, 17) ,
  RST_TIM17 = _REG_BIT(0x0C, 18) , RST_DBGMCU = _REG_BIT(0x0C, 22) , RST_TIM2 = _REG_BIT(0x10, 0) , RST_TIM3 = _REG_BIT(0x10, 1) ,
  RST_TIM6 = _REG_BIT(0x10, 4) , RST_TIM7 = _REG_BIT(0x10, 5) , RST_TIM14 = _REG_BIT(0x10, 8) , RST_WWDG = _REG_BIT(0x10, 11) ,
  RST_SPI2 = _REG_BIT(0x10, 14) , RST_USART2 = _REG_BIT(0x10, 17) , RST_USART3 = _REG_BIT(0x10, 18) , RST_USART4 = _REG_BIT(0x10, 19) ,
  RST_I2C1 = _REG_BIT(0x10, 21) , RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_CAN = _REG_BIT(0x10, 25) ,
  RST_CAN1 = _REG_BIT(0x10, 25) , RST_CRS = _REG_BIT(0x10, 27) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC = _REG_BIT(0x10, 29) ,
  RST_DAC1 = _REG_BIT(0x10, 29) , RST_CEC = _REG_BIT(0x10, 30) , RST_BDCR = _REG_BIT(0x20, 16) , RST_GPIOA = _REG_BIT(0x28, 17) ,
  RST_GPIOB = _REG_BIT(0x28, 18) , RST_GPIOC = _REG_BIT(0x28, 19) , RST_GPIOD = _REG_BIT(0x28, 20) , RST_GPIOE = _REG_BIT(0x28, 21) ,
  RST_GPIOF = _REG_BIT(0x28, 22) , RST_TSC = _REG_BIT(0x28, 24)
}
 

Functions

void rcc_osc_ready_int_clear (enum rcc_osc osc)
 RCC Clear the Oscillator Ready Interrupt Flag. More...
 
void rcc_osc_ready_int_enable (enum rcc_osc osc)
 RCC Enable the Oscillator Ready Interrupt. More...
 
void rcc_osc_ready_int_disable (enum rcc_osc osc)
 RCC Disable the Oscillator Ready Interrupt. More...
 
int rcc_osc_ready_int_flag (enum rcc_osc osc)
 RCC Read the Oscillator Ready Interrupt Flag. More...
 
void rcc_osc_on (enum rcc_osc osc)
 RCC Turn on an Oscillator. More...
 
void rcc_osc_off (enum rcc_osc osc)
 RCC Turn off an Oscillator. More...
 
void rcc_css_enable (void)
 RCC Enable the Clock Security System. More...
 
void rcc_css_disable (void)
 RCC Disable the Clock Security System. More...
 
void rcc_css_int_clear (void)
 RCC Clear the Clock Security System Interrupt Flag. More...
 
int rcc_css_int_flag (void)
 RCC Read the Clock Security System Interrupt Flag. More...
 
void rcc_set_sysclk_source (enum rcc_osc clk)
 RCC Set the Source for the System Clock. More...
 
void rcc_set_usbclk_source (enum rcc_osc clk)
 RCC Set the Source for the USB Clock. More...
 
void rcc_set_rtc_clock_source (enum rcc_osc clk)
 RCC Set the Source for the RTC clock. More...
 
void rcc_enable_rtc_clock (void)
 RCC Enable the RTC clock. More...
 
void rcc_disable_rtc_clock (void)
 RCC Disable the RTC clock. More...
 
void rcc_set_pll_multiplication_factor (uint32_t mul)
 RCC Set the PLL Multiplication Factor. More...
 
void rcc_set_pll_source (uint32_t pllsrc)
 RCC Set the PLL Clock Source. More...
 
void rcc_set_pllxtpre (uint32_t pllxtpre)
 RCC Set the HSE Frequency Divider used as PLL Clock Source. More...
 
void rcc_set_ppre (uint32_t ppre)
 RCC Set the APB Prescale Factor. More...
 
void rcc_set_hpre (uint32_t hpre)
 RCC Set the AHB Prescale Factor. More...
 
void rcc_set_prediv (uint32_t prediv)
 Set PLL Source pre-divider CAUTION. More...
 
enum rcc_osc rcc_system_clock_source (void)
 RCC Get the System Clock Source. More...
 
void rcc_set_i2c_clock_hsi (uint32_t i2c)
 
void rcc_set_i2c_clock_sysclk (uint32_t i2c)
 
uint32_t rcc_get_i2c_clocks (void)
 
enum rcc_osc rcc_usb_clock_source (void)
 RCC Get the USB Clock Source. More...
 
void rcc_clock_setup_in_hse_8mhz_out_48mhz (void)
 Set System Clock PLL at 48MHz from HSE at 8MHz. More...
 
void rcc_clock_setup_in_hsi_out_48mhz (void)
 Set System Clock PLL at 48MHz from HSI. More...
 
void rcc_clock_setup_in_hsi48_out_48mhz (void)
 Set System Clock HSI48 at 48MHz. More...
 
uint32_t rcc_get_usart_clk_freq (uint32_t usart)
 Get the peripheral clock speed for the USART at base specified. More...
 
uint32_t rcc_get_timer_clk_freq (uint32_t timer)
 Get the peripheral clock speed for the Timer at base specified. More...
 
uint32_t rcc_get_i2c_clk_freq (uint32_t i2c)
 Get the peripheral clock speed for the I2C device at base specified. More...
 
uint32_t rcc_get_spi_clk_freq (uint32_t spi)
 Get the peripheral clock speed for the SPI device at base specified. More...
 
void rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Enable Peripheral Clocks. More...
 
void rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Disable Peripheral Clocks. More...
 
void rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
 RCC Reset Peripherals. More...
 
void rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
 RCC Remove Reset on Peripherals. More...
 
void rcc_periph_clock_enable (enum rcc_periph_clken clken)
 Enable Peripheral Clock in running mode. More...
 
void rcc_periph_clock_disable (enum rcc_periph_clken clken)
 Disable Peripheral Clock in running mode. More...
 
void rcc_periph_reset_pulse (enum rcc_periph_rst rst)
 Reset Peripheral, pulsed. More...
 
void rcc_periph_reset_hold (enum rcc_periph_rst rst)
 Reset Peripheral, hold. More...
 
void rcc_periph_reset_release (enum rcc_periph_rst rst)
 Reset Peripheral, release. More...
 
void rcc_set_mco (uint32_t mcosrc)
 Select the source of Microcontroller Clock Output. More...
 
void rcc_osc_bypass_enable (enum rcc_osc osc)
 RCC Enable Bypass. More...
 
void rcc_osc_bypass_disable (enum rcc_osc osc)
 RCC Disable Bypass. More...
 
bool rcc_is_osc_ready (enum rcc_osc osc)
 Is the given oscillator ready? More...
 
void rcc_wait_for_osc_ready (enum rcc_osc osc)
 Wait for Oscillator Ready. More...
 
uint16_t rcc_get_div_from_hpre (uint8_t div_val)
 This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...
 

Variables

uint32_t rcc_ahb_frequency
 
uint32_t rcc_apb1_frequency
 

Detailed Description

Defined Constants and Types for the STM32F0xx Reset and Clock Control

Author
© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz
Version
1.0.0
Date
29 Jun 2013

LGPL License Terms libopencm3 License

Author
© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT (   base,
  bit 
)    (((base) << 5) + (bit))

Definition at line 440 of file f0/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR   MMIO32(RCC_BASE + 0x14)

Definition at line 53 of file f0/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR   MMIO32(RCC_BASE + 0x28)

Definition at line 58 of file f0/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x1c)

Definition at line 55 of file f0/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x10)

Definition at line 52 of file f0/rcc.h.

◆ rcc_apb2_frequency

#define rcc_apb2_frequency   rcc_apb1_frequency

F0 doens't realllly have apb2, but it has a bunch of things enabled via the "APB2" enable register.

Fake it out.

Definition at line 434 of file f0/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x18)

Definition at line 54 of file f0/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x0c)

Definition at line 51 of file f0/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR   MMIO32(RCC_BASE + 0x20)

Definition at line 56 of file f0/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST   (1 << 16)

Definition at line 316 of file f0/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP   (1 << 2)

Definition at line 330 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV

#define RCC_BDCR_LSEDRV   (3 << RCC_BDCR_LSEDRV_SHIFT)

Definition at line 325 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV_HIGH

#define RCC_BDCR_LSEDRV_HIGH   (3 << RCC_BDCR_LSEDRV_SHIFT)

Definition at line 329 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV_LOW

#define RCC_BDCR_LSEDRV_LOW   (0 << RCC_BDCR_LSEDRV_SHIFT)

Definition at line 326 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV_MEDHI

#define RCC_BDCR_LSEDRV_MEDHI   (2 << RCC_BDCR_LSEDRV_SHIFT)

Definition at line 328 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV_MEDLO

#define RCC_BDCR_LSEDRV_MEDLO   (1 << RCC_BDCR_LSEDRV_SHIFT)

Definition at line 327 of file f0/rcc.h.

◆ RCC_BDCR_LSEDRV_SHIFT

#define RCC_BDCR_LSEDRV_SHIFT   3

Definition at line 324 of file f0/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON   (1 << 0)

Definition at line 332 of file f0/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY   (1 << 1)

Definition at line 331 of file f0/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN   (1 << 15)

Definition at line 317 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL   (3 << RCC_BDCR_RTCSEL_SHIFT)

Definition at line 319 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL_HSE

#define RCC_BDCR_RTCSEL_HSE   (3 << RCC_BDCR_RTCSEL_SHIFT)

Definition at line 323 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL_LSE

#define RCC_BDCR_RTCSEL_LSE   (1 << RCC_BDCR_RTCSEL_SHIFT)

Definition at line 321 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL_LSI

#define RCC_BDCR_RTCSEL_LSI   (2 << RCC_BDCR_RTCSEL_SHIFT)

Definition at line 322 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL_NOCLK

#define RCC_BDCR_RTCSEL_NOCLK   (0 << RCC_BDCR_RTCSEL_SHIFT)

Definition at line 320 of file f0/rcc.h.

◆ RCC_BDCR_RTCSEL_SHIFT

#define RCC_BDCR_RTCSEL_SHIFT   8

Definition at line 318 of file f0/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR   MMIO32(RCC_BASE + 0x04)

Definition at line 49 of file f0/rcc.h.

◆ RCC_CFGR2

#define RCC_CFGR2   MMIO32(RCC_BASE + 0x2c)

Definition at line 59 of file f0/rcc.h.

◆ RCC_CFGR2_PREDIV

#define RCC_CFGR2_PREDIV   0xf

Definition at line 365 of file f0/rcc.h.

◆ RCC_CFGR3

#define RCC_CFGR3   MMIO32(RCC_BASE + 0x30)

Definition at line 60 of file f0/rcc.h.

◆ RCC_CFGR3_ADCSW

#define RCC_CFGR3_ADCSW   (1 << 8)

Definition at line 407 of file f0/rcc.h.

◆ RCC_CFGR3_CECSW

#define RCC_CFGR3_CECSW   (1 << 6)

Definition at line 409 of file f0/rcc.h.

◆ RCC_CFGR3_I2C1SW

#define RCC_CFGR3_I2C1SW   (1 << 4)

Definition at line 410 of file f0/rcc.h.

◆ RCC_CFGR3_USARTxSW_MASK

#define RCC_CFGR3_USARTxSW_MASK   0x3

Definition at line 405 of file f0/rcc.h.

◆ RCC_CFGR3_USBSW

#define RCC_CFGR3_USBSW   (1 << 7)

Definition at line 408 of file f0/rcc.h.

◆ RCC_CFGR_ADCPRE

#define RCC_CFGR_ADCPRE   (1<<14)

Definition at line 148 of file f0/rcc.h.

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE   (0xf << RCC_CFGR_HPRE_SHIFT)

Definition at line 163 of file f0/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK   0xf

Definition at line 164 of file f0/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT   4

Definition at line 162 of file f0/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE   6

Definition at line 105 of file f0/rcc.h.

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI   5

Definition at line 104 of file f0/rcc.h.

◆ RCC_CFGR_MCO_HSI14

#define RCC_CFGR_MCO_HSI14   1

Definition at line 100 of file f0/rcc.h.

◆ RCC_CFGR_MCO_HSI48

#define RCC_CFGR_MCO_HSI48   8

Definition at line 107 of file f0/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE   3

Definition at line 102 of file f0/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI   2

Definition at line 101 of file f0/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK   0xf

Definition at line 98 of file f0/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK   0

Definition at line 99 of file f0/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL   7

Definition at line 106 of file f0/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT   24

Definition at line 97 of file f0/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK   4

Definition at line 103 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE   (7 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 87 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1   (0 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 88 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV128

#define RCC_CFGR_MCOPRE_DIV128   (7 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 95 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16   (4 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 92 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2   (1 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 89 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV32

#define RCC_CFGR_MCOPRE_DIV32   (5 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 93 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4   (2 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 90 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV64

#define RCC_CFGR_MCOPRE_DIV64   (6 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 94 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8   (3 << RCC_CFGR_MCOPRE_SHIFT)

Definition at line 91 of file f0/rcc.h.

◆ RCC_CFGR_MCOPRE_SHIFT

#define RCC_CFGR_MCOPRE_SHIFT   28

Definition at line 86 of file f0/rcc.h.

◆ RCC_CFGR_PLLMUL

#define RCC_CFGR_PLLMUL   (0x0F << RCC_CFGR_PLLMUL_SHIFT)

Definition at line 110 of file f0/rcc.h.

◆ RCC_CFGR_PLLMUL_SHIFT

#define RCC_CFGR_PLLMUL_SHIFT   18

Definition at line 109 of file f0/rcc.h.

◆ RCC_CFGR_PLLNODIV

#define RCC_CFGR_PLLNODIV   (1 << 31)

Definition at line 84 of file f0/rcc.h.

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC   (1<<16)

Definition at line 139 of file f0/rcc.h.

◆ RCC_CFGR_PLLSRC0

#define RCC_CFGR_PLLSRC0   (1<<15)

Definition at line 147 of file f0/rcc.h.

◆ RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLXTPRE   (1<<17)

Definition at line 131 of file f0/rcc.h.

◆ RCC_CFGR_PPRE

#define RCC_CFGR_PPRE   (7 << RCC_CFGR_PPRE_SHIFT)

Definition at line 151 of file f0/rcc.h.

◆ RCC_CFGR_PPRE_MASK

#define RCC_CFGR_PPRE_MASK   0x7

Definition at line 152 of file f0/rcc.h.

◆ RCC_CFGR_PPRE_SHIFT

#define RCC_CFGR_PPRE_SHIFT   8

Definition at line 150 of file f0/rcc.h.

◆ RCC_CFGR_SW

#define RCC_CFGR_SW   (3 << RCC_CFGR_SW_SHIFT)

Definition at line 186 of file f0/rcc.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE   (1 << RCC_CFGR_SW_SHIFT)

Definition at line 188 of file f0/rcc.h.

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI   (0 << RCC_CFGR_SW_SHIFT)

Definition at line 187 of file f0/rcc.h.

◆ RCC_CFGR_SW_HSI48

#define RCC_CFGR_SW_HSI48   (3 << RCC_CFGR_SW_SHIFT)

Definition at line 190 of file f0/rcc.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL   (2 << RCC_CFGR_SW_SHIFT)

Definition at line 189 of file f0/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT   0

Definition at line 185 of file f0/rcc.h.

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS   (3 << RCC_CFGR_SWS_SHIFT)

Definition at line 179 of file f0/rcc.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE   (1 << RCC_CFGR_SWS_SHIFT)

Definition at line 181 of file f0/rcc.h.

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI   (0 << RCC_CFGR_SWS_SHIFT)

Definition at line 180 of file f0/rcc.h.

◆ RCC_CFGR_SWS_HSI48

#define RCC_CFGR_SWS_HSI48   (3 << RCC_CFGR_SWS_SHIFT)

Definition at line 183 of file f0/rcc.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL   (2 << RCC_CFGR_SWS_SHIFT)

Definition at line 182 of file f0/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT   2

Definition at line 178 of file f0/rcc.h.

◆ RCC_CIR

#define RCC_CIR   MMIO32(RCC_BASE + 0x08)

Definition at line 50 of file f0/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC   (1 << 23)

Definition at line 194 of file f0/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF   (1 << 7)

Definition at line 209 of file f0/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC   (1 << 19)

Definition at line 198 of file f0/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF   (1 << 3)

Definition at line 213 of file f0/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE   (1 << 11)

Definition at line 205 of file f0/rcc.h.

◆ RCC_CIR_HSI14RDYC

#define RCC_CIR_HSI14RDYC   (1 << 21)

Definition at line 196 of file f0/rcc.h.

◆ RCC_CIR_HSI14RDYF

#define RCC_CIR_HSI14RDYF   (1 << 5)

Definition at line 211 of file f0/rcc.h.

◆ RCC_CIR_HSI14RDYIE

#define RCC_CIR_HSI14RDYIE   (1 << 13)

Definition at line 203 of file f0/rcc.h.

◆ RCC_CIR_HSI48RDYC

#define RCC_CIR_HSI48RDYC   (1 << 22)

Definition at line 195 of file f0/rcc.h.

◆ RCC_CIR_HSI48RDYF

#define RCC_CIR_HSI48RDYF   (1 << 6)

Definition at line 210 of file f0/rcc.h.

◆ RCC_CIR_HSI48RDYIE

#define RCC_CIR_HSI48RDYIE   (1 << 14)

Definition at line 202 of file f0/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC   (1 << 18)

Definition at line 199 of file f0/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF   (1 << 2)

Definition at line 214 of file f0/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE   (1 << 10)

Definition at line 206 of file f0/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC   (1 << 17)

Definition at line 200 of file f0/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF   (1 << 1)

Definition at line 215 of file f0/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE   (1 << 9)

Definition at line 207 of file f0/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC   (1 << 16)

Definition at line 201 of file f0/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF   (1 << 0)

Definition at line 216 of file f0/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE   (1 << 8)

Definition at line 208 of file f0/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC   (1 << 20)

Definition at line 197 of file f0/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF   (1 << 4)

Definition at line 212 of file f0/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE   (1 << 12)

Definition at line 204 of file f0/rcc.h.

◆ RCC_CR

#define RCC_CR   MMIO32(RCC_BASE + 0x00)

Definition at line 48 of file f0/rcc.h.

◆ RCC_CR2

#define RCC_CR2   MMIO32(RCC_BASE + 0x34)

Definition at line 61 of file f0/rcc.h.

◆ RCC_CR2_HSI14CAL

#define RCC_CR2_HSI14CAL   (0xFF << RCC_CR2_HSI14CAL_SHIFT)

Definition at line 417 of file f0/rcc.h.

◆ RCC_CR2_HSI14CAL_SHIFT

#define RCC_CR2_HSI14CAL_SHIFT   8

Definition at line 416 of file f0/rcc.h.

◆ RCC_CR2_HSI14DIS

#define RCC_CR2_HSI14DIS   (1 << 2)

Definition at line 420 of file f0/rcc.h.

◆ RCC_CR2_HSI14ON

#define RCC_CR2_HSI14ON   (1 << 0)

Definition at line 422 of file f0/rcc.h.

◆ RCC_CR2_HSI14RDY

#define RCC_CR2_HSI14RDY   (1 << 1)

Definition at line 421 of file f0/rcc.h.

◆ RCC_CR2_HSI14TRIM

#define RCC_CR2_HSI14TRIM   (31 << RCC_CR2_HSI14TRIM_SHIFT)

Definition at line 419 of file f0/rcc.h.

◆ RCC_CR2_HSI14TRIM_SHIFT

#define RCC_CR2_HSI14TRIM_SHIFT   3

Definition at line 418 of file f0/rcc.h.

◆ RCC_CR2_HSI48CAL

#define RCC_CR2_HSI48CAL   (0xFF << RCC_CR2_HSI48CAL_SHIFT)

Definition at line 413 of file f0/rcc.h.

◆ RCC_CR2_HSI48CAL_SHIFT

#define RCC_CR2_HSI48CAL_SHIFT   24

Definition at line 412 of file f0/rcc.h.

◆ RCC_CR2_HSI48ON

#define RCC_CR2_HSI48ON   (1 << 16)

Definition at line 415 of file f0/rcc.h.

◆ RCC_CR2_HSI48RDY

#define RCC_CR2_HSI48RDY   (1 << 17)

Definition at line 414 of file f0/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON   (1 << 19)

Definition at line 71 of file f0/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP   (1 << 18)

Definition at line 72 of file f0/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON   (1 << 16)

Definition at line 74 of file f0/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY   (1 << 17)

Definition at line 73 of file f0/rcc.h.

◆ RCC_CR_HSICAL

#define RCC_CR_HSICAL   (0xFF << RCC_CR_HSICAL_SHIFT)

Definition at line 76 of file f0/rcc.h.

◆ RCC_CR_HSICAL_SHIFT

#define RCC_CR_HSICAL_SHIFT   8

Definition at line 75 of file f0/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION   (1 << 0)

Definition at line 80 of file f0/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   (1 << 1)

Definition at line 79 of file f0/rcc.h.

◆ RCC_CR_HSITRIM

#define RCC_CR_HSITRIM   (0x1F << RCC_CR_HSITRIM_SHIFT)

Definition at line 78 of file f0/rcc.h.

◆ RCC_CR_HSITRIM_SHIFT

#define RCC_CR_HSITRIM_SHIFT   3

Definition at line 77 of file f0/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON   (1 << 24)

Definition at line 70 of file f0/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   (1 << 25)

Definition at line 69 of file f0/rcc.h.

◆ RCC_CSR

#define RCC_CSR   MMIO32(RCC_BASE + 0x24)

Definition at line 57 of file f0/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF   (1 << 29)

Definition at line 338 of file f0/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF   (1 << 31)

Definition at line 336 of file f0/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION   (1 << 0)

Definition at line 349 of file f0/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY   (1 << 1)

Definition at line 348 of file f0/rcc.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF   (1 << 25)

Definition at line 342 of file f0/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF   (1 << 26)

Definition at line 341 of file f0/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF   (1 << 27)

Definition at line 340 of file f0/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS
Value:
(RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF)
RCC_CSR_OBLRSTF
#define RCC_CSR_OBLRSTF
Definition: f0/rcc.h:342
RCC_CSR_SFTRSTF
#define RCC_CSR_SFTRSTF
Definition: f0/rcc.h:339
RCC_CSR_LPWRRSTF
#define RCC_CSR_LPWRRSTF
Definition: f0/rcc.h:336
RCC_CSR_PORRSTF
#define RCC_CSR_PORRSTF
Definition: f0/rcc.h:340
RCC_CSR_WWDGRSTF
#define RCC_CSR_WWDGRSTF
Definition: f0/rcc.h:337

Definition at line 344 of file f0/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF   (1 << 24)

Definition at line 343 of file f0/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF   (1 << 28)

Definition at line 339 of file f0/rcc.h.

◆ RCC_CSR_V18PWRRSTF

#define RCC_CSR_V18PWRRSTF   (1 << 23)

Definition at line 347 of file f0/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF   (1 << 30)

Definition at line 337 of file f0/rcc.h.

Enumeration Type Documentation

◆ rcc_osc

enum rcc_osc
Enumerator
RCC_HSI14 
RCC_HSI 
RCC_HSE 
RCC_PLL 
RCC_LSI 
RCC_LSE 
RCC_HSI48 

Definition at line 436 of file f0/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken
Enumerator
RCC_DMA 
RCC_DMA1 
RCC_DMA2 
RCC_SRAM 
RCC_FLTIF 
RCC_CRC 
RCC_GPIOA 
RCC_GPIOB 
RCC_GPIOC 
RCC_GPIOD 
RCC_GPIOE 
RCC_GPIOF 
RCC_TSC 
RCC_SYSCFG_COMP 
RCC_USART6 
RCC_USART7 
RCC_USART8 
RCC_ADC 
RCC_ADC1 
RCC_TIM1 
RCC_SPI1 
RCC_USART1 
RCC_TIM15 
RCC_TIM16 
RCC_TIM17 
RCC_DBGMCU 
RCC_TIM2 
RCC_TIM3 
RCC_TIM6 
RCC_TIM7 
RCC_TIM14 
RCC_WWDG 
RCC_SPI2 
RCC_USART2 
RCC_USART3 
RCC_USART4 
RCC_USART5 
RCC_I2C1 
RCC_I2C2 
RCC_USB 
RCC_CAN 
RCC_CAN1 
RCC_CRS 
RCC_PWR 
RCC_DAC 
RCC_DAC1 
RCC_CEC 
RCC_RTC 

Definition at line 442 of file f0/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst
Enumerator
RST_SYSCFG 
RST_ADC 
RST_ADC1 
RST_TIM1 
RST_SPI1 
RST_USART1 
RST_TIM15 
RST_TIM16 
RST_TIM17 
RST_DBGMCU 
RST_TIM2 
RST_TIM3 
RST_TIM6 
RST_TIM7 
RST_TIM14 
RST_WWDG 
RST_SPI2 
RST_USART2 
RST_USART3 
RST_USART4 
RST_I2C1 
RST_I2C2 
RST_USB 
RST_CAN 
RST_CAN1 
RST_CRS 
RST_PWR 
RST_DAC 
RST_DAC1 
RST_CEC 
RST_BDCR 
RST_GPIOA 
RST_GPIOB 
RST_GPIOC 
RST_GPIOD 
RST_GPIOE 
RST_GPIOF 
RST_TSC 

Definition at line 500 of file f0/rcc.h.

Function Documentation

◆ rcc_clock_setup_in_hse_8mhz_out_48mhz()

void rcc_clock_setup_in_hse_8mhz_out_48mhz ( void  )

Set System Clock PLL at 48MHz from HSE at 8MHz.

Definition at line 557 of file rcc.c.

References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PLLMUL_MUL6, RCC_CFGR_PLLSRC_HSE_CLK, RCC_CFGR_PLLXTPRE_HSE_CLK, RCC_CFGR_PPRE_NODIV, RCC_HSE, rcc_osc_on(), RCC_PLL, rcc_set_hpre(), rcc_set_pll_multiplication_factor(), rcc_set_pll_source(), rcc_set_pllxtpre(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().

Here is the call graph for this function:

◆ rcc_clock_setup_in_hsi48_out_48mhz()

void rcc_clock_setup_in_hsi48_out_48mhz ( void  )

Set System Clock HSI48 at 48MHz.

Definition at line 612 of file rcc.c.

References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PPRE_NODIV, RCC_HSI48, rcc_osc_on(), rcc_set_hpre(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().

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◆ rcc_clock_setup_in_hsi_out_48mhz()

void rcc_clock_setup_in_hsi_out_48mhz ( void  )

Set System Clock PLL at 48MHz from HSI.

Definition at line 585 of file rcc.c.

References FLASH_ACR_LATENCY_024_048MHZ, flash_prefetch_enable(), flash_set_ws(), rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR_HPRE_NODIV, RCC_CFGR_PLLMUL_MUL12, RCC_CFGR_PLLSRC_HSI_CLK_DIV2, RCC_CFGR_PPRE_NODIV, RCC_HSI, rcc_osc_on(), RCC_PLL, rcc_set_hpre(), rcc_set_pll_multiplication_factor(), rcc_set_pll_source(), rcc_set_ppre(), rcc_set_sysclk_source(), and rcc_wait_for_osc_ready().

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◆ rcc_css_disable()

void rcc_css_disable ( void  )

RCC Disable the Clock Security System.

Definition at line 322 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void  )

RCC Enable the Clock Security System.

Definition at line 313 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void  )

RCC Clear the Clock Security System Interrupt Flag.

Definition at line 190 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void  )

RCC Read the Clock Security System Interrupt Flag.

Returns
int. Boolean value for flag set.

Definition at line 201 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_disable_rtc_clock()

void rcc_disable_rtc_clock ( void  )

RCC Disable the RTC clock.

Definition at line 397 of file rcc.c.

References RCC_BDCR.

◆ rcc_enable_rtc_clock()

void rcc_enable_rtc_clock ( void  )

RCC Enable the RTC clock.

Definition at line 387 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t  div_val)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters
div_valMasked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clksel_freq().

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◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t  i2c)

Get the peripheral clock speed for the I2C device at base specified.

Parameters
i2cBase address of I2C to get clock frequency for.

Definition at line 677 of file rcc.c.

References I2C1_BASE, rcc_ahb_frequency, rcc_apb1_frequency, RCC_CFGR, RCC_CFGR3, RCC_CFGR3_I2C1SW, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().

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◆ rcc_get_i2c_clocks()

uint32_t rcc_get_i2c_clocks ( void  )

Definition at line 538 of file rcc.c.

References RCC_CFGR3, and RCC_CFGR3_I2C1SW.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t  spi)

Get the peripheral clock speed for the SPI device at base specified.

Parameters
spiBase address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 695 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t  timer)

Get the peripheral clock speed for the Timer at base specified.

Parameters
timerBase address of TIM to get clock frequency for.

Definition at line 666 of file rcc.c.

References rcc_apb1_frequency, RCC_CFGR, RCC_CFGR_PPRE_MASK, RCC_CFGR_PPRE_NODIV, and RCC_CFGR_PPRE_SHIFT.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t  usart)

Get the peripheral clock speed for the USART at base specified.

Parameters
usartBase address of USART to get clock frequency for.

Definition at line 649 of file rcc.c.

References rcc_apb1_frequency, RCC_CFGR3_USART1SW_SHIFT, RCC_CFGR3_USART2SW_SHIFT, RCC_CFGR3_USART3SW_SHIFT, rcc_get_usart_clksel_freq(), USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc  osc)

Is the given oscillator ready?

Parameters
oscOscillator ID
Returns
true if the hardware indicates the oscillator is ready.

Definition at line 206 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR2, RCC_CR2_HSI14RDY, RCC_CR2_HSI48RDY, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc  osc)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc  osc)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc  osc)

RCC Turn off an Oscillator.

Disable an oscillator and power off.

Note
An oscillator cannot be turned off if it is selected as the system clock.
Parameters
oscOscillator ID

Definition at line 282 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CR2, RCC_CSR, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc  osc)

RCC Turn on an Oscillator.

Enable an oscillator and power on. Each oscillator requires an amount of time to settle to a usable state. Refer to datasheets for time delay information. A status flag is available to indicate when the oscillator becomes ready (see rcc_osc_ready_int_flag and rcc_wait_for_osc_ready).

Parameters
oscOscillator ID

Definition at line 244 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR2, RCC_CR2_HSI14ON, RCC_CR2_HSI48ON, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc  osc)

RCC Clear the Oscillator Ready Interrupt Flag.

Clear the interrupt flag that was set when a clock oscillator became ready to use.

Parameters
oscOscillator ID

Definition at line 57 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSI14RDYC, RCC_CIR_HSI48RDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc  osc)

RCC Disable the Oscillator Ready Interrupt.

Parameters
oscOscillator ID

Definition at line 123 of file rcc.c.

References RCC_CIR, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc  osc)

RCC Enable the Oscillator Ready Interrupt.

Parameters
oscOscillator ID

Definition at line 90 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSI14RDYIE, RCC_CIR_HSI48RDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc  osc)

RCC Read the Oscillator Ready Interrupt Flag.

Parameters
oscOscillator ID
Returns
int. Boolean value for flag set.

Definition at line 157 of file rcc.c.

References cm3_assert_not_reached, RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSI14RDYF, RCC_CIR_HSI48RDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken  clken)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken  clken)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), and st_usbfs_v2_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst  rst)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst  rst)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset().

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◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst  rst)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset ( volatile uint32_t *  reg,
uint32_t  clear_reset 
)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]clear_resetUnsigned int32. Logical OR of all resets to be removed:

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be used for disabling.

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be set

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset ( volatile uint32_t *  reg,
uint32_t  reset 
)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]resetUnsigned int32. Logical OR of all resets.

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t  hpre)

RCC Set the AHB Prescale Factor.

Parameters
[in]hpreUnsigned int32. AHB prescale factor RCC_CFGR AHB prescale Factors

Definition at line 484 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_set_i2c_clock_hsi()

void rcc_set_i2c_clock_hsi ( uint32_t  i2c)

Definition at line 524 of file rcc.c.

References I2C1, and RCC_CFGR3.

◆ rcc_set_i2c_clock_sysclk()

void rcc_set_i2c_clock_sysclk ( uint32_t  i2c)

Definition at line 531 of file rcc.c.

References I2C1, RCC_CFGR3, and RCC_CFGR3_I2C1SW.

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t  mcosrc)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters
[in]mcosrcthe unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_pll_multiplication_factor()

void rcc_set_pll_multiplication_factor ( uint32_t  mul)

RCC Set the PLL Multiplication Factor.

Note
This only has effect when the PLL is disabled.
Parameters
[in]mulUnsigned int32. PLL multiplication factor PLLMUL: PLL multiplication factor

Definition at line 434 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t  pllsrc)

RCC Set the PLL Clock Source.

Note
This only has effect when the PLL is disabled.
Parameters
[in]pllsrcUnsigned int32. PLL clock source PLLSRC: PLL Clock source

Definition at line 447 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_set_pllxtpre()

void rcc_set_pllxtpre ( uint32_t  pllxtpre)

RCC Set the HSE Frequency Divider used as PLL Clock Source.

Note
This only has effect when the PLL is disabled.
Parameters
[in]pllxtpreUnsigned int32. HSE division factor PLLXTPRE: HSE divider for PLL source

Definition at line 461 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz().

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◆ rcc_set_ppre()

void rcc_set_ppre ( uint32_t  ppre)

RCC Set the APB Prescale Factor.

Parameters
[in]ppreUnsigned int32. APB prescale factor RCC_CFGR APB prescale Factors

Definition at line 473 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_set_prediv()

void rcc_set_prediv ( uint32_t  prediv)

Set PLL Source pre-divider CAUTION.

On F03x and F05, prediv only applies to HSE source. On others, this is after source selection. See also f3.

Parameters
[in]predivdivision by prediv+1 PLL source predividers

Definition at line 495 of file rcc.c.

References RCC_CFGR2.

◆ rcc_set_rtc_clock_source()

void rcc_set_rtc_clock_source ( enum rcc_osc  clk)

RCC Set the Source for the RTC clock.

Parameters
[in]clkRTC clock source. Only HSE/32, LSE and LSI.

Definition at line 408 of file rcc.c.

References RCC_BDCR, RCC_BDCR_RTCSEL_HSE, RCC_BDCR_RTCSEL_LSE, RCC_BDCR_RTCSEL_LSI, RCC_HSE, RCC_LSE, and RCC_LSI.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( enum rcc_osc  clk)

RCC Set the Source for the System Clock.

Parameters
clkOscillator ID. Only HSE, LSE and PLL have effect.

Definition at line 334 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSI, RCC_CFGR_SW_HSI48, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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◆ rcc_set_usbclk_source()

void rcc_set_usbclk_source ( enum rcc_osc  clk)

RCC Set the Source for the USB Clock.

Parameters
clkOscillator ID. Only HSI48 or PLL have effect.

Definition at line 363 of file rcc.c.

References RCC_CFGR3, RCC_CFGR3_USBSW, RCC_HSE, RCC_HSI, RCC_HSI14, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_system_clock_source()

enum rcc_osc rcc_system_clock_source ( void  )

RCC Get the System Clock Source.

Returns
current system clock source

Definition at line 507 of file rcc.c.

References cm3_assert_not_reached, RCC_CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI, RCC_CFGR_SWS_HSI48, RCC_CFGR_SWS_PLL, RCC_HSE, RCC_HSI, RCC_HSI48, and RCC_PLL.

◆ rcc_usb_clock_source()

enum rcc_osc rcc_usb_clock_source ( void  )

RCC Get the USB Clock Source.

Returns
Currently selected USB clock source

Definition at line 549 of file rcc.c.

References RCC_CFGR3, RCC_CFGR3_USBSW, RCC_HSI48, and RCC_PLL.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc  osc)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters
oscOscillator ID

Definition at line 227 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), and rcc_clock_setup_in_hsi_out_48mhz().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency
extern

Definition at line 45 of file rcc.c.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_get_i2c_clk_freq(), and rcc_get_usart_clksel_freq().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency
extern

Definition at line 46 of file rcc.c.

Referenced by rcc_clock_setup_in_hse_8mhz_out_48mhz(), rcc_clock_setup_in_hsi48_out_48mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), rcc_get_usart_clk_freq(), and rcc_get_usart_clksel_freq().