libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
can.c
Go to the documentation of this file.
1/** @defgroup can_file CAN
2
3@ingroup STM32F_files
4
5@brief <b>libopencm3 STM32Fxxx CAN</b>
6
7@version 1.0.0
8
9@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
10
11@date 12 November 2012
12
13Devices can have up to two CAN peripherals. The peripherals support up to 1MBit
14transmission rate. The peripheral has several filters for incoming messages that
15can be distributed between two FIFOs and three transmit mailboxes.
16
17LGPL License Terms @ref lgpl_license
18*/
19/*
20 * This file is part of the libopencm3 project.
21 *
22 * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
23 *
24 * This library is free software: you can redistribute it and/or modify
25 * it under the terms of the GNU Lesser General Public License as published by
26 * the Free Software Foundation, either version 3 of the License, or
27 * (at your option) any later version.
28 *
29 * This library is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU Lesser General Public License for more details.
33 *
34 * You should have received a copy of the GNU Lesser General Public License
35 * along with this library. If not, see <http://www.gnu.org/licenses/>.
36 */
37
40
41/* Timeout for CAN INIT acknowledge
42 * this value is difficult to define.
43 * INIT is set latest after finishing the current transfer.
44 * Assuming the lowest CAN speed of 100kbps one CAN frame may take about 1.6ms
45 * WAIT loop timeout varies on compiler switches, optimization, CPU architecture
46 * and CPU speed
47 *
48 * The same timeout value is used for leaving INIT where the longest time is
49 * 11 bits(110 us on 100 kbps).
50 */
51#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
52
53/*---------------------------------------------------------------------------*/
54/** @brief CAN Reset
55
56The CAN peripheral and all its associated configuration registers are placed in
57the reset condition. The reset is effective via the RCC peripheral reset
58system.
59
60@param[in] canport Unsigned int32. CAN block register address base @ref
61can_reg_base.
62 */
63void can_reset(uint32_t canport)
64{
65 if (canport == CAN1) {
67 } else {
68#if defined(BX_CAN2_BASE)
69 rcc_periph_reset_pulse(RST_CAN2);
70#endif
71 }
72}
73
74/*---------------------------------------------------------------------------*/
75/** @brief CAN Init
76
77Initialize the selected CAN peripheral block.
78
79@param[in] canport Unsigend int32. CAN register base address @ref can_reg_base.
80@param[in] ttcm bool. Time triggered communication mode.
81@param[in] abom bool. Automatic bus-off management.
82@param[in] awum bool. Automatic wakeup mode.
83@param[in] nart bool. No automatic retransmission.
84@param[in] rflm bool. Receive FIFO locked mode.
85@param[in] txfp bool. Transmit FIFO priority.
86@param[in] sjw Unsigned int32. Resynchronization time quanta jump width.
87@param[in] ts1 Unsigned int32. Time segment 1 time quanta width.
88@param[in] ts2 Unsigned int32. Time segment 2 time quanta width.
89@param[in] brp Unsigned int32. Baud rate prescaler.
90@returns int 0 on success, 1 on initialization failure.
91*/
92int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
93 bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
94 uint32_t brp, bool loopback, bool silent)
95{
96 volatile uint32_t wait_ack;
97 int ret = 0;
98
99 /* Exit from sleep mode. */
100 CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
101
102 /* Request initialization "enter". */
103 CAN_MCR(canport) |= CAN_MCR_INRQ;
104
105 /* Wait for acknowledge. */
106 wait_ack = CAN_MSR_INAK_TIMEOUT;
107 while ((--wait_ack) &&
108 ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK));
109
110 /* Check the acknowledge. */
111 if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
112 return 1;
113 }
114
115 /* clear can timing bits */
116 CAN_BTR(canport) = 0;
117
118 /* Set the automatic bus-off management. */
119 if (ttcm) {
120 CAN_MCR(canport) |= CAN_MCR_TTCM;
121 } else {
122 CAN_MCR(canport) &= ~CAN_MCR_TTCM;
123 }
124
125 if (abom) {
126 CAN_MCR(canport) |= CAN_MCR_ABOM;
127 } else {
128 CAN_MCR(canport) &= ~CAN_MCR_ABOM;
129 }
130
131 if (awum) {
132 CAN_MCR(canport) |= CAN_MCR_AWUM;
133 } else {
134 CAN_MCR(canport) &= ~CAN_MCR_AWUM;
135 }
136
137 if (nart) {
138 CAN_MCR(canport) |= CAN_MCR_NART;
139 } else {
140 CAN_MCR(canport) &= ~CAN_MCR_NART;
141 }
142
143 if (rflm) {
144 CAN_MCR(canport) |= CAN_MCR_RFLM;
145 } else {
146 CAN_MCR(canport) &= ~CAN_MCR_RFLM;
147 }
148
149 if (txfp) {
150 CAN_MCR(canport) |= CAN_MCR_TXFP;
151 } else {
152 CAN_MCR(canport) &= ~CAN_MCR_TXFP;
153 }
154
155 if (silent) {
156 CAN_BTR(canport) |= CAN_BTR_SILM;
157 } else {
158 CAN_BTR(canport) &= ~CAN_BTR_SILM;
159 }
160
161 if (loopback) {
162 CAN_BTR(canport) |= CAN_BTR_LBKM;
163 } else {
164 CAN_BTR(canport) &= ~CAN_BTR_LBKM;
165 }
166
167 /* Set bit timings. */
168 CAN_BTR(canport) |= sjw | ts2 | ts1 |
169 ((brp - 1ul) & CAN_BTR_BRP_MASK);
170
171 /* Request initialization "leave". */
172 CAN_MCR(canport) &= ~CAN_MCR_INRQ;
173
174 /* Wait for acknowledge. */
175 wait_ack = CAN_MSR_INAK_TIMEOUT;
176 while ((--wait_ack) &&
177 ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK));
178
179 if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
180 ret = 1;
181 }
182
183 return ret;
184}
185
186/*---------------------------------------------------------------------------*/
187/** @brief CAN Filter Init
188
189Initialize incoming message filter and assign to FIFO.
190
191@param[in] nr Unsigned int32. ID number of the filter.
192@param[in] scale_32bit true for single 32bit, false for dual 16bit
193@param[in] id_list_mode true for id lists, false for id/mask
194@param[in] fr1 Unsigned int32. First filter register content.
195@param[in] fr2 Unsigned int32. Second filter register content.
196@param[in] fifo Unsigned int32. FIFO id.
197@param[in] enable bool. Enable filter?
198 */
199void can_filter_init(uint32_t nr, bool scale_32bit,
200 bool id_list_mode, uint32_t fr1, uint32_t fr2,
201 uint32_t fifo, bool enable)
202{
203 uint32_t filter_select_bit = 0x00000001 << nr;
204
205 /* Request initialization "enter". */
207
208 /* Deactivate the filter. */
209 CAN_FA1R(CAN1) &= ~filter_select_bit;
210
211 if (scale_32bit) {
212 /* Set 32-bit scale for the filter. */
213 CAN_FS1R(CAN1) |= filter_select_bit;
214 } else {
215 /* Set 16-bit scale for the filter. */
216 CAN_FS1R(CAN1) &= ~filter_select_bit;
217 }
218
219 if (id_list_mode) {
220 /* Set filter mode to ID list mode. */
221 CAN_FM1R(CAN1) |= filter_select_bit;
222 } else {
223 /* Set filter mode to id/mask mode. */
224 CAN_FM1R(CAN1) &= ~filter_select_bit;
225 }
226
227 /* Set the first filter register. */
228 CAN_FiR1(CAN1, nr) = fr1;
229
230 /* Set the second filter register. */
231 CAN_FiR2(CAN1, nr) = fr2;
232
233 /* Select FIFO0 or FIFO1 as filter assignement. */
234 if (fifo) {
235 CAN_FFA1R(CAN1) |= filter_select_bit; /* FIFO1 */
236 } else {
237 CAN_FFA1R(CAN1) &= ~filter_select_bit; /* FIFO0 */
238 }
239
240 if (enable) {
241 CAN_FA1R(CAN1) |= filter_select_bit; /* Activate filter. */
242 }
243
244 /* Request initialization "leave". */
245 CAN_FMR(CAN1) &= ~CAN_FMR_FINIT;
246}
247
248/*---------------------------------------------------------------------------*/
249/** @brief CAN Initialize a 16bit Message ID Mask Filter
250
251@param[in] nr Unsigned int32. ID number of the filter.
252@param[in] id1 Unsigned int16. First message ID to filter.
253@param[in] mask1 Unsigned int16. First message ID bit mask.
254@param[in] id2 Unsigned int16. Second message ID to filter.
255@param[in] mask2 Unsigned int16. Second message ID bit mask.
256@param[in] fifo Unsigned int32. FIFO id.
257@param[in] enable bool. Enable filter?
258 */
259void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1,
260 uint16_t mask1, uint16_t id2,
261 uint16_t mask2, uint32_t fifo, bool enable)
262{
263 can_filter_init(nr, false, false,
264 ((uint32_t)mask1 << 16) | (uint32_t)id1,
265 ((uint32_t)mask2 << 16) | (uint32_t)id2, fifo, enable);
266}
267
268/*---------------------------------------------------------------------------*/
269/** @brief CAN Initialize a 32bit Message ID Mask Filter
270
271@param[in] nr Unsigned int32. ID number of the filter.
272@param[in] id Unsigned int32. Message ID to filter.
273@param[in] mask Unsigned int32. Message ID bit mask.
274@param[in] fifo Unsigned int32. FIFO id.
275@param[in] enable bool. Enable filter?
276 */
277void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id,
278 uint32_t mask, uint32_t fifo, bool enable)
279{
280 can_filter_init(nr, true, false, id, mask, fifo, enable);
281}
282
283/*---------------------------------------------------------------------------*/
284/** @brief CAN Initialize a 16bit Message ID List Filter
285
286@param[in] nr Unsigned int32. ID number of the filter.
287@param[in] id1 Unsigned int16. First message ID to match.
288@param[in] id2 Unsigned int16. Second message ID to match.
289@param[in] id3 Unsigned int16. Third message ID to match.
290@param[in] id4 Unsigned int16. Fourth message ID to match.
291@param[in] fifo Unsigned int32. FIFO id.
292@param[in] enable bool. Enable filter?
293 */
295 uint16_t id1, uint16_t id2,
296 uint16_t id3, uint16_t id4,
297 uint32_t fifo, bool enable)
298{
299 can_filter_init(nr, false, true,
300 ((uint32_t)id1 << 16) | (uint32_t)id2,
301 ((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable);
302}
303
304/*---------------------------------------------------------------------------*/
305/** @brief CAN Initialize a 32bit Message ID List Filter
306
307@param[in] nr Unsigned int32. ID number of the filter.
308@param[in] id1 Unsigned int32. First message ID to match.
309@param[in] id2 Unsigned int32. Second message ID to match.
310@param[in] fifo Unsigned int32. FIFO id.
311@param[in] enable bool. Enable filter?
312 */
314 uint32_t id1, uint32_t id2,
315 uint32_t fifo, bool enable)
316{
317 can_filter_init(nr, true, true, id1, id2, fifo, enable);
318}
319
320/*---------------------------------------------------------------------------*/
321/** @brief CAN Enable IRQ
322
323@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
324@param[in] irq Unsigned int32. IRQ bit(s).
325 */
326void can_enable_irq(uint32_t canport, uint32_t irq)
327{
328 CAN_IER(canport) |= irq;
329}
330
331/*---------------------------------------------------------------------------*/
332/** @brief CAN Disable IRQ
333
334@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
335@param[in] irq Unsigned int32. IRQ bit(s).
336 */
337void can_disable_irq(uint32_t canport, uint32_t irq)
338{
339 CAN_IER(canport) &= ~irq;
340}
341
342/*---------------------------------------------------------------------------*/
343/** @brief CAN Transmit Message
344
345@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
346@param[in] id Unsigned int32. Message ID.
347@param[in] ext bool. Extended message ID?
348@param[in] rtr bool. Request transmit?
349@param[in] length Unsigned int8. Message payload length.
350@param[in] data Unsigned int8[]. Message payload data.
351@returns int 0, 1 or 2 on success and depending on which outgoing mailbox got
352selected. -1 if no mailbox was available and no transmission got queued.
353 */
354int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
355 uint8_t length, uint8_t *data)
356{
357 int ret = 0;
358 uint32_t mailbox = 0;
359 union {
360 uint8_t data8[4];
361 uint32_t data32;
362 } tdlxr, tdhxr;
363
364 /* Check which transmit mailbox is empty if any. */
365 if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
366 ret = 0;
367 mailbox = CAN_MBOX0;
368 } else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) {
369 ret = 1;
370 mailbox = CAN_MBOX1;
371 } else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) {
372 ret = 2;
373 mailbox = CAN_MBOX2;
374 } else {
375 ret = -1;
376 }
377
378 /* If we have no empty mailbox return with an error. */
379 if (ret == -1) {
380 return ret;
381 }
382
383 if (ext) {
384 /* Set extended ID. */
385 CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) |
387 } else {
388 /* Set standard ID. */
389 CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT;
390 }
391
392 /* Set/clear remote transmission request bit. */
393 if (rtr) {
394 CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
395 }
396
397 /* Set the DLC. */
398 CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
399 CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK);
400
401 switch (length) {
402 case 8:
403 tdhxr.data8[3] = data[7];
404 /* fall through */
405 case 7:
406 tdhxr.data8[2] = data[6];
407 /* fall through */
408 case 6:
409 tdhxr.data8[1] = data[5];
410 /* fall through */
411 case 5:
412 tdhxr.data8[0] = data[4];
413 /* fall through */
414 case 4:
415 tdlxr.data8[3] = data[3];
416 /* fall through */
417 case 3:
418 tdlxr.data8[2] = data[2];
419 /* fall through */
420 case 2:
421 tdlxr.data8[1] = data[1];
422 /* fall through */
423 case 1:
424 tdlxr.data8[0] = data[0];
425 /* fall through */
426 default:
427 break;
428 }
429 /* Set the data. */
430
431 CAN_TDLxR(canport, mailbox) = tdlxr.data32;
432 CAN_TDHxR(canport, mailbox) = tdhxr.data32;
433
434 /* Request transmission. */
435 CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ;
436
437 return ret;
438}
439
440/*---------------------------------------------------------------------------*/
441/** @brief CAN Release FIFO
442
443@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
444@param[in] fifo Unsigned int8. FIFO id.
445 */
446void can_fifo_release(uint32_t canport, uint8_t fifo)
447{
448 if (fifo == 0) {
449 CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
450 } else {
451 CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
452 }
453}
454
455/*---------------------------------------------------------------------------*/
456/** @brief CAN Receive Message
457
458@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
459@param[in] fifo Unsigned int8. FIFO id.
460@param[in] release bool. Release the FIFO automatically after coping data out.
461@param[out] id Unsigned int32 pointer. Message ID.
462@param[out] ext bool pointer. The message ID is extended?
463@param[out] rtr bool pointer. Request of transmission?
464@param[out] fmi Unsigned int8 pointer. ID of the matched filter.
465@param[out] length Unsigned int8 pointer. Length of message payload.
466@param[out] data Unsigned int8[]. Message payload data.
467@param[out] timestamp Pointer to store the message timestamp.
468 Only valid on time triggered CAN. Use NULL to ignore.
469 */
470void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
471 bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length,
472 uint8_t *data, uint16_t *timestamp)
473{
474 uint32_t fifo_id = 0;
475 union {
476 uint8_t data8[4];
477 uint32_t data32;
478 } rdlxr, rdhxr;
479 const uint32_t fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
480
481 fifo_id = fifoid_array[fifo];
482
483 /* Get type of CAN ID and CAN ID. */
484 if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
485 *ext = true;
486 /* Get extended CAN ID. */
487 *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) &
489 } else {
490 *ext = false;
491 /* Get standard CAN ID. */
492 *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) &
494 }
495
496 /* Get remote transmit flag. */
497 if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
498 *rtr = true;
499 } else {
500 *rtr = false;
501 }
502
503 /* Get filter match ID. */
504 *fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >>
506
507 /* Get data length. */
508 *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
509 /* accelerate reception by copying the CAN data from the controller
510 * memory to the fast internal RAM
511 */
512
513 if (timestamp) {
514 *timestamp = (CAN_RDTxR(canport, fifo_id) &
516 }
517
518 rdlxr.data32 = CAN_RDLxR(canport, fifo_id);
519 rdhxr.data32 = CAN_RDHxR(canport, fifo_id);
520 /* */
521 /* Get data.
522 * Byte wise copy is needed because we do not know the alignment
523 * of the input buffer.
524 * Here copying 8 bytes unconditionally is faster than using loop
525 *
526 * It is OK to copy all 8 bytes because the upper layer must be
527 * prepared for data length bigger expected.
528 * In contrary the driver has no information about the intended size.
529 * This could be different if the max length would be handed over
530 * to the function, but it is not the case
531 */
532 data[0] = rdlxr.data8[0];
533 data[1] = rdlxr.data8[1];
534 data[2] = rdlxr.data8[2];
535 data[3] = rdlxr.data8[3];
536 data[4] = rdhxr.data8[0];
537 data[5] = rdhxr.data8[1];
538 data[6] = rdhxr.data8[2];
539 data[7] = rdhxr.data8[3];
540
541 /* Release the FIFO. */
542 if (release) {
543 can_fifo_release(canport, fifo);
544 }
545}
546
547bool can_available_mailbox(uint32_t canport)
548{
549 return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2);
550}
#define CAN_MSR_INAK_TIMEOUT
Definition: can.c:51
#define CAN_TDLxR(can_base, mbox)
Definition: can.h:99
#define CAN_MCR_INRQ
Definition: can.h:201
bool can_available_mailbox(uint32_t canport)
Definition: can.c:547
void can_filter_init(uint32_t nr, bool scale_32bit, bool id_list_mode, uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
CAN Filter Init.
Definition: can.c:199
#define CAN_TDTxR(can_base, mbox)
Definition: can.h:93
#define CAN_MCR_NART
Definition: can.h:189
#define CAN_MSR_INAK
Definition: can.h:234
#define CAN_FM1R(can_base)
Definition: can.h:136
#define CAN_FMR(can_base)
Definition: can.h:133
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length, uint8_t *data, uint16_t *timestamp)
CAN Receive Message.
Definition: can.c:470
#define CAN_MCR_TTCM
Definition: can.h:180
#define CAN_MCR_TXFP
Definition: can.h:195
#define CAN_RIxR_IDE
Definition: can.h:546
#define CAN_TSR(can_base)
Definition: can.h:61
#define CAN_MBOX0
Definition: can.h:80
#define CAN_RIxR_RTR
Definition: can.h:549
#define CAN_MCR_RFLM
Definition: can.h:192
#define CAN_MCR(can_base)
Definition: can.h:57
#define CAN_RIxR_EXID_MASK
Definition: can.h:542
#define CAN_RDTxR_TIME_SHIFT
Definition: can.h:557
#define CAN_TSR_TME1
Definition: can.h:251
#define CAN_FMR_FINIT
Definition: can.h:597
#define CAN_FiR1(can_base, bank)
Definition: can.h:162
#define CAN_TDTxR_DLC_MASK
Definition: can.h:518
#define CAN_RF1R_RFOM1
Definition: can.h:333
#define CAN_RDTxR_TIME_MASK
Definition: can.h:556
void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1, uint32_t id2, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID List Filter.
Definition: can.c:313
#define CAN_RDTxR_FMI_MASK
Definition: can.h:560
#define CAN_RIxR(can_base, fifo)
Definition: can.h:111
void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID List Filter.
Definition: can.c:294
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp, bool loopback, bool silent)
CAN Init.
Definition: can.c:92
#define CAN_TIxR_RTR
Definition: can.h:499
#define CAN_TIxR_IDE
Definition: can.h:496
#define CAN_BTR_BRP_MASK
Definition: can.h:483
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
CAN Transmit Message.
Definition: can.c:354
#define CAN_MBOX1
Definition: can.h:81
#define CAN_FIFO0
Definition: can.h:83
void can_disable_irq(uint32_t canport, uint32_t irq)
CAN Disable IRQ.
Definition: can.c:337
#define CAN_RF0R(can_base)
Definition: can.h:64
#define CAN_RDLxR(can_base, fifo)
Definition: can.h:121
void can_reset(uint32_t canport)
CAN Reset.
Definition: can.c:63
#define CAN_TDHxR(can_base, mbox)
Definition: can.h:105
#define CAN_MCR_AWUM
Definition: can.h:186
#define CAN_BTR_SILM
Definition: can.h:431
void can_enable_irq(uint32_t canport, uint32_t irq)
CAN Enable IRQ.
Definition: can.c:326
void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1, uint16_t mask1, uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID Mask Filter.
Definition: can.c:259
#define CAN_RIxR_EXID_SHIFT
Definition: can.h:543
#define CAN_BTR(can_base)
Definition: can.h:73
#define CAN_RIxR_STID_MASK
Definition: can.h:538
#define CAN_FS1R(can_base)
Definition: can.h:141
#define CAN_TIxR_STID_SHIFT
Definition: can.h:489
#define CAN_BTR_LBKM
Definition: can.h:434
#define CAN_RDHxR(can_base, fifo)
Definition: can.h:126
#define CAN_FA1R(can_base)
Definition: can.h:151
void can_fifo_release(uint32_t canport, uint8_t fifo)
CAN Release FIFO.
Definition: can.c:446
#define CAN_TIxR_TXRQ
Definition: can.h:502
#define CAN_FiR2(can_base, bank)
Definition: can.h:164
#define CAN_TSR_TME0
Definition: can.h:254
#define CAN_MCR_ABOM
Definition: can.h:183
#define CAN_MSR(can_base)
Definition: can.h:59
#define CAN_RDTxR_FMI_SHIFT
Definition: can.h:561
#define CAN_TIxR_EXID_SHIFT
Definition: can.h:493
#define CAN_IER(can_base)
Definition: can.h:69
#define CAN_TIxR(can_base, mbox)
Definition: can.h:87
void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id, uint32_t mask, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID Mask Filter.
Definition: can.c:277
#define CAN_RDTxR(can_base, fifo)
Definition: can.h:116
#define CAN_RDTxR_DLC_MASK
Definition: can.h:566
#define CAN_MBOX2
Definition: can.h:82
#define CAN_TSR_TME2
Definition: can.h:248
#define CAN_FFA1R(can_base)
Definition: can.h:146
#define CAN_RIxR_STID_SHIFT
Definition: can.h:539
#define CAN_FIFO1
Definition: can.h:84
#define CAN_RF1R(can_base)
Definition: can.h:66
#define CAN1
Definition: can.h:50
void rcc_periph_reset_pulse(enum rcc_periph_rst rst)
Reset Peripheral, pulsed.
@ RST_CAN1
Definition: f0/rcc.h:534