libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
can.h
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1 /** @defgroup can_defines CAN defines
2 
3 @ingroup STM32F_defines
4 
5 @brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
6 
7 @version 1.0.0
8 
9 @author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
10 
11 @date 12 November 2012
12 
13 LGPL License Terms @ref lgpl_license
14 */
15 /*
16  * This file is part of the libopencm3 project.
17  *
18  * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
19  *
20  * This library is free software: you can redistribute it and/or modify
21  * it under the terms of the GNU Lesser General Public License as published by
22  * the Free Software Foundation, either version 3 of the License, or
23  * (at your option) any later version.
24  *
25  * This library is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28  * GNU Lesser General Public License for more details.
29  *
30  * You should have received a copy of the GNU Lesser General Public License
31  * along with this library. If not, see <http://www.gnu.org/licenses/>.
32  */
33 
34 #ifndef LIBOPENCM3_CAN_H
35 #define LIBOPENCM3_CAN_H
36 
38 #include <libopencm3/cm3/common.h>
39 
40 /**@{*/
41 
42 /* --- Convenience macros -------------------------------------------------- */
43 
44 /* CAN register base addresses (for convenience) */
45 /*****************************************************************************/
46 /** @defgroup can_reg_base CAN register base address
47 @ingroup can_defines
48 
49 @{*/
50 #define CAN1 BX_CAN1_BASE
51 #define CAN2 BX_CAN2_BASE
52 /**@}*/
53 
54 /* --- CAN registers ------------------------------------------------------- */
55 
56 /* CAN master control register (CAN_MCR) */
57 #define CAN_MCR(can_base) MMIO32((can_base) + 0x000)
58 /* CAN master status register (CAN_MSR) */
59 #define CAN_MSR(can_base) MMIO32((can_base) + 0x004)
60 /* CAN transmit status register (CAN_TSR) */
61 #define CAN_TSR(can_base) MMIO32((can_base) + 0x008)
62 
63 /* CAN receive FIFO 0 register (CAN_RF0R) */
64 #define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C)
65 /* CAN receive FIFO 1 register (CAN_RF1R) */
66 #define CAN_RF1R(can_base) MMIO32((can_base) + 0x010)
67 
68 /* CAN interrupt enable register (CAN_IER) */
69 #define CAN_IER(can_base) MMIO32((can_base) + 0x014)
70 /* CAN error status register (CAN_ESR) */
71 #define CAN_ESR(can_base) MMIO32((can_base) + 0x018)
72 /* CAN bit timing register (CAN_BTR) */
73 #define CAN_BTR(can_base) MMIO32((can_base) + 0x01C)
74 
75 /* Registers in the offset range 0x020 to 0x17F are reserved. */
76 
77 /* --- CAN mailbox registers ----------------------------------------------- */
78 
79 /* CAN mailbox / FIFO register offsets */
80 #define CAN_MBOX0 0x180
81 #define CAN_MBOX1 0x190
82 #define CAN_MBOX2 0x1A0
83 #define CAN_FIFO0 0x1B0
84 #define CAN_FIFO1 0x1C0
85 
86 /* CAN TX mailbox identifier register (CAN_TIxR) */
87 #define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0)
88 #define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
89 #define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
90 #define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
91 
92 /* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
93 #define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4)
94 #define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0)
95 #define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1)
96 #define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2)
97 
98 /* CAN mailbox data low register (CAN_TDLxR) */
99 #define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8)
100 #define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0)
101 #define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1)
102 #define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2)
103 
104 /* CAN mailbox data high register (CAN_TDHxR) */
105 #define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC)
106 #define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0)
107 #define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1)
108 #define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2)
109 
110 /* CAN RX FIFO identifier register (CAN_RIxR) */
111 #define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0)
112 #define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0)
113 #define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1)
114 
115 /* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
116 #define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4)
117 #define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0)
118 #define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1)
119 
120 /* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
121 #define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8)
122 #define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0)
123 #define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1)
124 
125 /* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
126 #define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC)
127 #define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0)
128 #define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1)
129 
130 /* --- CAN filter registers ------------------------------------------------ */
131 
132 /* CAN filter master register (CAN_FMR) */
133 #define CAN_FMR(can_base) MMIO32((can_base) + 0x200)
134 
135 /* CAN filter mode register (CAN_FM1R) */
136 #define CAN_FM1R(can_base) MMIO32((can_base) + 0x204)
137 
138 /* Register offset 0x208 is reserved. */
139 
140 /* CAN filter scale register (CAN_FS1R) */
141 #define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C)
142 
143 /* Register offset 0x210 is reserved. */
144 
145 /* CAN filter FIFO assignement register (CAN_FFA1R) */
146 #define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214)
147 
148 /* Register offset 0x218 is reserved. */
149 
150 /* CAN filter activation register (CAN_FA1R) */
151 #define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C)
152 
153 /* Register offset 0x220 is reserved. */
154 
155 /* Registers with offset 0x224 to 0x23F are reserved. */
156 
157 /* CAN filter bank registers (CAN_FiRx) */
158 /*
159  * Connectivity line devices have 28 banks so the bank ID spans 0..27
160  * all other devices have 14 banks so the bank ID spans 0..13.
161  */
162 #define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \
163  ((bank) * 0x8) + 0x0)
164 #define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \
165  ((bank) * 0x8) + 0x4)
166 
167 /* --- CAN_MCR values ------------------------------------------------------ */
168 
169 /* 31:17 Reserved, forced by hardware to 0 */
170 
171 /* DBF: Debug freeze */
172 #define CAN_MCR_DBF (1 << 16)
173 
174 /* RESET: bxCAN software master reset */
175 #define CAN_MCR_RESET (1 << 15)
176 
177 /* 14:8 Reserved, forced by hardware to 0 */
178 
179 /* TTCM: Time triggered communication mode */
180 #define CAN_MCR_TTCM (1 << 7)
181 
182 /* ABOM: Automatic bus-off management */
183 #define CAN_MCR_ABOM (1 << 6)
184 
185 /* AWUM: Automatic wakeup mode */
186 #define CAN_MCR_AWUM (1 << 5)
187 
188 /* NART: No automatic retransmission */
189 #define CAN_MCR_NART (1 << 4)
190 
191 /* RFLM: Receive FIFO locked mode */
192 #define CAN_MCR_RFLM (1 << 3)
193 
194 /* TXFP: Transmit FIFO priority */
195 #define CAN_MCR_TXFP (1 << 2)
196 
197 /* SLEEP: Sleep mode request */
198 #define CAN_MCR_SLEEP (1 << 1)
199 
200 /* INRQ: Initialization request */
201 #define CAN_MCR_INRQ (1 << 0)
202 
203 /* --- CAN_MSR values ------------------------------------------------------ */
204 
205 /* 31:12 Reserved, forced by hardware to 0 */
206 
207 /* RX: CAN Rx signal */
208 #define CAN_MSR_RX (1 << 11)
209 
210 /* SAMP: Last sample point */
211 #define CAN_MSR_SAMP (1 << 10)
212 
213 /* RXM: Receive mode */
214 #define CAN_MSR_RXM (1 << 9)
215 
216 /* TXM: Transmit mode */
217 #define CAN_MSR_TXM (1 << 8)
218 
219 /* 7:5 Reserved, forced by hardware to 0 */
220 
221 /* SLAKI: Sleep acknowledge interrupt */
222 #define CAN_MSR_SLAKI (1 << 4)
223 
224 /* WKUI: Wakeup interrupt */
225 #define CAN_MSR_WKUI (1 << 3)
226 
227 /* ERRI: Error interrupt */
228 #define CAN_MSR_ERRI (1 << 2)
229 
230 /* SLAK: Sleep acknowledge */
231 #define CAN_MSR_SLAK (1 << 1)
232 
233 /* INAK: Initialization acknowledge */
234 #define CAN_MSR_INAK (1 << 0)
235 
236 /* --- CAN_TSR values ------------------------------------------------------ */
237 
238 /* LOW2: Lowest priority flag for mailbox 2 */
239 #define CAN_TSR_LOW2 (1 << 31)
240 
241 /* LOW1: Lowest priority flag for mailbox 1 */
242 #define CAN_TSR_LOW1 (1 << 30)
243 
244 /* LOW0: Lowest priority flag for mailbox 0 */
245 #define CAN_TSR_LOW0 (1 << 29)
246 
247 /* TME2: Transmit mailbox 2 empty */
248 #define CAN_TSR_TME2 (1 << 28)
249 
250 /* TME1: Transmit mailbox 1 empty */
251 #define CAN_TSR_TME1 (1 << 27)
252 
253 /* TME0: Transmit mailbox 0 empty */
254 #define CAN_TSR_TME0 (1 << 26)
255 
256 /* CODE[1:0]: Mailbox code */
257 #define CAN_TSR_CODE_MASK (0x3 << 24)
258 
259 /* ABRQ2: Abort request for mailbox 2 */
260 #define CAN_TSR_ABRQ2 (1 << 23)
261 
262 /* 22:20 Reserved, forced by hardware to 0 */
263 
264 /* TERR2: Transmission error for mailbox 2 */
265 #define CAN_TSR_TERR2 (1 << 19)
266 
267 /* ALST2: Arbitration lost for mailbox 2 */
268 #define CAN_TSR_ALST2 (1 << 18)
269 
270 /* TXOK2: Transmission OK for mailbox 2 */
271 #define CAN_TSR_TXOK2 (1 << 17)
272 
273 /* RQCP2: Request completed mailbox 2 */
274 #define CAN_TSR_RQCP2 (1 << 16)
275 
276 /* ABRQ1: Abort request for mailbox 1 */
277 #define CAN_TSR_ABRQ1 (1 << 15)
278 
279 /* 14:12 Reserved, forced by hardware to 0 */
280 
281 /* TERR1: Transmission error for mailbox 1 */
282 #define CAN_TSR_TERR1 (1 << 11)
283 
284 /* ALST1: Arbitration lost for mailbox 1 */
285 #define CAN_TSR_ALST1 (1 << 10)
286 
287 /* TXOK1: Transmission OK for mailbox 1 */
288 #define CAN_TSR_TXOK1 (1 << 9)
289 
290 /* RQCP1: Request completed mailbox 1 */
291 #define CAN_TSR_RQCP1 (1 << 8)
292 
293 /* ABRQ0: Abort request for mailbox 0 */
294 #define CAN_TSR_ABRQ0 (1 << 7)
295 
296 /* 6:4 Reserved, forced by hardware to 0 */
297 
298 /* TERR0: Transmission error for mailbox 0 */
299 #define CAN_TSR_TERR0 (1 << 3)
300 
301 /* ALST0: Arbitration lost for mailbox 0 */
302 #define CAN_TSR_ALST0 (1 << 2)
303 
304 /* TXOK0: Transmission OK for mailbox 0 */
305 #define CAN_TSR_TXOK0 (1 << 1)
306 
307 /* RQCP0: Request completed mailbox 0 */
308 #define CAN_TSR_RQCP0 (1 << 0)
309 
310 /* --- CAN_RF0R values ----------------------------------------------------- */
311 
312 /* 31:6 Reserved, forced by hardware to 0 */
313 
314 /* RFOM0: Release FIFO 0 output mailbox */
315 #define CAN_RF0R_RFOM0 (1 << 5)
316 
317 /* FOVR0: FIFO 0 overrun */
318 #define CAN_RF0R_FOVR0 (1 << 4)
319 
320 /* FULL0: FIFO 0 full */
321 #define CAN_RF0R_FULL0 (1 << 3)
322 
323 /* 2 Reserved, forced by hardware to 0 */
324 
325 /* FMP0[1:0]: FIFO 0 message pending */
326 #define CAN_RF0R_FMP0_MASK (0x3 << 0)
327 
328 /* --- CAN_RF1R values ----------------------------------------------------- */
329 
330 /* 31:6 Reserved, forced by hardware to 0 */
331 
332 /* RFOM1: Release FIFO 1 output mailbox */
333 #define CAN_RF1R_RFOM1 (1 << 5)
334 
335 /* FOVR1: FIFO 1 overrun */
336 #define CAN_RF1R_FOVR1 (1 << 4)
337 
338 /* FULL1: FIFO 1 full */
339 #define CAN_RF1R_FULL1 (1 << 3)
340 
341 /* 2 Reserved, forced by hardware to 0 */
342 
343 /* FMP1[1:0]: FIFO 1 message pending */
344 #define CAN_RF1R_FMP1_MASK (0x3 << 0)
345 
346 /* --- CAN_IER values ------------------------------------------------------ */
347 
348 /* 32:18 Reserved, forced by hardware to 0 */
349 
350 /* SLKIE: Sleep interrupt enable */
351 #define CAN_IER_SLKIE (1 << 17)
352 
353 /* WKUIE: Wakeup interrupt enable */
354 #define CAN_IER_WKUIE (1 << 16)
355 
356 /* ERRIE: Error interrupt enable */
357 #define CAN_IER_ERRIE (1 << 15)
358 
359 /* 14:12 Reserved, forced by hardware to 0 */
360 
361 /* LECIE: Last error code interrupt enable */
362 #define CAN_IER_LECIE (1 << 11)
363 
364 /* BOFIE: Bus-off interrupt enable */
365 #define CAN_IER_BOFIE (1 << 10)
366 
367 /* EPVIE: Error passive interrupt enable */
368 #define CAN_IER_EPVIE (1 << 9)
369 
370 /* EWGIE: Error warning interrupt enable */
371 #define CAN_IER_EWGIE (1 << 8)
372 
373 /* 7 Reserved, forced by hardware to 0 */
374 
375 /* FOVIE1: FIFO overrun interrupt enable */
376 #define CAN_IER_FOVIE1 (1 << 6)
377 
378 /* FFIE1: FIFO full interrupt enable */
379 #define CAN_IER_FFIE1 (1 << 5)
380 
381 /* FMPIE1: FIFO message pending interrupt enable */
382 #define CAN_IER_FMPIE1 (1 << 4)
383 
384 /* FOVIE0: FIFO overrun interrupt enable */
385 #define CAN_IER_FOVIE0 (1 << 3)
386 
387 /* FFIE0: FIFO full interrupt enable */
388 #define CAN_IER_FFIE0 (1 << 2)
389 
390 /* FMPIE0: FIFO message pending interrupt enable */
391 #define CAN_IER_FMPIE0 (1 << 1)
392 
393 /* TMEIE: Transmit mailbox empty interrupt enable */
394 #define CAN_IER_TMEIE (1 << 0)
395 
396 /* --- CAN_ESR values ------------------------------------------------------ */
397 
398 /* REC[7:0]: Receive error counter */
399 #define CAN_ESR_REC_MASK (0xF << 24)
400 
401 /* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
402 #define CAN_ESR_TEC_MASK (0xF << 16)
403 
404 /* 15:7 Reserved, forced by hardware to 0 */
405 
406 /* LEC[2:0]: Last error code */
407 #define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
408 #define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
409 #define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
410 #define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
411 #define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
412 #define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
413 #define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
414 #define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
415 #define CAN_ESR_LEC_MASK (0x7 << 4)
416 
417 /* 3 Reserved, forced by hardware to 0 */
418 
419 /* BOFF: Bus-off flag */
420 #define CAN_ESR_BOFF (1 << 2)
421 
422 /* EPVF: Error passive flag */
423 #define CAN_ESR_EPVF (1 << 1)
424 
425 /* EWGF: Error warning flag */
426 #define CAN_ESR_EWGF (1 << 0)
427 
428 /* --- CAN_BTR values ------------------------------------------------------ */
429 
430 /* SILM: Silent mode (debug) */
431 #define CAN_BTR_SILM (1 << 31)
432 
433 /* LBKM: Loop back mode (debug) */
434 #define CAN_BTR_LBKM (1 << 30)
435 
436 /* 29:26 Reserved, forced by hardware to 0 */
437 
438 /* SJW[1:0]: Resynchronization jump width */
439 #define CAN_BTR_SJW_1TQ (0x0 << 24)
440 #define CAN_BTR_SJW_2TQ (0x1 << 24)
441 #define CAN_BTR_SJW_3TQ (0x2 << 24)
442 #define CAN_BTR_SJW_4TQ (0x3 << 24)
443 #define CAN_BTR_SJW_MASK (0x3 << 24)
444 #define CAN_BTR_SJW_SHIFT 24
445 
446 /* 23 Reserved, forced by hardware to 0 */
447 
448 /* TS2[2:0]: Time segment 2 */
449 #define CAN_BTR_TS2_1TQ (0x0 << 20)
450 #define CAN_BTR_TS2_2TQ (0x1 << 20)
451 #define CAN_BTR_TS2_3TQ (0x2 << 20)
452 #define CAN_BTR_TS2_4TQ (0x3 << 20)
453 #define CAN_BTR_TS2_5TQ (0x4 << 20)
454 #define CAN_BTR_TS2_6TQ (0x5 << 20)
455 #define CAN_BTR_TS2_7TQ (0x6 << 20)
456 #define CAN_BTR_TS2_8TQ (0x7 << 20)
457 #define CAN_BTR_TS2_MASK (0x7 << 20)
458 #define CAN_BTR_TS2_SHIFT 20
459 
460 /* TS1[3:0]: Time segment 1 */
461 #define CAN_BTR_TS1_1TQ (0x0 << 16)
462 #define CAN_BTR_TS1_2TQ (0x1 << 16)
463 #define CAN_BTR_TS1_3TQ (0x2 << 16)
464 #define CAN_BTR_TS1_4TQ (0x3 << 16)
465 #define CAN_BTR_TS1_5TQ (0x4 << 16)
466 #define CAN_BTR_TS1_6TQ (0x5 << 16)
467 #define CAN_BTR_TS1_7TQ (0x6 << 16)
468 #define CAN_BTR_TS1_8TQ (0x7 << 16)
469 #define CAN_BTR_TS1_9TQ (0x8 << 16)
470 #define CAN_BTR_TS1_10TQ (0x9 << 16)
471 #define CAN_BTR_TS1_11TQ (0xA << 16)
472 #define CAN_BTR_TS1_12TQ (0xB << 16)
473 #define CAN_BTR_TS1_13TQ (0xC << 16)
474 #define CAN_BTR_TS1_14TQ (0xD << 16)
475 #define CAN_BTR_TS1_15TQ (0xE << 16)
476 #define CAN_BTR_TS1_16TQ (0xF << 16)
477 #define CAN_BTR_TS1_MASK (0xF << 16)
478 #define CAN_BTR_TS1_SHIFT 16
479 
480 /* 15:10 Reserved, forced by hardware to 0 */
481 
482 /* BRP[9:0]: Baud rate prescaler */
483 #define CAN_BTR_BRP_MASK (0x3FFUL << 0)
484 
485 /* --- CAN_TIxR values ------------------------------------------------------ */
486 
487 /* STID[10:0]: Standard identifier */
488 #define CAN_TIxR_STID_MASK (0x7FF << 21)
489 #define CAN_TIxR_STID_SHIFT 21
490 
491 /* EXID[15:0]: Extended identifier */
492 #define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
493 #define CAN_TIxR_EXID_SHIFT 3
494 
495 /* IDE: Identifier extension */
496 #define CAN_TIxR_IDE (1 << 2)
497 
498 /* RTR: Remote transmission request */
499 #define CAN_TIxR_RTR (1 << 1)
500 
501 /* TXRQ: Transmit mailbox request */
502 #define CAN_TIxR_TXRQ (1 << 0)
503 
504 /* --- CAN_TDTxR values ----------------------------------------------------- */
505 
506 /* TIME[15:0]: Message time stamp */
507 #define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
508 #define CAN_TDTxR_TIME_SHIFT 15
509 
510 /* 15:6 Reserved, forced by hardware to 0 */
511 
512 /* TGT: Transmit global time */
513 #define CAN_TDTxR_TGT (1 << 5)
514 
515 /* 7:4 Reserved, forced by hardware to 0 */
516 
517 /* DLC[3:0]: Data length code */
518 #define CAN_TDTxR_DLC_MASK (0xF << 0)
519 #define CAN_TDTxR_DLC_SHIFT 0
520 
521 /* --- CAN_TDLxR values ----------------------------------------------------- */
522 
523 /* DATA3[7:0]: Data byte 3 */
524 /* DATA2[7:0]: Data byte 2 */
525 /* DATA1[7:0]: Data byte 1 */
526 /* DATA0[7:0]: Data byte 0 */
527 
528 /* --- CAN_TDHxR values ----------------------------------------------------- */
529 
530 /* DATA7[7:0]: Data byte 7 */
531 /* DATA6[7:0]: Data byte 6 */
532 /* DATA5[7:0]: Data byte 5 */
533 /* DATA4[7:0]: Data byte 4 */
534 
535 /* --- CAN_RIxR values ------------------------------------------------------ */
536 
537 /* STID[10:0]: Standard identifier */
538 #define CAN_RIxR_STID_MASK (0x7FF)
539 #define CAN_RIxR_STID_SHIFT 21
540 
541 /* EXID[15:0]: Extended identifier */
542 #define CAN_RIxR_EXID_MASK (0x1FFFFFFF)
543 #define CAN_RIxR_EXID_SHIFT 3
544 
545 /* IDE: Identifier extension */
546 #define CAN_RIxR_IDE (1 << 2)
547 
548 /* RTR: Remote transmission request */
549 #define CAN_RIxR_RTR (1 << 1)
550 
551 /* 0 Reserved */
552 
553 /* --- CAN_RDTxR values ----------------------------------------------------- */
554 
555 /* TIME[15:0]: Message time stamp */
556 #define CAN_RDTxR_TIME_MASK (0xFFFF << 16)
557 #define CAN_RDTxR_TIME_SHIFT 16
558 
559 /* FMI[7:0]: Filter match index */
560 #define CAN_RDTxR_FMI_MASK (0xFF << 8)
561 #define CAN_RDTxR_FMI_SHIFT 8
562 
563 /* 7:4 Reserved, forced by hardware to 0 */
564 
565 /* DLC[3:0]: Data length code */
566 #define CAN_RDTxR_DLC_MASK (0xF << 0)
567 #define CAN_RDTxR_DLC_SHIFT 0
568 
569 /* --- CAN_RDLxR values ----------------------------------------------------- */
570 
571 /* DATA3[7:0]: Data byte 3 */
572 /* DATA2[7:0]: Data byte 2 */
573 /* DATA1[7:0]: Data byte 1 */
574 /* DATA0[7:0]: Data byte 0 */
575 
576 /* --- CAN_RDHxR values ----------------------------------------------------- */
577 
578 /* DATA7[7:0]: Data byte 7 */
579 /* DATA6[7:0]: Data byte 6 */
580 /* DATA5[7:0]: Data byte 5 */
581 /* DATA4[7:0]: Data byte 4 */
582 
583 /* --- CAN_FMR values ------------------------------------------------------- */
584 
585 /* 31:14 Reserved, forced to reset value */
586 
587 /*
588  * CAN2SB[5:0]: CAN2 start bank
589  * (only on connectivity line devices otherwise reserved)
590  */
591 #define CAN_FMR_CAN2SB_SHIFT 8
592 #define CAN_FMR_CAN2SB_MASK (0x3F << CAN_FMR_CAN2SB_SHIFT)
593 
594 /* 7:1 Reserved, forced to reset value */
595 
596 /* FINIT: Filter init mode */
597 #define CAN_FMR_FINIT (1 << 0)
598 
599 /* --- CAN_FM1R values ------------------------------------------------------ */
600 
601 /* 31:28 Reserved, forced by hardware to 0 */
602 
603 /*
604  * FBMx: Filter mode
605  * x is 0..27 should be calculated by a helper function making so many macros
606  * seems like an overkill?
607  */
608 
609 /* --- CAN_FS1R values ------------------------------------------------------ */
610 
611 /* 31:28 Reserved, forced by hardware to 0 */
612 
613 /*
614  * FSCx: Filter scale configuration
615  * x is 0..27 should be calculated by a helper function making so many macros
616  * seems like an overkill?
617  */
618 
619 /* --- CAN_FFA1R values ----------------------------------------------------- */
620 
621 /* 31:28 Reserved, forced by hardware to 0 */
622 
623 /*
624  * FFAx: Filter scale configuration
625  * x is 0..27 should be calculated by a helper function making so many macros
626  * seems like an overkill?
627  */
628 
629 /* --- CAN_FA1R values ------------------------------------------------------ */
630 
631 /* 31:28 Reserved, forced by hardware to 0 */
632 
633 /*
634  * FACTx: Filter active
635  * x is 0..27 should be calculated by a helper function making so many macros
636  * seems like an overkill?
637  */
638 
639 /* --- CAN_FiRx values ------------------------------------------------------ */
640 
641 /* FB[31:0]: Filter bits */
642 
643 /* --- CAN functions -------------------------------------------------------- */
644 
646 
647 void can_reset(uint32_t canport);
648 int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
649  bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
650  uint32_t brp, bool loopback, bool silent);
651 
652 void can_filter_init(uint32_t nr, bool scale_32bit,
653  bool id_list_mode, uint32_t fr1, uint32_t fr2,
654  uint32_t fifo, bool enable);
655 void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1,
656  uint16_t mask1, uint16_t id2,
657  uint16_t mask2, uint32_t fifo, bool enable);
658 void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id,
659  uint32_t mask, uint32_t fifo, bool enable);
660 void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1,
661  uint16_t id2, uint16_t id3, uint16_t id4,
662  uint32_t fifo, bool enable);
663 void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1,
664  uint32_t id2, uint32_t fifo, bool enable);
665 
666 void can_enable_irq(uint32_t canport, uint32_t irq);
667 void can_disable_irq(uint32_t canport, uint32_t irq);
668 
669 int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
670  uint8_t length, uint8_t *data);
671 void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
672  bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length,
673  uint8_t *data, uint16_t *timestamp);
674 
675 void can_fifo_release(uint32_t canport, uint8_t fifo);
676 bool can_available_mailbox(uint32_t canport);
677 END_DECLS
678 
679 /**@}*/
680 #endif
bool can_available_mailbox(uint32_t canport)
Definition: can.c:547
void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1, uint16_t mask1, uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID Mask Filter.
Definition: can.c:259
void can_disable_irq(uint32_t canport, uint32_t irq)
CAN Disable IRQ.
Definition: can.c:337
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp, bool loopback, bool silent)
CAN Init.
Definition: can.c:92
void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id, uint32_t mask, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID Mask Filter.
Definition: can.c:277
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
CAN Transmit Message.
Definition: can.c:354
#define END_DECLS
Definition: common.h:34
void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1, uint32_t id2, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID List Filter.
Definition: can.c:313
void can_fifo_release(uint32_t canport, uint8_t fifo)
CAN Release FIFO.
Definition: can.c:446
void can_reset(uint32_t canport)
CAN Reset.
Definition: can.c:63
void can_enable_irq(uint32_t canport, uint32_t irq)
CAN Enable IRQ.
Definition: can.c:326
#define BEGIN_DECLS
Definition: common.h:33
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length, uint8_t *data, uint16_t *timestamp)
CAN Receive Message.
Definition: can.c:470
void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID List Filter.
Definition: can.c:294
void can_filter_init(uint32_t nr, bool scale_32bit, bool id_list_mode, uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
CAN Filter Init.
Definition: can.c:199