libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
rcc_common_all.c
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1 /*
2  * This file is part of the libopencm3 project.
3  *
4  * Copyright (C) 2013 Frantisek Burian <bufran@seznam.cz>
5  * .. file is merged from many other copyrighted files of stm32 family
6  *
7  * This library is free software: you can redistribute it and/or modify
8  * it under the terms of the GNU Lesser General Public License as published by
9  * the Free Software Foundation, either version 3 of the License, or
10  * (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public License
18  * along with this library. If not, see <http://www.gnu.org/licenses/>.
19  */
20 /**@{*/
21 
22 #include <libopencm3/stm32/rcc.h>
23 
24 /*---------------------------------------------------------------------------*/
25 /** @brief RCC Enable Peripheral Clocks.
26  *
27  * Enable the clock on particular peripherals. There are three registers
28  * involved, each one controlling the enabling of clocks associated with the
29  * AHB, APB1 and APB2 respectively. Several peripherals could be enabled
30  * simultaneously <em>only if they are controlled by the same register</em>.
31  *
32  * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
33  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
34  *
35  * @param[in] en Unsigned int32. Logical OR of all enables to be set
36  * @li If register is RCC_AHBER, from @ref rcc_ahbenr_en
37  * @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
38  * @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
39  */
40 
41 void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
42 {
43  *reg |= en;
44 }
45 
46 /*---------------------------------------------------------------------------*/
47 /** @brief RCC Disable Peripheral Clocks.
48  *
49  * Enable the clock on particular peripherals. There are three registers
50  * involved, each one controlling the enabling of clocks associated with
51  * the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
52  * simultaneously <em>only if they are controlled by the same register</em>.
53  *
54  * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
55  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
56  * @param[in] en Unsigned int32. Logical OR of all enables to be used for
57  * disabling.
58  * @li If register is RCC_AHBER, from @ref rcc_ahbenr_en
59  * @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
60  * @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
61  */
62 void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
63 {
64  *reg &= ~en;
65 }
66 
67 /*---------------------------------------------------------------------------*/
68 /** @brief RCC Reset Peripherals.
69  *
70  * Reset particular peripherals. There are three registers involved, each one
71  * controlling reset of peripherals associated with the AHB, APB1 and APB2
72  * respectively. Several peripherals could be reset simultaneously <em>only if
73  * they are controlled by the same register</em>.
74  *
75  * @param[in] *reg Unsigned int32. Pointer to a Reset Register
76  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
77  * @param[in] reset Unsigned int32. Logical OR of all resets.
78  * @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
79  * @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
80  * @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
81  */
82 void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
83 {
84  *reg |= reset;
85 }
86 
87 /*---------------------------------------------------------------------------*/
88 /** @brief RCC Remove Reset on Peripherals.
89  *
90  * Remove the reset on particular peripherals. There are three registers
91  * involved, each one controlling reset of peripherals associated with the AHB,
92  * APB1 and APB2 respectively. Several peripherals could have the reset removed
93  * simultaneously <em>only if they are controlled by the same register</em>.
94  *
95  * @param[in] *reg Unsigned int32. Pointer to a Reset Register
96  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
97  * @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
98  * removed:
99  * @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
100  * @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
101  * @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
102  */
103 void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
104 {
105  *reg &= ~clear_reset;
106 }
107 
108 #define _RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))
109 #define _RCC_BIT(i) (1 << ((i) & 0x1f))
110 
111 /*---------------------------------------------------------------------------*/
112 /** @brief Enable Peripheral Clock in running mode.
113  *
114  * Enable the clock on particular peripheral.
115  *
116  * @param[in] clken rcc_periph_clken Peripheral RCC
117  *
118  * For available constants, see #rcc_periph_clken (RCC_UART1 for example)
119  */
120 
122 {
123  _RCC_REG(clken) |= _RCC_BIT(clken);
124 }
125 
126 /*---------------------------------------------------------------------------*/
127 /** @brief Disable Peripheral Clock in running mode.
128  * Disable the clock on particular peripheral.
129  *
130  * @param[in] clken rcc_periph_clken Peripheral RCC
131  *
132  * For available constants, see #rcc_periph_clken (RCC_UART1 for example)
133  */
134 
136 {
137  _RCC_REG(clken) &= ~_RCC_BIT(clken);
138 }
139 
140 /*---------------------------------------------------------------------------*/
141 /** @brief Reset Peripheral, pulsed
142  *
143  * Reset particular peripheral, and restore to working state.
144  *
145  * @param[in] rst rcc_periph_rst Peripheral reset
146  *
147  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
148  */
149 
151 {
152  _RCC_REG(rst) |= _RCC_BIT(rst);
153  _RCC_REG(rst) &= ~_RCC_BIT(rst);
154 }
155 
156 /*---------------------------------------------------------------------------*/
157 /** @brief Reset Peripheral, hold
158  *
159  * Reset particular peripheral, and hold in reset state.
160  *
161  * @param[in] rst rcc_periph_rst Peripheral reset
162  *
163  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
164  */
165 
167 {
168  _RCC_REG(rst) |= _RCC_BIT(rst);
169 }
170 
171 /*---------------------------------------------------------------------------*/
172 /** @brief Reset Peripheral, release
173  *
174  * Restore peripheral from reset state to working state.
175  *
176  * @param[in] rst rcc_periph_rst Peripheral reset
177  *
178  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
179  */
180 
182 {
183  _RCC_REG(rst) &= ~_RCC_BIT(rst);
184 }
185 
186 /** @brief Select the source of Microcontroller Clock Output
187  *
188  * Exact sources available depend on your target. On devices with multiple
189  * MCO pins, this function controls MCO1
190  *
191  * @param[in] mcosrc the unshifted source bits
192  */
193 
194 void rcc_set_mco(uint32_t mcosrc)
195 {
197  (mcosrc << RCC_CFGR_MCO_SHIFT);
198 }
199 
200 /**
201  * RCC Enable Bypass.
202  * Enable an external clock to bypass the internal clock (high speed and low
203  * speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
204  * and the internal clock must be disabled (see @ref rcc_osc_off) for this to
205  * have effect.
206  * @note The LSE clock is in the backup domain and cannot be bypassed until the
207  * backup domain write protection has been removed (see @ref
208  * pwr_disable_backup_domain_write_protect).
209  * @param[in] osc Oscillator ID. Only HSE and LSE have effect.
210  */
212 {
213  switch (osc) {
214  case RCC_HSE:
216  break;
217  case RCC_LSE:
218 #ifdef RCC_CSR_LSEBYP
219  RCC_CSR |= RCC_CSR_LSEBYP;
220 #else
222 #endif
223  break;
224  default:
225  /* Do nothing, only HSE/LSE allowed here. */
226  break;
227  }
228 }
229 
230 /**
231  * RCC Disable Bypass.
232  * Re-enable the internal clock (high speed and low speed clocks only). The
233  * internal clock must be disabled (see @ref rcc_osc_off) for this to have
234  * effect.
235  * @note The LSE clock is in the backup domain and cannot have bypass removed
236  * until the backup domain write protection has been removed (see @ref
237  * pwr_disable_backup_domain_write_protect) or the backup domain has been reset
238  * (see @ref rcc_backupdomain_reset).
239  * @param[in] osc Oscillator ID. Only HSE and LSE have effect.
240  */
242 {
243  switch (osc) {
244  case RCC_HSE:
245  RCC_CR &= ~RCC_CR_HSEBYP;
246  break;
247  case RCC_LSE:
248 #ifdef RCC_CSR_LSEBYP
249  RCC_CSR &= ~RCC_CSR_LSEBYP;
250 #else
252 #endif
253  break;
254  default:
255  /* Do nothing, only HSE/LSE allowed here. */
256  break;
257  }
258 }
259 
260 /**@}*/
261 
262 #undef _RCC_REG
263 #undef _RCC_BIT
rcc_periph_rst
Definition: f0/rcc.h:471
void rcc_periph_clock_enable(enum rcc_periph_clken clken)
Enable Peripheral Clock in running mode.
void rcc_osc_bypass_enable(enum rcc_osc osc)
RCC Enable Bypass.
void rcc_set_mco(uint32_t mcosrc)
Select the source of Microcontroller Clock Output.
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
RCC Remove Reset on Peripherals.
void rcc_osc_bypass_disable(enum rcc_osc osc)
RCC Disable Bypass.
#define RCC_CR
Definition: f0/rcc.h:48
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
RCC Reset Peripherals.
#define _RCC_BIT(i)
void rcc_periph_reset_pulse(enum rcc_periph_rst rst)
Reset Peripheral, pulsed.
#define RCC_CFGR_MCO_SHIFT
Definition: f0/rcc.h:97
void rcc_periph_reset_release(enum rcc_periph_rst rst)
Reset Peripheral, release.
#define RCC_CFGR
Definition: f0/rcc.h:49
#define RCC_BDCR
Definition: f0/rcc.h:56
#define RCC_CFGR_MCO_MASK
Definition: f0/rcc.h:98
#define RCC_CSR
Definition: f0/rcc.h:57
void rcc_periph_clock_disable(enum rcc_periph_clken clken)
Disable Peripheral Clock in running mode.
#define RCC_CR_HSEBYP
Definition: f0/rcc.h:72
void rcc_periph_reset_hold(enum rcc_periph_rst rst)
Reset Peripheral, hold.
#define RCC_BDCR_LSEBYP
Definition: f0/rcc.h:304
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
RCC Enable Peripheral Clocks.
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
RCC Disable Peripheral Clocks.
rcc_periph_clken
Definition: f0/rcc.h:413
rcc_osc
Definition: f0/rcc.h:407
#define _RCC_REG(i)