libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
rcc_common_all.c
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1 /** @addtogroup rcc_file RCC peripheral API
2  * @ingroup peripheral_apis
3  */
4 /*
5  * This file is part of the libopencm3 project.
6  *
7  * Copyright (C) 2013 Frantisek Burian <bufran@seznam.cz>
8  * .. file is merged from many other copyrighted files of stm32 family
9  *
10  * This library is free software: you can redistribute it and/or modify
11  * it under the terms of the GNU Lesser General Public License as published by
12  * the Free Software Foundation, either version 3 of the License, or
13  * (at your option) any later version.
14  *
15  * This library is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU Lesser General Public License for more details.
19  *
20  * You should have received a copy of the GNU Lesser General Public License
21  * along with this library. If not, see <http://www.gnu.org/licenses/>.
22  */
23 /**@{*/
24 
25 #include <libopencm3/stm32/rcc.h>
26 
27 /*---------------------------------------------------------------------------*/
28 /** @brief RCC Enable Peripheral Clocks.
29  *
30  * Enable the clock on particular peripherals. There are three registers
31  * involved, each one controlling the enabling of clocks associated with the
32  * AHB, APB1 and APB2 respectively. Several peripherals could be enabled
33  * simultaneously <em>only if they are controlled by the same register</em>.
34  *
35  * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
36  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
37  *
38  * @param[in] en Unsigned int32. Logical OR of all enables to be set
39  * @li If register is RCC_AHBER, from @ref rcc_ahbenr_en
40  * @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
41  * @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
42  */
43 
44 void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
45 {
46  *reg |= en;
47 }
48 
49 /*---------------------------------------------------------------------------*/
50 /** @brief RCC Disable Peripheral Clocks.
51  *
52  * Enable the clock on particular peripherals. There are three registers
53  * involved, each one controlling the enabling of clocks associated with
54  * the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
55  * simultaneously <em>only if they are controlled by the same register</em>.
56  *
57  * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
58  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
59  * @param[in] en Unsigned int32. Logical OR of all enables to be used for
60  * disabling.
61  * @li If register is RCC_AHBER, from @ref rcc_ahbenr_en
62  * @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
63  * @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
64  */
65 void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
66 {
67  *reg &= ~en;
68 }
69 
70 /*---------------------------------------------------------------------------*/
71 /** @brief RCC Reset Peripherals.
72  *
73  * Reset particular peripherals. There are three registers involved, each one
74  * controlling reset of peripherals associated with the AHB, APB1 and APB2
75  * respectively. Several peripherals could be reset simultaneously <em>only if
76  * they are controlled by the same register</em>.
77  *
78  * @param[in] *reg Unsigned int32. Pointer to a Reset Register
79  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
80  * @param[in] reset Unsigned int32. Logical OR of all resets.
81  * @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
82  * @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
83  * @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
84  */
85 void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
86 {
87  *reg |= reset;
88 }
89 
90 /*---------------------------------------------------------------------------*/
91 /** @brief RCC Remove Reset on Peripherals.
92  *
93  * Remove the reset on particular peripherals. There are three registers
94  * involved, each one controlling reset of peripherals associated with the AHB,
95  * APB1 and APB2 respectively. Several peripherals could have the reset removed
96  * simultaneously <em>only if they are controlled by the same register</em>.
97  *
98  * @param[in] *reg Unsigned int32. Pointer to a Reset Register
99  * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
100  * @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
101  * removed:
102  * @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
103  * @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
104  * @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
105  */
106 void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
107 {
108  *reg &= ~clear_reset;
109 }
110 
111 #define _RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))
112 #define _RCC_BIT(i) (1 << ((i) & 0x1f))
113 
114 /*---------------------------------------------------------------------------*/
115 /** @brief Enable Peripheral Clock in running mode.
116  *
117  * Enable the clock on particular peripheral.
118  *
119  * @param[in] clken rcc_periph_clken Peripheral RCC
120  *
121  * For available constants, see #rcc_periph_clken (RCC_UART1 for example)
122  */
123 
125 {
126  _RCC_REG(clken) |= _RCC_BIT(clken);
127 }
128 
129 /*---------------------------------------------------------------------------*/
130 /** @brief Disable Peripheral Clock in running mode.
131  * Disable the clock on particular peripheral.
132  *
133  * @param[in] clken rcc_periph_clken Peripheral RCC
134  *
135  * For available constants, see #rcc_periph_clken (RCC_UART1 for example)
136  */
137 
139 {
140  _RCC_REG(clken) &= ~_RCC_BIT(clken);
141 }
142 
143 /*---------------------------------------------------------------------------*/
144 /** @brief Reset Peripheral, pulsed
145  *
146  * Reset particular peripheral, and restore to working state.
147  *
148  * @param[in] rst rcc_periph_rst Peripheral reset
149  *
150  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
151  */
152 
154 {
155  _RCC_REG(rst) |= _RCC_BIT(rst);
156  _RCC_REG(rst) &= ~_RCC_BIT(rst);
157 }
158 
159 /*---------------------------------------------------------------------------*/
160 /** @brief Reset Peripheral, hold
161  *
162  * Reset particular peripheral, and hold in reset state.
163  *
164  * @param[in] rst rcc_periph_rst Peripheral reset
165  *
166  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
167  */
168 
170 {
171  _RCC_REG(rst) |= _RCC_BIT(rst);
172 }
173 
174 /*---------------------------------------------------------------------------*/
175 /** @brief Reset Peripheral, release
176  *
177  * Restore peripheral from reset state to working state.
178  *
179  * @param[in] rst rcc_periph_rst Peripheral reset
180  *
181  * For available constants, see #rcc_periph_rst (RST_UART1 for example)
182  */
183 
185 {
186  _RCC_REG(rst) &= ~_RCC_BIT(rst);
187 }
188 
189 /** @brief Select the source of Microcontroller Clock Output
190  *
191  * Exact sources available depend on your target. On devices with multiple
192  * MCO pins, this function controls MCO1
193  *
194  * @param[in] mcosrc the unshifted source bits
195  */
196 
197 void rcc_set_mco(uint32_t mcosrc)
198 {
200  (mcosrc << RCC_CFGR_MCO_SHIFT);
201 }
202 
203 /**
204  * RCC Enable Bypass.
205  * Enable an external clock to bypass the internal clock (high speed and low
206  * speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
207  * and the internal clock must be disabled (see @ref rcc_osc_off) for this to
208  * have effect.
209  * @note The LSE clock is in the backup domain and cannot be bypassed until the
210  * backup domain write protection has been removed (see @ref
211  * pwr_disable_backup_domain_write_protect).
212  * @param[in] osc Oscillator ID. Only HSE and LSE have effect.
213  */
215 {
216  switch (osc) {
217  case RCC_HSE:
219  break;
220  case RCC_LSE:
221 #ifdef RCC_CSR_LSEBYP
222  RCC_CSR |= RCC_CSR_LSEBYP;
223 #else
225 #endif
226  break;
227  default:
228  /* Do nothing, only HSE/LSE allowed here. */
229  break;
230  }
231 }
232 
233 /**
234  * RCC Disable Bypass.
235  * Re-enable the internal clock (high speed and low speed clocks only). The
236  * internal clock must be disabled (see @ref rcc_osc_off) for this to have
237  * effect.
238  * @note The LSE clock is in the backup domain and cannot have bypass removed
239  * until the backup domain write protection has been removed (see @ref
240  * pwr_disable_backup_domain_write_protect) or the backup domain has been reset
241  * (see @ref rcc_backupdomain_reset).
242  * @param[in] osc Oscillator ID. Only HSE and LSE have effect.
243  */
245 {
246  switch (osc) {
247  case RCC_HSE:
248  RCC_CR &= ~RCC_CR_HSEBYP;
249  break;
250  case RCC_LSE:
251 #ifdef RCC_CSR_LSEBYP
252  RCC_CSR &= ~RCC_CSR_LSEBYP;
253 #else
255 #endif
256  break;
257  default:
258  /* Do nothing, only HSE/LSE allowed here. */
259  break;
260  }
261 }
262 
263 /**@}*/
264 
265 #undef _RCC_REG
266 #undef _RCC_BIT
void rcc_osc_bypass_disable(enum rcc_osc osc)
RCC Disable Bypass.
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
RCC Remove Reset on Peripherals.
rcc_periph_rst
Definition: f0/rcc.h:496
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
RCC Enable Peripheral Clocks.
void rcc_periph_clock_disable(enum rcc_periph_clken clken)
Disable Peripheral Clock in running mode.
#define RCC_CR
Definition: f0/rcc.h:48
#define _RCC_REG(i)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
RCC Disable Peripheral Clocks.
#define RCC_CFGR_MCO_SHIFT
Definition: f0/rcc.h:97
#define RCC_CFGR
Definition: f0/rcc.h:49
#define RCC_BDCR
Definition: f0/rcc.h:56
#define RCC_CFGR_MCO_MASK
Definition: f0/rcc.h:98
#define RCC_CSR
Definition: f0/rcc.h:57
#define _RCC_BIT(i)
#define RCC_CR_HSEBYP
Definition: f0/rcc.h:72
void rcc_osc_bypass_enable(enum rcc_osc osc)
RCC Enable Bypass.
#define RCC_BDCR_LSEBYP
Definition: f0/rcc.h:328
void rcc_periph_reset_pulse(enum rcc_periph_rst rst)
Reset Peripheral, pulsed.
rcc_periph_clken
Definition: f0/rcc.h:438
void rcc_periph_reset_release(enum rcc_periph_rst rst)
Reset Peripheral, release.
void rcc_set_mco(uint32_t mcosrc)
Select the source of Microcontroller Clock Output.
rcc_osc
Definition: f0/rcc.h:432
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
RCC Reset Peripherals.
void rcc_periph_reset_hold(enum rcc_periph_rst rst)
Reset Peripheral, hold.
void rcc_periph_clock_enable(enum rcc_periph_clken clken)
Enable Peripheral Clock in running mode.