#include <libopencm3/cm3/memorymap.h>

Include dependency graph for stm32/f0/memorymap.h:

Macros
#define	FLASH_BASE (0x08000000U)

#define	PERIPH_BASE (0x40000000U)

#define	INFO_BASE (0x1ffff000U)

#define	PERIPH_BASE_APB (PERIPH_BASE + 0x00000000)

#define	PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000)

#define	PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000)

#define	TIM2_BASE (PERIPH_BASE_APB + 0x0000)

#define	TIM3_BASE (PERIPH_BASE_APB + 0x0400)

#define	TIM6_BASE (PERIPH_BASE_APB + 0x1000)

#define	TIM7_BASE (PERIPH_BASE_APB + 0x1400)

#define	TIM14_BASE (PERIPH_BASE_APB + 0x2000)

#define	RTC_BASE (PERIPH_BASE_APB + 0x2800)

#define	WWDG_BASE (PERIPH_BASE_APB + 0x2c00)

#define	IWDG_BASE (PERIPH_BASE_APB + 0x3000)

#define	SPI2_BASE (PERIPH_BASE_APB + 0x3800)

#define	USART2_BASE (PERIPH_BASE_APB + 0x4400)

#define	USART3_BASE (PERIPH_BASE_APB + 0x4800)

#define	USART4_BASE (PERIPH_BASE_APB + 0x4C00)

#define	USART5_BASE (PERIPH_BASE_APB + 0x5000)

#define	I2C1_BASE (PERIPH_BASE_APB + 0x5400)

#define	I2C2_BASE (PERIPH_BASE_APB + 0x5800)

#define	USB_DEV_FS_BASE (PERIPH_BASE_APB + 0x5C00)

#define	USB_PMA_BASE (PERIPH_BASE_APB + 0x6000)

#define	BX_CAN1_BASE (PERIPH_BASE_APB + 0x6400)

#define	CRS_BASE (PERIPH_BASE_APB + 0x6C00)

#define	POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)

#define	DAC_BASE (PERIPH_BASE_APB + 0x7400)

#define	CEC_BASE (PERIPH_BASE_APB + 0x7800)

#define	SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000)

#define	EXTI_BASE (PERIPH_BASE_APB + 0x10400)

#define	USART6_BASE (PERIPH_BASE_APB + 0x11400)

#define	USART7_BASE (PERIPH_BASE_APB + 0x11800)

#define	USART8_BASE (PERIPH_BASE_APB + 0x11C00)

#define	ADC_BASE (PERIPH_BASE_APB + 0x12400)

#define	TIM1_BASE (PERIPH_BASE_APB + 0x12C00)

#define	SPI1_BASE (PERIPH_BASE_APB + 0x13000)

#define	USART1_BASE (PERIPH_BASE_APB + 0x13800)

#define	TIM15_BASE (PERIPH_BASE_APB + 0x14000)

#define	TIM16_BASE (PERIPH_BASE_APB + 0x14400)

#define	TIM17_BASE (PERIPH_BASE_APB + 0x14800)

#define	DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)

#define	DMA_BASE (PERIPH_BASE_AHB1 + 0x0000)

#define	DMA1_BASE DMA_BASE

#define	DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)

#define	RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)

#define	FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)

#define	CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

#define	TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)

#define	GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)

#define	GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)

#define	GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)

#define	GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00)

#define	GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)

#define	GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)

#define	DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU)

#define	DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU)

#define	DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

#define	DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

#define	DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)

#define	ST_VREFINT_CAL MMIO16(0x1FFFF7BA)

#define	ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8)

#define	ST_TSENSE_CAL2_110C MMIO16(0x1FFFF7C2)

Macro Definition Documentation

◆ ADC_BASE

#define ADC_BASE (PERIPH_BASE_APB + 0x12400)

Definition at line 77 of file stm32/f0/memorymap.h.

◆ BX_CAN1_BASE

#define BX_CAN1_BASE (PERIPH_BASE_APB + 0x6400)

Definition at line 63 of file stm32/f0/memorymap.h.

◆ CEC_BASE

#define CEC_BASE (PERIPH_BASE_APB + 0x7800)

Definition at line 68 of file stm32/f0/memorymap.h.

◆ CRC_BASE

#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

Definition at line 98 of file stm32/f0/memorymap.h.

◆ CRS_BASE

#define CRS_BASE (PERIPH_BASE_APB + 0x6C00)

Definition at line 65 of file stm32/f0/memorymap.h.

◆ DAC_BASE

#define DAC_BASE (PERIPH_BASE_APB + 0x7400)

Definition at line 67 of file stm32/f0/memorymap.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)

Definition at line 86 of file stm32/f0/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE

#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU)

Definition at line 111 of file stm32/f0/memorymap.h.

◆ DESIG_UNIQUE_ID0

#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

Definition at line 113 of file stm32/f0/memorymap.h.

◆ DESIG_UNIQUE_ID1

#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

Definition at line 114 of file stm32/f0/memorymap.h.

◆ DESIG_UNIQUE_ID2

#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)

Definition at line 115 of file stm32/f0/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE

#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU)

Definition at line 112 of file stm32/f0/memorymap.h.

◆ DMA1_BASE

#define DMA1_BASE DMA_BASE

Definition at line 91 of file stm32/f0/memorymap.h.

◆ DMA2_BASE

#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)

Definition at line 92 of file stm32/f0/memorymap.h.

◆ DMA_BASE

#define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000)

Definition at line 89 of file stm32/f0/memorymap.h.

◆ EXTI_BASE

#define EXTI_BASE (PERIPH_BASE_APB + 0x10400)

Definition at line 71 of file stm32/f0/memorymap.h.

◆ FLASH_BASE

#define FLASH_BASE (0x08000000U)

Definition at line 30 of file stm32/f0/memorymap.h.

◆ FLASH_MEM_INTERFACE_BASE

#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)

Definition at line 96 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_A_BASE

#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)

Definition at line 103 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_B_BASE

#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)

Definition at line 104 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_C_BASE

#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)

Definition at line 105 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_D_BASE

#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00)

Definition at line 106 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_E_BASE

#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)

Definition at line 107 of file stm32/f0/memorymap.h.

◆ GPIO_PORT_F_BASE

#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)

Definition at line 108 of file stm32/f0/memorymap.h.

◆ I2C1_BASE

#define I2C1_BASE (PERIPH_BASE_APB + 0x5400)

Definition at line 59 of file stm32/f0/memorymap.h.

◆ I2C2_BASE

#define I2C2_BASE (PERIPH_BASE_APB + 0x5800)

Definition at line 60 of file stm32/f0/memorymap.h.

◆ INFO_BASE

#define INFO_BASE (0x1ffff000U)

Definition at line 32 of file stm32/f0/memorymap.h.

◆ IWDG_BASE

#define IWDG_BASE (PERIPH_BASE_APB + 0x3000)

Definition at line 50 of file stm32/f0/memorymap.h.

◆ PERIPH_BASE

#define PERIPH_BASE (0x40000000U)

Definition at line 31 of file stm32/f0/memorymap.h.

◆ PERIPH_BASE_AHB1

#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000)

Definition at line 34 of file stm32/f0/memorymap.h.

◆ PERIPH_BASE_AHB2

#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000)

Definition at line 35 of file stm32/f0/memorymap.h.

◆ PERIPH_BASE_APB

#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000)

Definition at line 33 of file stm32/f0/memorymap.h.

◆ POWER_CONTROL_BASE

#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)

Definition at line 66 of file stm32/f0/memorymap.h.

◆ RCC_BASE

#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)

Definition at line 94 of file stm32/f0/memorymap.h.

◆ RTC_BASE

#define RTC_BASE (PERIPH_BASE_APB + 0x2800)

Definition at line 48 of file stm32/f0/memorymap.h.

◆ SPI1_BASE

#define SPI1_BASE (PERIPH_BASE_APB + 0x13000)

Definition at line 79 of file stm32/f0/memorymap.h.

◆ SPI2_BASE

#define SPI2_BASE (PERIPH_BASE_APB + 0x3800)

Definition at line 52 of file stm32/f0/memorymap.h.

◆ ST_TSENSE_CAL1_30C

#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8)

Definition at line 119 of file stm32/f0/memorymap.h.

◆ ST_TSENSE_CAL2_110C

#define ST_TSENSE_CAL2_110C MMIO16(0x1FFFF7C2)

Definition at line 120 of file stm32/f0/memorymap.h.

◆ ST_VREFINT_CAL

#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA)

Definition at line 118 of file stm32/f0/memorymap.h.

◆ SYSCFG_COMP_BASE

#define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000)

Definition at line 70 of file stm32/f0/memorymap.h.

◆ TIM14_BASE

#define TIM14_BASE (PERIPH_BASE_APB + 0x2000)

Definition at line 46 of file stm32/f0/memorymap.h.

◆ TIM15_BASE

#define TIM15_BASE (PERIPH_BASE_APB + 0x14000)

Definition at line 82 of file stm32/f0/memorymap.h.

◆ TIM16_BASE

#define TIM16_BASE (PERIPH_BASE_APB + 0x14400)

Definition at line 83 of file stm32/f0/memorymap.h.

◆ TIM17_BASE

#define TIM17_BASE (PERIPH_BASE_APB + 0x14800)

Definition at line 84 of file stm32/f0/memorymap.h.

◆ TIM1_BASE

#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00)

Definition at line 78 of file stm32/f0/memorymap.h.

◆ TIM2_BASE

#define TIM2_BASE (PERIPH_BASE_APB + 0x0000)

Definition at line 40 of file stm32/f0/memorymap.h.

◆ TIM3_BASE

#define TIM3_BASE (PERIPH_BASE_APB + 0x0400)

Definition at line 41 of file stm32/f0/memorymap.h.

◆ TIM6_BASE

#define TIM6_BASE (PERIPH_BASE_APB + 0x1000)

Definition at line 43 of file stm32/f0/memorymap.h.

◆ TIM7_BASE

#define TIM7_BASE (PERIPH_BASE_APB + 0x1400)

Definition at line 44 of file stm32/f0/memorymap.h.

◆ TSC_BASE

#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)

Definition at line 100 of file stm32/f0/memorymap.h.

◆ USART1_BASE

#define USART1_BASE (PERIPH_BASE_APB + 0x13800)

Definition at line 81 of file stm32/f0/memorymap.h.

◆ USART2_BASE

#define USART2_BASE (PERIPH_BASE_APB + 0x4400)

Definition at line 54 of file stm32/f0/memorymap.h.

◆ USART3_BASE

#define USART3_BASE (PERIPH_BASE_APB + 0x4800)

Definition at line 55 of file stm32/f0/memorymap.h.

◆ USART4_BASE

#define USART4_BASE (PERIPH_BASE_APB + 0x4C00)

Definition at line 56 of file stm32/f0/memorymap.h.

◆ USART5_BASE

#define USART5_BASE (PERIPH_BASE_APB + 0x5000)

Definition at line 57 of file stm32/f0/memorymap.h.

◆ USART6_BASE

#define USART6_BASE (PERIPH_BASE_APB + 0x11400)

Definition at line 73 of file stm32/f0/memorymap.h.

◆ USART7_BASE

#define USART7_BASE (PERIPH_BASE_APB + 0x11800)

Definition at line 74 of file stm32/f0/memorymap.h.

◆ USART8_BASE

#define USART8_BASE (PERIPH_BASE_APB + 0x11C00)

Definition at line 75 of file stm32/f0/memorymap.h.

◆ USB_DEV_FS_BASE

#define USB_DEV_FS_BASE (PERIPH_BASE_APB + 0x5C00)

Definition at line 61 of file stm32/f0/memorymap.h.

◆ USB_PMA_BASE

#define USB_PMA_BASE (PERIPH_BASE_APB + 0x6000)

Definition at line 62 of file stm32/f0/memorymap.h.

◆ WWDG_BASE

#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00)

Definition at line 49 of file stm32/f0/memorymap.h.

Macros