RCC_APB1RSTR reset values
Collaboration diagram for RCC_APB1RSTR reset values:
Macros | |
| #define | RCC_APB1RSTR_CECRST (1 << 30) |
| #define | RCC_APB1RSTR_DACRST (1 << 29) |
| #define | RCC_APB1RSTR_PWRRST (1 << 28) |
| #define | RCC_APB1RSTR_CRSRST (1 << 27) |
| #define | RCC_APB1RSTR_CANRST (1 << 25) |
| #define | RCC_APB1RSTR_USBRST (1 << 23) |
| #define | RCC_APB1RSTR_I2C2RST (1 << 22) |
| #define | RCC_APB1RSTR_I2C1RST (1 << 21) |
| #define | RCC_APB1RSTR_USART5RST (1 << 20) |
| #define | RCC_APB1RSTR_USART4RST (1 << 19) |
| #define | RCC_APB1RSTR_USART3RST (1 << 18) |
| #define | RCC_APB1RSTR_USART2RST (1 << 17) |
| #define | RCC_APB1RSTR_SPI2RST (1 << 14) |
| #define | RCC_APB1RSTR_WWDGRST (1 << 11) |
| #define | RCC_APB1RSTR_TIM14RST (1 << 8) |
| #define | RCC_APB1RSTR_TIM7RST (1 << 5) |
| #define | RCC_APB1RSTR_TIM6RST (1 << 4) |
| #define | RCC_APB1RSTR_TIM3RST (1 << 1) |
| #define | RCC_APB1RSTR_TIM2RST (1 << 0) |
