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| #define | SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00) |
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| #define | SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4) |
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| #define | SYSCFG_EXTICR1 SYSCFG_EXTICR(0) |
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| #define | SYSCFG_EXTICR2 SYSCFG_EXTICR(1) |
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| #define | SYSCFG_EXTICR3 SYSCFG_EXTICR(2) |
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| #define | SYSCFG_EXTICR4 SYSCFG_EXTICR(3) |
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| #define | SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SHIFT 0 |
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| #define | SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) |
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| #define | SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8) |
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| #define | SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9) |
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| #define | SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10) |
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| #define | SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11) |
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| #define | SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12) |
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| #define | SYSCFG_CFGR1_TIM16_DMA_RMP2 (1 << 13) |
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| #define | SYSCFG_CFGR1_TIM17_DMA_RMP2 (1 << 14) |
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| #define | SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) |
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| #define | SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) |
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| #define | SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) |
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| #define | SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) |
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| #define | SYSCFG_CFGR1_I2C1_FMP (1 << 20) |
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| #define | SYSCFG_CFGR1_I2C2_FMP (1 << 21) |
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| #define | SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22) |
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| #define | SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23) |
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| #define | SYSCFG_CFGR1_SPI2_DMA_RMP (1 << 24) |
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| #define | SYSCFG_CFGR1_USART2_DMA_RMP (1 << 25) |
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| #define | SYSCFG_CFGR1_USART3_DMA_RMP (1 << 26) |
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| #define | SYSCFG_CFGR1_I2C1_DMA_RMP (1 << 27) |
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| #define | SYSCFG_CFGR1_TIM1_DMA_RMP (1 << 28) |
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| #define | SYSCFG_CFGR1_TIM2_DMA_RMP (1 << 29) |
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| #define | SYSCFG_CFGR1_TIM3_DMA_RMP (1 << 30) |
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| #define | SYSCFG_EXTICR_FIELDSIZE 4 |
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| #define | SYSCFG_EXTICR_GPIOA 0 |
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| #define | SYSCFG_EXTICR_GPIOB 1 |
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| #define | SYSCFG_EXTICR_GPIOC 2 |
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| #define | SYSCFG_EXTICR_GPIOD 3 |
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| #define | SYSCFG_EXTICR_GPIOF 5 |
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| #define | SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0) |
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| #define | SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1) |
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| #define | SYSCFG_CFGR2_PVD_LOCK (1 << 2) |
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| #define | SYSCFG_CFGR2_SRAM_PEF (1 << 8) |
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