libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
f0/syscfg.h
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1/** @defgroup syscfg_defines SYSCFG Defines
2 *
3 * @brief <b>Defined Constants and Types for the STM32F0xx System Config</b>
4 *
5 * @ingroup STM32F0xx_defines
6 *
7 * @version 1.0.0
8 *
9 * @author @htmlonly &copy; @endhtmlonly 2013
10 * Frantisek Burian <BuFran@seznam.cz>
11 *
12 * @date 13 January 2014
13 *
14 * LGPL License Terms @ref lgpl_license
15 */
16/*
17 * This file is part of the libopencm3 project.
18 *
19 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
20 *
21 * This library is free software: you can redistribute it and/or modify
22 * it under the terms of the GNU Lesser General Public License as published by
23 * the Free Software Foundation, either version 3 of the License, or
24 * (at your option) any later version.
25 *
26 * This library is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU Lesser General Public License for more details.
30 *
31 * You should have received a copy of the GNU Lesser General Public License
32 * along with this library. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35#ifndef LIBOPENCM3_SYSCFG_H
36#define LIBOPENCM3_SYSCFG_H
37/**@{*/
38
39/*****************************************************************************/
40/* Module definitions */
41/*****************************************************************************/
42
43/*****************************************************************************/
44/* Register definitions */
45/*****************************************************************************/
46
47#define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00)
48#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4)
49#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0)
50#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1)
51#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2)
52#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3)
53#define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18)
54
55/*****************************************************************************/
56/* Register values */
57/*****************************************************************************/
58
59/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/
60
61#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0
62#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
63#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
64#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
65#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
66
67#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4)
68#define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8)
69#define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9)
70#define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10)
71#define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11)
72#define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12)
73#define SYSCFG_CFGR1_TIM16_DMA_RMP2 (1 << 13)
74#define SYSCFG_CFGR1_TIM17_DMA_RMP2 (1 << 14)
75
76#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16)
77#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17)
78#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18)
79#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19)
80#define SYSCFG_CFGR1_I2C1_FMP (1 << 20)
81#define SYSCFG_CFGR1_I2C2_FMP (1 << 21)
82#define SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22)
83#define SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23)
84#define SYSCFG_CFGR1_SPI2_DMA_RMP (1 << 24)
85#define SYSCFG_CFGR1_USART2_DMA_RMP (1 << 25)
86#define SYSCFG_CFGR1_USART3_DMA_RMP (1 << 26)
87#define SYSCFG_CFGR1_I2C1_DMA_RMP (1 << 27)
88#define SYSCFG_CFGR1_TIM1_DMA_RMP (1 << 28)
89#define SYSCFG_CFGR1_TIM2_DMA_RMP (1 << 29)
90#define SYSCFG_CFGR1_TIM3_DMA_RMP (1 << 30)
91
92/* SYSCFG_EXTICR Values -- --------------------------------------------------*/
93
94#define SYSCFG_EXTICR_FIELDSIZE 4
95#define SYSCFG_EXTICR_GPIOA 0
96#define SYSCFG_EXTICR_GPIOB 1
97#define SYSCFG_EXTICR_GPIOC 2
98#define SYSCFG_EXTICR_GPIOD 3
99#define SYSCFG_EXTICR_GPIOF 5
100
101/* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/
102
103#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0)
104#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1)
105#define SYSCFG_CFGR2_PVD_LOCK (1 << 2)
106#define SYSCFG_CFGR2_SRAM_PEF (1 << 8)
107
108/*****************************************************************************/
109/* API definitions */
110/*****************************************************************************/
111
112/*****************************************************************************/
113/* API Functions */
114/*****************************************************************************/
115
116BEGIN_DECLS
117
118END_DECLS
119/**@}*/
120
121#endif
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33