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| #define | BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) |
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| #define | BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) |
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| #define | BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) |
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| #define | BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) |
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| #define | BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) |
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| #define | BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) |
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| #define | BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) |
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| #define | BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) |
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| #define | BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) |
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| #define | BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) |
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| #define | BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) |
| | RTC clock calibration register (BKP_RTCCR) More...
|
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| #define | BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) |
| | Backup control register (BKP_CR) More...
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| #define | BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) |
| | Backup control/status register (BKP_CSR) More...
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| #define | BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) |
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| #define | BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) |
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| #define | BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) |
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| #define | BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) |
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| #define | BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) |
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| #define | BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) |
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| #define | BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) |
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| #define | BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) |
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| #define | BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) |
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| #define | BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) |
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| #define | BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) |
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| #define | BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) |
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| #define | BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) |
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| #define | BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) |
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| #define | BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) |
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| #define | BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) |
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| #define | BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) |
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| #define | BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) |
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| #define | BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) |
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| #define | BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) |
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| #define | BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) |
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| #define | BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) |
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| #define | BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) |
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| #define | BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) |
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| #define | BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) |
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| #define | BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) |
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| #define | BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) |
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| #define | BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) |
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| #define | BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) |
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| #define | BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) |
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| #define | BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) |
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| #define | BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) |
| |
| #define | BKP_RTCCR_ASOS (1 << 9) |
| | ASOS: Alarm or second output selection. More...
|
| |
| #define | BKP_RTCCR_ASOE (1 << 8) |
| | ASOE: Alarm or second output enable. More...
|
| |
| #define | BKP_RTCCR_CCO (1 << 7) |
| | CCO: Calibration clock output. More...
|
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| #define | BKP_RTCCR_CAL_LSB 0 |
| | CAL[6:0]: Calibration value. More...
|
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| #define | BKP_CR_TPAL (1 << 1) |
| | TPAL: TAMPER pin active level. More...
|
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| #define | BKP_CR_TPE (1 << 0) |
| | TPE: TAMPER pin enable. More...
|
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| #define | BKP_CSR_TIF (1 << 9) |
| | TIF: Tamper interrupt flag. More...
|
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| #define | BKP_CSR_TEF (1 << 8) |
| | TEF: Tamper event flag. More...
|
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| #define | BKP_CSR_TPIE (1 << 2) |
| | TPIE: TAMPER pin interrupt enable. More...
|
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| #define | BKP_CSR_CTI (1 << 1) |
| | CTI: Clear tamper interrupt. More...
|
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| #define | BKP_CSR_CTE (1 << 0) |
| | CTE: Clear tamper event. More...
|
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