#include <libopencm3/cm3/memorymap.h>

Include dependency graph for stm32/f1/memorymap.h:

Macros
#define	FLASH_BASE (0x08000000U)

#define	PERIPH_BASE (0x40000000U)

#define	INFO_BASE (0x1ffff000U)

#define	PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

#define	PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

#define	PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)

#define	TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

#define	TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

#define	TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

#define	TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

#define	TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

#define	TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

#define	TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)

#define	TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)

#define	TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)

#define	RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

#define	WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

#define	IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

#define	SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

#define	SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

#define	USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

#define	USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

#define	UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

#define	UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

#define	I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

#define	I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

#define	USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)

#define	USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)

#define	USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)

#define	BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

#define	BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

#define	BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)

#define	POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

#define	DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

#define	CEC_BASE (PERIPH_BASE_APB1 + 0x7800)

#define	AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)

#define	EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)

#define	GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)

#define	GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)

#define	GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)

#define	GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)

#define	GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)

#define	GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)

#define	GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)

#define	ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)

#define	ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)

#define	TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)

#define	SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

#define	TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)

#define	USART1_BASE (PERIPH_BASE_APB2 + 0x3800)

#define	ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)

#define	TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)

#define	TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)

#define	TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)

#define	TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00)

#define	TIM10_BASE (PERIPH_BASE_APB2 + 0x5000)

#define	TIM11_BASE (PERIPH_BASE_APB2 + 0x5400)

#define	SDIO_BASE (PERIPH_BASE_AHB + 0x00000)

#define	DMA1_BASE (PERIPH_BASE_AHB + 0x08000)

#define	DMA2_BASE (PERIPH_BASE_AHB + 0x08400)

#define	RCC_BASE (PERIPH_BASE_AHB + 0x09000)

#define	FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)

#define	CRC_BASE (PERIPH_BASE_AHB + 0x0b000)

#define	ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)

#define	USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000)

#define	DBGMCU_BASE (PPBI_BASE + 0x00042000)

#define	FSMC_BASE (PERIPH_BASE + 0x60000000)

#define	DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)

#define	DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)

#define	DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

#define	DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

#define	DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)

Macro Definition Documentation

◆ ADC1_BASE

#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)

Definition at line 83 of file stm32/f1/memorymap.h.

◆ ADC2_BASE

#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)

Definition at line 84 of file stm32/f1/memorymap.h.

◆ ADC3_BASE

#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)

Definition at line 89 of file stm32/f1/memorymap.h.

◆ AFIO_BASE

#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)

Definition at line 74 of file stm32/f1/memorymap.h.

◆ BACKUP_REGS_BASE

#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)

Definition at line 67 of file stm32/f1/memorymap.h.

◆ BX_CAN1_BASE

#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

Definition at line 64 of file stm32/f1/memorymap.h.

◆ BX_CAN2_BASE

#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

Definition at line 65 of file stm32/f1/memorymap.h.

◆ CEC_BASE

#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800)

Definition at line 70 of file stm32/f1/memorymap.h.

◆ CRC_BASE

#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)

Definition at line 107 of file stm32/f1/memorymap.h.

◆ DAC_BASE

#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

Definition at line 69 of file stm32/f1/memorymap.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE (PPBI_BASE + 0x00042000)

Definition at line 114 of file stm32/f1/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE

#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)

Definition at line 120 of file stm32/f1/memorymap.h.

◆ DESIG_UNIQUE_ID0

#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

Definition at line 123 of file stm32/f1/memorymap.h.

◆ DESIG_UNIQUE_ID1

#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

Definition at line 124 of file stm32/f1/memorymap.h.

◆ DESIG_UNIQUE_ID2

#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)

Definition at line 125 of file stm32/f1/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE

#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)

Definition at line 121 of file stm32/f1/memorymap.h.

◆ DMA1_BASE

#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)

Definition at line 101 of file stm32/f1/memorymap.h.

◆ DMA2_BASE

#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)

Definition at line 102 of file stm32/f1/memorymap.h.

◆ ETHERNET_BASE

#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)

Definition at line 109 of file stm32/f1/memorymap.h.

◆ EXTI_BASE

#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)

Definition at line 75 of file stm32/f1/memorymap.h.

◆ FLASH_BASE

#define FLASH_BASE (0x08000000U)

Definition at line 28 of file stm32/f1/memorymap.h.

◆ FLASH_MEM_INTERFACE_BASE

#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)

Definition at line 106 of file stm32/f1/memorymap.h.

◆ FSMC_BASE

#define FSMC_BASE (PERIPH_BASE + 0x60000000)

Definition at line 117 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_A_BASE

#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)

Definition at line 76 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_B_BASE

#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)

Definition at line 77 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_C_BASE

#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)

Definition at line 78 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_D_BASE

#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)

Definition at line 79 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_E_BASE

#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)

Definition at line 80 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_F_BASE

#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)

Definition at line 81 of file stm32/f1/memorymap.h.

◆ GPIO_PORT_G_BASE

#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)

Definition at line 82 of file stm32/f1/memorymap.h.

◆ I2C1_BASE

#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

Definition at line 59 of file stm32/f1/memorymap.h.

◆ I2C2_BASE

#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

Definition at line 60 of file stm32/f1/memorymap.h.

◆ INFO_BASE

#define INFO_BASE (0x1ffff000U)

Definition at line 30 of file stm32/f1/memorymap.h.

◆ IWDG_BASE

#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

Definition at line 50 of file stm32/f1/memorymap.h.

◆ PERIPH_BASE

#define PERIPH_BASE (0x40000000U)

Definition at line 29 of file stm32/f1/memorymap.h.

◆ PERIPH_BASE_AHB

#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)

Definition at line 33 of file stm32/f1/memorymap.h.

◆ PERIPH_BASE_APB1

#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

Definition at line 31 of file stm32/f1/memorymap.h.

◆ PERIPH_BASE_APB2

#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

Definition at line 32 of file stm32/f1/memorymap.h.

◆ POWER_CONTROL_BASE

#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

Definition at line 68 of file stm32/f1/memorymap.h.

◆ RCC_BASE

#define RCC_BASE (PERIPH_BASE_AHB + 0x09000)

Definition at line 104 of file stm32/f1/memorymap.h.

◆ RTC_BASE

#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

Definition at line 48 of file stm32/f1/memorymap.h.

◆ SDIO_BASE

#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)

Definition at line 99 of file stm32/f1/memorymap.h.

◆ SPI1_BASE

#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

Definition at line 86 of file stm32/f1/memorymap.h.

◆ SPI2_BASE

#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

Definition at line 52 of file stm32/f1/memorymap.h.

◆ SPI3_BASE

#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

Definition at line 53 of file stm32/f1/memorymap.h.

◆ TIM10_BASE

#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000)

Definition at line 94 of file stm32/f1/memorymap.h.

◆ TIM11_BASE

#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400)

Definition at line 95 of file stm32/f1/memorymap.h.

◆ TIM12_BASE

#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)

Definition at line 44 of file stm32/f1/memorymap.h.

◆ TIM13_BASE

#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)

Definition at line 45 of file stm32/f1/memorymap.h.

◆ TIM14_BASE

#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)

Definition at line 46 of file stm32/f1/memorymap.h.

◆ TIM15_BASE

#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)

Definition at line 90 of file stm32/f1/memorymap.h.

◆ TIM16_BASE

#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)

Definition at line 91 of file stm32/f1/memorymap.h.

◆ TIM17_BASE

#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)

Definition at line 92 of file stm32/f1/memorymap.h.

◆ TIM1_BASE

#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)

Definition at line 85 of file stm32/f1/memorymap.h.

◆ TIM2_BASE

#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

Definition at line 38 of file stm32/f1/memorymap.h.

◆ TIM3_BASE

#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

Definition at line 39 of file stm32/f1/memorymap.h.

◆ TIM4_BASE

#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

Definition at line 40 of file stm32/f1/memorymap.h.

◆ TIM5_BASE

#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

Definition at line 41 of file stm32/f1/memorymap.h.

◆ TIM6_BASE

#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

Definition at line 42 of file stm32/f1/memorymap.h.

◆ TIM7_BASE

#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

Definition at line 43 of file stm32/f1/memorymap.h.

◆ TIM8_BASE

#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)

Definition at line 87 of file stm32/f1/memorymap.h.

◆ TIM9_BASE

#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00)

Definition at line 93 of file stm32/f1/memorymap.h.

◆ UART4_BASE

#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

Definition at line 57 of file stm32/f1/memorymap.h.

◆ UART5_BASE

#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

Definition at line 58 of file stm32/f1/memorymap.h.

◆ USART1_BASE

#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)

Definition at line 88 of file stm32/f1/memorymap.h.

◆ USART2_BASE

#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

Definition at line 55 of file stm32/f1/memorymap.h.

◆ USART3_BASE

#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

Definition at line 56 of file stm32/f1/memorymap.h.

◆ USB_CAN_SRAM_BASE

#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)

Definition at line 63 of file stm32/f1/memorymap.h.

◆ USB_DEV_FS_BASE

#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)

Definition at line 61 of file stm32/f1/memorymap.h.

◆ USB_OTG_FS_BASE

#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000)

Definition at line 111 of file stm32/f1/memorymap.h.

◆ USB_PMA_BASE

#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)

Definition at line 62 of file stm32/f1/memorymap.h.

◆ WWDG_BASE

#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

Definition at line 49 of file stm32/f1/memorymap.h.

Macros