ISR ADC interrupt status register
Collaboration diagram for ISR ADC interrupt status register:
Macros | |
| #define | ADC_ISR_AWD1 (1 << 7) |
| AWD1: Analog watchdog 1 flag. More... | |
| #define | ADC_ISR_OVR (1 << 4) |
| OVR: Overrun flag. More... | |
| #define | ADC_ISR_EOS (1 << 3) |
| EOS: End of sequence conversions flag. More... | |
| #define | ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ |
| #define | ADC_ISR_EOC (1 << 2) |
| EOS: End of regular conversion flag. More... | |
| #define | ADC_ISR_EOSMP (1 << 1) |
| EOSMP: End of sampling flag. More... | |
| #define | ADC_ISR_ADRDY (1 << 0) |
| ADRDY: Ready flag. More... | |
Detailed Description
Macro Definition Documentation
◆ ADC_ISR_ADRDY
| #define ADC_ISR_ADRDY (1 << 0) |
ADRDY: Ready flag.
Definition at line 81 of file adc_common_v2.h.
◆ ADC_ISR_AWD1
| #define ADC_ISR_AWD1 (1 << 7) |
AWD1: Analog watchdog 1 flag.
Definition at line 70 of file adc_common_v2.h.
◆ ADC_ISR_EOC
| #define ADC_ISR_EOC (1 << 2) |
EOS: End of regular conversion flag.
Definition at line 77 of file adc_common_v2.h.
◆ ADC_ISR_EOS
| #define ADC_ISR_EOS (1 << 3) |
EOS: End of sequence conversions flag.
Definition at line 74 of file adc_common_v2.h.
◆ ADC_ISR_EOSEQ
| #define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ |
Definition at line 75 of file adc_common_v2.h.
◆ ADC_ISR_EOSMP
| #define ADC_ISR_EOSMP (1 << 1) |
EOSMP: End of sampling flag.
Definition at line 79 of file adc_common_v2.h.
◆ ADC_ISR_OVR
| #define ADC_ISR_OVR (1 << 4) |
OVR: Overrun flag.
Definition at line 72 of file adc_common_v2.h.
