libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
adc_common_v1_multi.h
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1/** @addtogroup adc_defines
2
3@author @htmlonly &copy; @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au>
4
5 */
6
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
11 * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
12 *
13 * This library is free software: you can redistribute it and/or modify
14 * it under the terms of the GNU Lesser General Public License as published by
15 * the Free Software Foundation, either version 3 of the License, or
16 * (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public License
24 * along with this library. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27/**@{*/
28
29/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
30The order of header inclusion is important. adc.h includes the device
31specific memorymap.h header before including this header file.*/
32
33/** @cond */
34#ifdef LIBOPENCM3_ADC_H
35/** @endcond */
36#ifndef LIBOPENCM3_ADC_COMMON_V1_MULTI_H
37#define LIBOPENCM3_ADC_COMMON_V1_MULTI_H
38
39#include <libopencm3/stm32/common/adc_common_v1.h>
40
41/* --- Convenience macros -------------------------------------------------- */
42
43
44/* ADC common (shared) registers */
45#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
46#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
47#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
48#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
49
50/* --- ADC Channels ------------------------------------------------------- */
51
52
53/* --- ADC_SR values ------------------------------------------------------- */
54
55/** @defgroup adc_sr_values ADC Status Register Flags
56 * @ingroup adc_defines
57 *@{*/
58
59/* OVR:*//** Overrun */
60#define ADC_SR_OVR (1 << 5)
61/**@}*/
62
63/* OVRIE: Overrun interrupt enable */
64#define ADC_CR1_OVRIE (1 << 26)
65
66/* RES[1:0]: Resolution */
67/****************************************************************************/
68/** @defgroup adc_cr1_res ADC Resolution.
69@ingroup adc_defines
70
71@{*/
72#define ADC_CR1_RES_12BIT (0x0 << 24)
73#define ADC_CR1_RES_10BIT (0x1 << 24)
74#define ADC_CR1_RES_8BIT (0x2 << 24)
75#define ADC_CR1_RES_6BIT (0x3 << 24)
76/**@}*/
77#define ADC_CR1_RES_MASK (0x3 << 24)
78#define ADC_CR1_RES_SHIFT 24
79
80/* Note: Bits [21:16] are reserved, and must be kept at reset value. */
81
82
83
84/* --- ADC_CR2 values ------------------------------------------------------ */
85
86/* SWSTART: Start conversion of regular channels. */
87#define ADC_CR2_SWSTART (1 << 30)
88
89/* EXTEN[1:0]: External trigger enable for regular channels. */
90/****************************************************************************/
91#define ADC_CR2_EXTEN_SHIFT 28
92#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT)
93/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity
94@ingroup adc_defines
95@{*/
96#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT)
97#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT)
98#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT)
99#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT)
100/**@}*/
101
102/* EXTSEL[3:0]: External event selection for regular group. */
103/****************************************************************************/
104/* Note: Selection values are family-dependent. */
105#define ADC_CR2_EXTSEL_MASK (0xF << 24)
106#define ADC_CR2_EXTSEL_SHIFT 24
107
108/* Bit 23 is reserved */
109
110/* JSWSTART: Start conversion of injected channels. */
111#define ADC_CR2_JSWSTART (1 << 22)
112
113/* JEXTEN[1:0]: External trigger enable for injected channels. */
114/****************************************************************************/
115#define ADC_CR2_JEXTEN_SHIFT 20
116#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT)
117/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity
118@ingroup adc_defines
119@{*/
120#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT)
121#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT)
122#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT)
123#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT)
124/**@}*/
125
126/* JEXTSEL[3:0]: External event selection for injected group. */
127/****************************************************************************/
128/* Note: Selection values are family-dependent. */
129#define ADC_CR2_JEXTSEL_SHIFT 16
130#define ADC_CR2_JEXTSEL_MASK (0xF << ADC_CR2_JEXTSEL_SHIFT)
131
132/* ALIGN: Data alignement. */
133#define ADC_CR2_ALIGN_RIGHT (0 << 11)
134#define ADC_CR2_ALIGN_LEFT (1 << 11)
135#define ADC_CR2_ALIGN (1 << 11)
136
137/* EOCS: End of conversion selection. */
138#define ADC_CR2_EOCS (1 << 10)
139
140/* DDS: DMA disable selection */
141#define ADC_CR2_DDS (1 << 9)
142
143/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
144#define ADC_CR2_DMA (1 << 8)
145
146/* Note: Bits [7:2] are reserved and must be kept at reset value. */
147
148/* CONT: Continuous conversion. */
149#define ADC_CR2_CONT (1 << 1)
150
151/* ADON: A/D converter On/Off. */
152/* Note: If any other bit in this register apart from ADON is changed at the
153 * same time, then conversion is not triggered. This is to prevent triggering
154 * an erroneous conversion.
155 * Conclusion: Must be separately written.
156 */
157#define ADC_CR2_ADON (1 << 0)
158
159
160/* --- ADC_SMPRx values --------------------------------------------------- */
161/****************************************************************************/
162
163#define ADC_SQRx_MASK 0x1f
164
165/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
166
167#define ADC_JDATA_LSB 0
168#define ADC_DATA_LSB 0
169#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
170#define ADC_DATA_MSK (0xffff << ADC_DA)
171
172/* --- Common Registers ---------------------------------------------------- */
173
174/* --- ADC_CSR values (read only images) ------------------------------------ */
175
176/* OVR3: Overrun ADC3. */
177#define ADC_CSR_OVR3 (1 << 21)
178
179/* STRT3: Regular channel start ADC3. */
180#define ADC_CSR_STRT3 (1 << 20)
181
182/* JSTRT3: Injected channel start ADC3. */
183#define ADC_CSR_JSTRT3 (1 << 19)
184
185/* JEOC3: Injected channel end of conversion ADC3. */
186#define ADC_CSR_JEOC3 (1 << 18)
187
188/* EOC3: Regular channel end of conversion ADC3. */
189#define ADC_CSR_EOC3 (1 << 17)
190
191/* EOC3: Regular channel end of conversion ADC3. */
192#define ADC_CSR_AWD3 (1 << 16)
193
194/* Bits 15:14 Reserved, must be kept at reset value */
195
196/* OVR2: Overrun ADC2. */
197#define ADC_CSR_OVR2 (1 << 13)
198
199/* STRT2: Regular channel start ADC2. */
200#define ADC_CSR_STRT2 (1 << 12)
201
202/* JSTRT2: Injected channel start ADC2. */
203#define ADC_CSR_JSTRT2 (1 << 11)
204
205/* JEOC2: Injected channel end of conversion ADC2. */
206#define ADC_CSR_JEOC2 (1 << 10)
207
208/* EOC2: Regular channel end of conversion ADC2. */
209#define ADC_CSR_EOC2 (1 << 9)
210
211/* EOC2: Regular channel end of conversion ADC2. */
212#define ADC_CSR_AWD2 (1 << 8)
213
214/* Bits 7:6 Reserved, must be kept at reset value */
215
216/* OVR1: Overrun ADC1. */
217#define ADC_CSR_OVR1 (1 << 5)
218
219/* STRT1: Regular channel start ADC1. */
220#define ADC_CSR_STRT1 (1 << 4)
221
222/* JSTRT1: Injected channel start ADC1. */
223#define ADC_CSR_JSTRT1 (1 << 3)
224
225/* JEOC1: Injected channel end of conversion ADC1. */
226#define ADC_CSR_JEOC1 (1 << 2)
227
228/* EOC1: Regular channel end of conversion ADC1. */
229#define ADC_CSR_EOC1 (1 << 1)
230
231/* EOC1: Regular channel end of conversion ADC1. */
232#define ADC_CSR_AWD1 (1 << 0)
233
234/* --- ADC_CCR values ------------------------------------------------------ */
235
236/* TSVREFE: Temperature sensor and Vrefint enable. */
237#define ADC_CCR_TSVREFE (1 << 23)
238
239/* VBATE: VBat enable. */
240#define ADC_CCR_VBATE (1 << 22)
241
242/* Bit 18:21 reserved, must be kept at reset value. */
243
244/* DMA: Direct memory access mode for multi ADC mode. */
245/****************************************************************************/
246/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode
247@ingroup adc_defines
248
249@{*/
250#define ADC_CCR_DMA_DISABLE (0x0 << 14)
251#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
252#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
253#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
254/**@}*/
255#define ADC_CCR_DMA_MASK (0x3 << 14)
256#define ADC_CCR_DMA_SHIFT 14
257
258/* DDS: DMA disable selection (for multi-ADC mode). */
259#define ADC_CCR_DDS (1 << 13)
260
261/* Bit 12 reserved, must be kept at reset value */
262
263/* DELAY: Delay between 2 sampling phases. */
264/****************************************************************************/
265/** @defgroup adc_delay ADC Delay between 2 sampling phases
266@ingroup adc_defines
267
268@{*/
269#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8)
270#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8)
271#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8)
272#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8)
273#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8)
274#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8)
275#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8)
276#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8)
277#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8)
278#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8)
279#define ADC_CCR_DELAY_15ADCCLK (0xa << 8)
280#define ADC_CCR_DELAY_16ADCCLK (0xb << 8)
281#define ADC_CCR_DELAY_17ADCCLK (0xc << 8)
282#define ADC_CCR_DELAY_18ADCCLK (0xd << 8)
283#define ADC_CCR_DELAY_19ADCCLK (0xe << 8)
284#define ADC_CCR_DELAY_20ADCCLK (0xf << 8)
285/**@}*/
286#define ADC_CCR_DELAY_MASK (0xf << 8)
287#define ADC_CCR_DELAY_SHIFT 8
288
289/* Bit 7:5 reserved, must be kept at reset value */
290
291/* MULTI: Multi ADC mode selection. */
292/****************************************************************************/
293/** @defgroup adc_multi_mode ADC Multi mode selection
294@ingroup adc_defines
295
296@{*/
297
298/** All ADCs independent */
299#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
300
301/* Dual modes (ADC1 + ADC2) */
302/**
303 * Dual modes (ADC1 + ADC2) Combined regular simultaneous +
304 * injected simultaneous mode.
305 */
306#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
307/**
308 * Dual modes (ADC1 + ADC2) Combined regular simultaneous +
309 * alternate trigger mode.
310 */
311#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
312/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
313#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
314/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
315#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
316/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
317#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
318/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
319#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
320
321/* Triple modes (ADC1 + ADC2 + ADC3) */
322/**
323 * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
324 * injected simultaneous mode.
325 */
326#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
327/**
328 * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
329 * alternate trigger mode.
330 */
331#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
332/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
333#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
334/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
335#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
336/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
337#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
338/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
339#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
340/**@}*/
341
342#define ADC_CCR_MULTI_MASK (0x1f << 0)
343#define ADC_CCR_MULTI_SHIFT 0
344
345/* --- ADC_CDR values ------------------------------------------------------ */
346
347#define ADC_CDR_DATA2_MASK (0xffff << 16)
348#define ADC_CDR_DATA2_SHIFT 16
349
350#define ADC_CDR_DATA1_MASK (0xffff << 0)
351#define ADC_CDR_DATA1_SHIFT 0
352
353BEGIN_DECLS
354
355void adc_set_clk_prescale(uint32_t prescaler);
356void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
357 uint32_t polarity);
358void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
359 uint32_t polarity);
360void adc_set_resolution(uint32_t adc, uint32_t resolution);
361void adc_enable_overrun_interrupt(uint32_t adc);
362void adc_disable_overrun_interrupt(uint32_t adc);
363bool adc_get_overrun_flag(uint32_t adc);
364void adc_clear_overrun_flag(uint32_t adc);
365bool adc_awd(uint32_t adc);
366void adc_eoc_after_each(uint32_t adc);
367void adc_eoc_after_group(uint32_t adc);
368void adc_set_dma_continue(uint32_t adc);
369void adc_set_dma_terminate(uint32_t adc);
370void adc_enable_temperature_sensor(void);
371void adc_disable_temperature_sensor(void);
372
373END_DECLS
374
375#endif
376/** @cond */
377#endif
378/** @endcond */
379/**@}*/
adc_common_v1.h
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
adc_disable_temperature_sensor
void adc_disable_temperature_sensor(void)
ADC Disable The Temperature Sensor.
Definition: adc_common_v1_multi.c:355
adc_disable_overrun_interrupt
void adc_disable_overrun_interrupt(uint32_t adc)
ADC Disable the Overrun Interrupt.
Definition: adc_common_v1_multi.c:227
adc_set_dma_terminate
void adc_set_dma_terminate(uint32_t adc)
ADC Set DMA to Terminate.
Definition: adc_common_v1_multi.c:316
adc_clear_overrun_flag
void adc_clear_overrun_flag(uint32_t adc)
ADC Clear Overrun Flags.
Definition: adc_common_v1_multi.c:259
adc_set_dma_continue
void adc_set_dma_continue(uint32_t adc)
ADC Set DMA to Continue.
Definition: adc_common_v1_multi.c:302
adc_set_resolution
void adc_set_resolution(uint32_t adc, uint32_t resolution)
ADC Set Resolution.
Definition: adc_common_v1_multi.c:197
adc_enable_external_trigger_regular
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity)
ADC Enable an External Trigger for Regular Channels.
Definition: adc_common_v1_multi.c:133
adc_enable_temperature_sensor
void adc_enable_temperature_sensor(void)
ADC Enable The Temperature Sensor.
Definition: adc_common_v1_multi.c:343
adc_eoc_after_each
void adc_eoc_after_each(uint32_t adc)
ADC Enable an EOC for Each Conversion.
Definition: adc_common_v1_multi.c:274
adc_enable_external_trigger_injected
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity)
ADC Enable an External Trigger for Injected Channels.
Definition: adc_common_v1_multi.c:166
adc_enable_overrun_interrupt
void adc_enable_overrun_interrupt(uint32_t adc)
ADC Enable the Overrun Interrupt.
Definition: adc_common_v1_multi.c:216
adc_awd
bool adc_awd(uint32_t adc)
ADC Read the Analog Watchdog Flag.
Definition: adc_common_v1_multi.c:329
adc_eoc_after_group
void adc_eoc_after_group(uint32_t adc)
ADC Disable the EOC for Each Conversion.
Definition: adc_common_v1_multi.c:288
adc_get_overrun_flag
bool adc_get_overrun_flag(uint32_t adc)
ADC Read the Overrun Flag.
Definition: adc_common_v1_multi.c:243
adc_set_clk_prescale
void adc_set_clk_prescale(uint32_t prescaler)
ADC Set Clock Prescale The ADC clock can be prescaled.
Definition: adc_common_v1_multi.c:114