Macros | |
| #define | ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) |
| All ADCs independent. More... | |
| #define | ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) |
| Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode. More... | |
| #define | ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) |
| Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. More... | |
| #define | ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) |
| Dual modes (ADC1 + ADC2) Injected simultaneous mode only. More... | |
| #define | ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) |
| Dual modes (ADC1 + ADC2) Regular simultaneous mode only. More... | |
| #define | ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) |
| Dual modes (ADC1 + ADC2) Interleaved mode only. More... | |
| #define | ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) |
| Dual modes (ADC1 + ADC2) Alternate trigger mode only. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. More... | |
| #define | ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. More... | |
Detailed Description
Macro Definition Documentation
◆ ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG
| #define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) |
Dual modes (ADC1 + ADC2) Alternate trigger mode only.
Definition at line 319 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_DUAL_INJECTED_SIMUL
| #define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) |
Dual modes (ADC1 + ADC2) Injected simultaneous mode only.
Definition at line 313 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_DUAL_INTERLEAVED
| #define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) |
Dual modes (ADC1 + ADC2) Interleaved mode only.
Definition at line 317 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG
| #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) |
Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode.
Definition at line 311 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL
| #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) |
Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode.
Definition at line 306 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_DUAL_REGULAR_SIMUL
| #define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) |
Dual modes (ADC1 + ADC2) Regular simultaneous mode only.
Definition at line 315 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_INDEPENDENT
| #define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) |
All ADCs independent.
Definition at line 299 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG
| #define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only.
Definition at line 339 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL
| #define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only.
Definition at line 333 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_INTERLEAVED
| #define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only.
Definition at line 337 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG
| #define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode.
Definition at line 331 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL
| #define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode.
Definition at line 326 of file adc_common_v1_multi.h.
◆ ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL
| #define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) |
Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only.
Definition at line 335 of file adc_common_v1_multi.h.
