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#define | ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) |
| All ADCs independent. More...
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#define | ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) |
| Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode. More...
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#define | ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) |
| Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. More...
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#define | ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) |
| Dual modes (ADC1 + ADC2) Injected simultaneous mode only. More...
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#define | ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) |
| Dual modes (ADC1 + ADC2) Regular simultaneous mode only. More...
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#define | ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) |
| Dual modes (ADC1 + ADC2) Interleaved mode only. More...
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#define | ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) |
| Dual modes (ADC1 + ADC2) Alternate trigger mode only. More...
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#define | ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode. More...
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#define | ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. More...
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#define | ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. More...
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#define | ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. More...
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#define | ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. More...
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#define | ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) |
| Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. More...
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