Collaboration diagram for TIMER peripheral API:

Functions
void	timer_enable_irq (uint32_t timer_peripheral, uint32_t irq)
	Enable Interrupts for a Timer. More...

void	timer_disable_irq (uint32_t timer_peripheral, uint32_t irq)
	Disable Interrupts for a Timer. More...

bool	timer_interrupt_source (uint32_t timer_peripheral, uint32_t flag)
	Return Interrupt Source. More...

bool	timer_get_flag (uint32_t timer_peripheral, uint32_t flag)
	Read a Status Flag. More...

void	timer_clear_flag (uint32_t timer_peripheral, uint32_t flag)
	Clear a Status Flag. More...

void	timer_set_mode (uint32_t timer_peripheral, uint32_t clock_div, uint32_t alignment, uint32_t direction)
	Set the Timer Mode. More...

void	timer_set_clock_division (uint32_t timer_peripheral, uint32_t clock_div)
	Set Input Filter and Dead-time Clock Divider Ratio. More...

void	timer_enable_preload (uint32_t timer_peripheral)
	Enable Auto-Reload Buffering. More...

void	timer_disable_preload (uint32_t timer_peripheral)
	Disable Auto-Reload Buffering. More...

void	timer_set_alignment (uint32_t timer_peripheral, uint32_t alignment)
	Specify the counter alignment mode. More...

void	timer_direction_up (uint32_t timer_peripheral)
	Set the Timer to Count Up. More...

void	timer_direction_down (uint32_t timer_peripheral)
	Set the Timer to Count Down. More...

void	timer_one_shot_mode (uint32_t timer_peripheral)
	Enable the Timer for One Cycle and Stop. More...

void	timer_continuous_mode (uint32_t timer_peripheral)
	Enable the Timer to Run Continuously. More...

void	timer_update_on_any (uint32_t timer_peripheral)
	Set the Timer to Generate Update IRQ or DMA on any Event. More...

void	timer_update_on_overflow (uint32_t timer_peripheral)
	Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events. More...

void	timer_enable_update_event (uint32_t timer_peripheral)
	Enable Timer Update Events. More...

void	timer_disable_update_event (uint32_t timer_peripheral)
	Disable Timer Update Events. More...

void	timer_enable_counter (uint32_t timer_peripheral)
	Enable the timer to start counting. More...

void	timer_disable_counter (uint32_t timer_peripheral)
	Stop the timer from counting. More...

void	timer_set_output_idle_state (uint32_t timer_peripheral, uint32_t outputs)
	Set Timer Output Idle States High. More...

void	timer_reset_output_idle_state (uint32_t timer_peripheral, uint32_t outputs)
	Set Timer Output Idle States Low. More...

void	timer_set_ti1_ch123_xor (uint32_t timer_peripheral)
	Set Timer 1 Input to XOR of Three Channels. More...

void	timer_set_ti1_ch1 (uint32_t timer_peripheral)
	Set Timer 1 Input to Channel 1. More...

void	timer_set_master_mode (uint32_t timer_peripheral, uint32_t mode)
	Set the Master Mode. More...

void	timer_set_dma_on_compare_event (uint32_t timer_peripheral)
	Set Timer DMA Requests on Capture/Compare Events. More...

void	timer_set_dma_on_update_event (uint32_t timer_peripheral)
	Set Timer DMA Requests on Update Events. More...

void	timer_enable_compare_control_update_on_trigger (uint32_t timer_peripheral)
	Enable Timer Capture/Compare Control Update with Trigger. More...

void	timer_disable_compare_control_update_on_trigger (uint32_t timer_peripheral)
	Disable Timer Capture/Compare Control Update with Trigger. More...

void	timer_enable_preload_complementry_enable_bits (uint32_t timer_peripheral)
	Enable Timer Capture/Compare Control Preload. More...

void	timer_disable_preload_complementry_enable_bits (uint32_t timer_peripheral)
	Disable Timer Capture/Compare Control Preload. More...

void	timer_set_prescaler (uint32_t timer_peripheral, uint32_t value)
	Set the Value for the Timer Prescaler. More...

void	timer_set_repetition_counter (uint32_t timer_peripheral, uint32_t value)
	Set the Value for the Timer Repetition Counter. More...

void	timer_set_period (uint32_t timer_peripheral, uint32_t period)
	Timer Set Period. More...

void	timer_enable_oc_clear (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Enable the Output Compare Clear Function. More...

void	timer_disable_oc_clear (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Disable the Output Compare Clear Function. More...

void	timer_set_oc_fast_mode (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Enable the Output Compare Fast Mode. More...

void	timer_set_oc_slow_mode (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Enable the Output Compare Slow Mode. More...

void	timer_set_oc_mode (uint32_t timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode)
	Timer Set Output Compare Mode. More...

void	timer_enable_oc_preload (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Enable the Output Compare Preload Register. More...

void	timer_disable_oc_preload (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Disable the Output Compare Preload Register. More...

void	timer_set_oc_polarity_high (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Set the Output Polarity High. More...

void	timer_set_oc_polarity_low (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Set the Output Polarity Low. More...

void	timer_enable_oc_output (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Enable the Output Compare. More...

void	timer_disable_oc_output (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Disable the Output Compare. More...

void	timer_set_oc_idle_state_set (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer set Output Compare Idle State High. More...

void	timer_set_oc_idle_state_unset (uint32_t timer_peripheral, enum tim_oc_id oc_id)
	Timer Set Output Compare Idle State Low. More...

void	timer_set_oc_value (uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
	Timer Set Output Compare Value. More...

void	timer_enable_break_main_output (uint32_t timer_peripheral)
	Enable Output in Break. More...

void	timer_disable_break_main_output (uint32_t timer_peripheral)
	Disable Output in Break. More...

void	timer_enable_break_automatic_output (uint32_t timer_peripheral)
	Enable Automatic Output in Break. More...

void	timer_disable_break_automatic_output (uint32_t timer_peripheral)
	Disable Automatic Output in Break. More...

void	timer_set_break_polarity_high (uint32_t timer_peripheral)
	Activate Break when Input High. More...

void	timer_set_break_polarity_low (uint32_t timer_peripheral)
	Activate Break when Input Low. More...

void	timer_enable_break (uint32_t timer_peripheral)
	Enable Break. More...

void	timer_disable_break (uint32_t timer_peripheral)
	Disable Break. More...

void	timer_set_enabled_off_state_in_run_mode (uint32_t timer_peripheral)
	Enable Off-State in Run Mode. More...

void	timer_set_disabled_off_state_in_run_mode (uint32_t timer_peripheral)
	Disable Off-State in Run Mode. More...

void	timer_set_enabled_off_state_in_idle_mode (uint32_t timer_peripheral)
	Enable Off-State in Idle Mode. More...

void	timer_set_disabled_off_state_in_idle_mode (uint32_t timer_peripheral)
	Disable Off-State in Idle Mode. More...

void	timer_set_break_lock (uint32_t timer_peripheral, uint32_t lock)
	Set Lock Bits. More...

void	timer_set_deadtime (uint32_t timer_peripheral, uint32_t deadtime)
	Set Deadtime. More...

void	timer_generate_event (uint32_t timer_peripheral, uint32_t event)
	Force generate a timer event. More...

uint32_t	timer_get_counter (uint32_t timer_peripheral)
	Read Counter. More...

void	timer_set_counter (uint32_t timer_peripheral, uint32_t count)
	Set Counter. More...

void	timer_ic_set_filter (uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt)
	Set Input Capture Filter Parameters. More...

void	timer_ic_set_prescaler (uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc)
	Set Input Capture Prescaler. More...

void	timer_ic_set_input (uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in)
	Set Capture/Compare Channel Direction/Input. More...

void	timer_ic_enable (uint32_t timer_peripheral, enum tim_ic_id ic)
	Enable Timer Input Capture. More...

void	timer_ic_disable (uint32_t timer_peripheral, enum tim_ic_id ic)
	Disable Timer Input Capture. More...

void	timer_slave_set_filter (uint32_t timer_peripheral, enum tim_ic_filter flt)
	Set External Trigger Filter Parameters for Slave. More...

void	timer_slave_set_prescaler (uint32_t timer_peripheral, enum tim_ic_psc psc)
	Set External Trigger Prescaler for Slave. More...

void	timer_slave_set_polarity (uint32_t timer_peripheral, enum tim_et_pol pol)
	Set External Trigger Polarity for Slave. More...

void	timer_slave_set_mode (uint32_t timer_peripheral, uint8_t mode)
	Set Slave Mode. More...

void	timer_slave_set_trigger (uint32_t timer_peripheral, uint8_t trigger)
	Set Slave Trigger Source. More...

void	timer_slave_set_extclockmode2 (uint32_t timer_peripheral, enum tim_ecm2_state state)
	Set External Clock Mode 2. More...

Detailed Description

Author: © 2010 Edward Cheeseman evbui.nosp@m.lder.nosp@m.@user.nosp@m.s.so.nosp@m.urcef.nosp@m.orge.nosp@m..org; © 2011 Stephen Caudle scaud.nosp@m.le@d.nosp@m.oceme.nosp@m..com

Notes for All Timers

This library supports the General Purpose and Advanced Control Timers for the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.

The STM32 series have four general purpose timers (2-5), while some have an additional two advanced timers (1,8), and some have two basic timers (6,7). Some of the larger devices have additional general purpose timers (9-14).

Basic TIMER handling API.

Enable the timer clock first. The timer mode sets the clock division ratio, the count alignment (edge or centred) and count direction. Finally enable the timer.

The timer output compare block produces a signal that can be configured for output to a pin or passed to other peripherals for use as a trigger. In all cases the output compare mode must be set to define how the output responds to a compare match, and the output must be enabled. If output to a pin is required, enable the appropriate GPIO clock and set the pin to alternate output mode.

Example: Timer 2 with 2x clock divide, edge aligned and up counting.

rcc_periph_clock_enable(RCC_TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT_MUL_2,
               TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
...
timer_set_period(TIM2, 1000);
timer_enable_counter(TIM2);

Example: Timer 1 with PWM output, no clock divide and centre alignment. Set the Output Compare mode to PWM and enable the output of channel 1. Note that for the advanced timers the break functionality must be enabled before the signal will appear at the output, even though break is not being used. This is in addition to the normal output enable. Enable the alternate function clock (APB2 only) and port A clock. Set port A8 (timer 1 channel 1 compare output) to alternate function push-pull output where the PWM output will appear.

rcc_periph_clock_enable(RCC_TIM1);
rcc_periph_clock_enable(RCC_GPIOA);
 
// for F1....
rcc_periph_clock_enable(RCC_AFIO);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8);
// For anyone else
gpio_set_output_options(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO8);
// End of family specific
 
rcc_periph_clock_enable(RCC_TIM1);
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1,
               TIM_CR1_DIR_UP);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2);
timer_enable_oc_output(TIM1, TIM_OC1);
timer_enable_break_main_output(TIM1);
timer_set_oc_value(TIM1, TIM_OC1, 200);
timer_set_period(TIM1, 1000);
timer_enable_counter(TIM1);

Example: Timer 3 as a Quadrature encoder counting input from a motor or control knob.

rcc_periph_clock_enable(RCC_TIM3);
timer_set_period(TIM3, 1024);
timer_slave_set_mode(TIM3, 0x3); // encoder
timer_ic_set_input(TIM3, TIM_IC1, TIM_IC_IN_TI1);
timer_ic_set_input(TIM3, TIM_IC2, TIM_IC_IN_TI2);
timer_enable_counter(TIM3);
...
int motor_pos = timer_get_count(TIM3);

Function Documentation

◆ timer_clear_flag()

void timer_clear_flag	(	uint32_t	timer_peripheral,
		uint32_t	flag
	)

Clear a Status Flag.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	flag	Unsigned int32. TIMx_SR Timer Status Register Flags. Status register flag.

Definition at line 203 of file timer_common_all.c.

References TIM_SR.

◆ timer_continuous_mode()

void timer_continuous_mode ( uint32_t timer_peripheral )

Enable the Timer to Run Continuously.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 365 of file timer_common_all.c.

References TIM_CR1.

◆ timer_direction_down()

void timer_direction_down ( uint32_t timer_peripheral )

Set the Timer to Count Down.

This has no effect if the timer is set to center aligned.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 341 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_DIR_DOWN.

◆ timer_direction_up()

void timer_direction_up ( uint32_t timer_peripheral )

Set the Timer to Count Up.

This has no effect if the timer is set to center aligned.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 327 of file timer_common_all.c.

References TIM_CR1.

◆ timer_disable_break()

void timer_disable_break ( uint32_t timer_peripheral )

Disable Break.

Disables the break function of an advanced timer.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1476 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_disable_break_automatic_output()

void timer_disable_break_automatic_output ( uint32_t timer_peripheral )

Disable Automatic Output in Break.

Disables the automatic output feature of the Break function of an advanced timer so that the output is re-enabled at the next update event following a break event.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1412 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_disable_break_main_output()

void timer_disable_break_main_output ( uint32_t timer_peripheral )

Disable Output in Break.

Disables the output in the Break feature of an advanced timer. This clears the Master Output Enable in the Break and Deadtime Register.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1376 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_disable_compare_control_update_on_trigger()

void timer_disable_compare_control_update_on_trigger ( uint32_t timer_peripheral )

Disable Timer Capture/Compare Control Update with Trigger.

If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (timer_generate_event).

Note: This setting is only valid for the advanced timer channels with complementary outputs.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 600 of file timer_common_all.c.

References TIM_CR2.

◆ timer_disable_counter()

void timer_disable_counter ( uint32_t timer_peripheral )

Stop the timer from counting.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 447 of file timer_common_all.c.

References TIM_CR1.

◆ timer_disable_irq()

void timer_disable_irq	(	uint32_t	timer_peripheral,
		uint32_t	irq
	)

Disable Interrupts for a Timer.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	irq	Unsigned int32. TIMx_DIER Timer DMA and Interrupt Enable Values. Logical OR of all interrupt enable bits to be cleared

Definition at line 145 of file timer_common_all.c.

References TIM_DIER.

◆ timer_disable_oc_clear()

void timer_disable_oc_clear	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Disable the Output Compare Clear Function.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)

Definition at line 736 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_disable_oc_output()

void timer_disable_oc_output	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Disable the Output Compare.

The channel output compare functionality is disabled.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1193 of file timer_common_all.c.

References TIM_CCER, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_disable_oc_preload()

void timer_disable_oc_preload	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Disable the Output Compare Preload Register.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action)

Definition at line 1041 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_disable_preload()

void timer_disable_preload ( uint32_t timer_peripheral )

Disable Auto-Reload Buffering.

This causes the counter to be loaded immediately with a new count value when the auto-reload register is written, so that the new value becomes effective for the current count cycle rather than for the cycle following an update event.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 296 of file timer_common_all.c.

References TIM_CR1.

◆ timer_disable_preload_complementry_enable_bits()

void timer_disable_preload_complementry_enable_bits ( uint32_t timer_peripheral )

Disable Timer Capture/Compare Control Preload.

The capture/compare control bits CCxE, CCxNE and OCxM preload is disabled.

Note: This setting is only valid for the advanced timer channels with complementary outputs.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 635 of file timer_common_all.c.

References TIM_CR2.

◆ timer_disable_update_event()

void timer_disable_update_event ( uint32_t timer_peripheral )

Disable Timer Update Events.

Update events are not generated and the shadow registers keep their values.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 421 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_UDIS.

◆ timer_enable_break()

void timer_enable_break ( uint32_t timer_peripheral )

Enable Break.

Enables the break function of an advanced timer.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1460 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_BKE.

◆ timer_enable_break_automatic_output()

void timer_enable_break_automatic_output ( uint32_t timer_peripheral )

Enable Automatic Output in Break.

Enables the automatic output feature of the Break function of an advanced timer so that the output is re-enabled at the next update event following a break event.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1394 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_AOE.

◆ timer_enable_break_main_output()

void timer_enable_break_main_output ( uint32_t timer_peripheral )

Enable Output in Break.

Enables the output in the Break feature of an advanced timer. This does not enable the break functionality itself but only sets the Master Output Enable in the Break and Deadtime Register.

Note: Not all timers support Break/Deadtime features; It is necessary to call this function to enable the output on an advanced timer even if break or deadtime features are not being used.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1359 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_MOE.

◆ timer_enable_compare_control_update_on_trigger()

void timer_enable_compare_control_update_on_trigger ( uint32_t timer_peripheral )

Enable Timer Capture/Compare Control Update with Trigger.

If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (timer_generate_event) or when a rising edge occurs on the trigger input TRGI.

Note: This setting is only valid for the advanced timer channels with complementary outputs.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 581 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_CCUS.

◆ timer_enable_counter()

void timer_enable_counter ( uint32_t timer_peripheral )

Enable the timer to start counting.

This should be called after the timer initial configuration has been completed.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 435 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_CEN.

◆ timer_enable_irq()

void timer_enable_irq	(	uint32_t	timer_peripheral,
		uint32_t	irq
	)

Enable Interrupts for a Timer.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	irq	Unsigned int32. TIMx_DIER Timer DMA and Interrupt Enable Values. Logical OR of all interrupt enable bits to be set

Definition at line 131 of file timer_common_all.c.

References TIM_DIER.

◆ timer_enable_oc_clear()

void timer_enable_oc_clear	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Enable the Output Compare Clear Function.

When this is enabled, the output compare signal is cleared when a high is detected on the external trigger input. This works in the output compare and PWM modes only (not forced mode). The output compare signal remains off until the next update event.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)

Definition at line 702 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR1_OC1CE, TIM_CCMR1_OC2CE, TIM_CCMR2, TIM_CCMR2_OC3CE, TIM_CCMR2_OC4CE, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_enable_oc_output()

void timer_enable_oc_output	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Enable the Output Compare.

The channel output compare functionality is enabled.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1154 of file timer_common_all.c.

References TIM_CCER, TIM_CCER_CC1E, TIM_CCER_CC1NE, TIM_CCER_CC2E, TIM_CCER_CC2NE, TIM_CCER_CC3E, TIM_CCER_CC3NE, TIM_CCER_CC4E, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_enable_oc_preload()

void timer_enable_oc_preload	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Enable the Output Compare Preload Register.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)

Definition at line 1009 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR1_OC1PE, TIM_CCMR1_OC2PE, TIM_CCMR2, TIM_CCMR2_OC3PE, TIM_CCMR2_OC4PE, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_enable_preload()

void timer_enable_preload ( uint32_t timer_peripheral )

Enable Auto-Reload Buffering.

During counter operation this causes the counter to be loaded from its auto-reload register only at the next update event.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 280 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_ARPE.

◆ timer_enable_preload_complementry_enable_bits()

void timer_enable_preload_complementry_enable_bits ( uint32_t timer_peripheral )

Enable Timer Capture/Compare Control Preload.

The capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded when a COM event occurs.

Note: This setting is only valid for the advanced timer channels with complementary outputs.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 618 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_CCPC.

◆ timer_enable_update_event()

void timer_enable_update_event ( uint32_t timer_peripheral )

Enable Timer Update Events.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 407 of file timer_common_all.c.

References TIM_CR1.

◆ timer_generate_event()

void timer_generate_event	(	uint32_t	timer_peripheral,
		uint32_t	event
	)

Force generate a timer event.

The event specification consists of 8 possible events that can be forced on the timer. The forced events are automatically cleared by hardware. The UG event is useful to cause shadow registers to be preloaded before the timer is started to avoid uncertainties in the first cycle in case an update event may never be generated.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	event	Unsigned int32. Event specification TIMx_EGR Timer Event Generator Values

Definition at line 1612 of file timer_common_all.c.

References TIM_EGR.

◆ timer_get_counter()

uint32_t timer_get_counter ( uint32_t timer_peripheral )

Read Counter.

Read back the value of a timer's counter register contents

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base

Returns: Unsigned int32. Counter value.

Definition at line 1626 of file timer_common_all.c.

References TIM_CNT.

◆ timer_get_flag()

bool timer_get_flag	(	uint32_t	timer_peripheral,
		uint32_t	flag
	)

Read a Status Flag.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	flag	Unsigned int32. Status register flag TIMx_SR Timer Status Register Flags.

Returns: boolean: flag set.

Definition at line 186 of file timer_common_all.c.

References TIM_SR.

◆ timer_ic_disable()

void timer_ic_disable	(	uint32_t	timer_peripheral,
		enum tim_ic_id	ic
	)

Disable Timer Input Capture.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	ic	tim_ic_id. Input Capture channel designator.

Definition at line 1786 of file timer_common_all.c.

References TIM_CCER.

◆ timer_ic_enable()

void timer_ic_enable	(	uint32_t	timer_peripheral,
		enum tim_ic_id	ic
	)

Enable Timer Input Capture.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	ic	tim_ic_id. Input Capture channel designator.

Definition at line 1774 of file timer_common_all.c.

References TIM_CCER.

◆ timer_ic_set_filter()

void timer_ic_set_filter	(	uint32_t	timer_peripheral,
		enum tim_ic_id	ic,
		enum tim_ic_filter	flt
	)

Set Input Capture Filter Parameters.

Set the input filter parameters for an input channel, specifying:

the frequency of sampling from the Deadtime and Sampling clock (
See also
timer_set_clock_division)
the number of events that must occur before a transition is considered valid.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	ic	tim_ic_id. Input Capture channel designator.
[in]	flt	tim_ic_filter. Input Capture Filter identifier.

Definition at line 1659 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_IC1, TIM_IC2, TIM_IC3, and TIM_IC4.

◆ timer_ic_set_input()

void timer_ic_set_input	(	uint32_t	timer_peripheral,
		enum tim_ic_id	ic,
		enum tim_ic_input	in
	)

Set Capture/Compare Channel Direction/Input.

The Capture/Compare channel is defined as output (compare) or input with the input mapping specified:

channel is configured as output
channel is configured as input and mapped on corresponding input
channel is configured as input and mapped on alternate input (TI2 for channel 1, TI1 for channel 2, TI4 for channel 3, TI3 for channel 4)
channel is configured as input and is mapped on TRC (requires an internal trigger input selected through TS bit

Note: not all combinations of the input and channel are valid, see datasheets.; these parameters are writable only when the channel is off.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	ic	tim_ic_id. Input Capture channel designator.
[in]	in	tim_ic_input. Input Capture channel direction and source input.

Definition at line 1736 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_IC1, TIM_IC2, TIM_IC3, TIM_IC4, TIM_IC_IN_TI1, and TIM_IC_IN_TI2.

◆ timer_ic_set_prescaler()

void timer_ic_set_prescaler	(	uint32_t	timer_peripheral,
		enum tim_ic_id	ic,
		enum tim_ic_psc	psc
	)

Set Input Capture Prescaler.

Set the number of events between each capture.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	ic	tim_ic_id. Input Capture channel designator.
[in]	psc	tim_ic_psc. Input Capture sample clock prescaler.

Definition at line 1692 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_IC1, TIM_IC2, TIM_IC3, and TIM_IC4.

◆ timer_interrupt_source()

bool timer_interrupt_source	(	uint32_t	timer_peripheral,
		uint32_t	flag
	)

Return Interrupt Source.

Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF for advanced timers) was set and the interrupt was enabled. If the specified flag is not an interrupt flag, the function returns false.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	flag	Unsigned int32. Status register flag TIMx_SR Timer Status Register Flags.

Returns: boolean: flag set.

Definition at line 166 of file timer_common_all.c.

References TIM_DIER, TIM_SR, and TIM_SR_BIF.

◆ timer_one_shot_mode()

void timer_one_shot_mode ( uint32_t timer_peripheral )

Enable the Timer for One Cycle and Stop.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 353 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_OPM.

◆ timer_reset_output_idle_state()

void timer_reset_output_idle_state	(	uint32_t	timer_peripheral,
		uint32_t	outputs
	)

Set Timer Output Idle States Low.

This determines the value of the timer output compare when it enters idle state.

See also: timer_set_oc_idle_state_unset

Note: This setting is only valid for the advanced timers.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	outputs	Unsigned int32. Timer Output Idle State Controls TIMx_CR2_OIS: Force Output Idle State Control Values

Definition at line 488 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_OIS_MASK.

◆ timer_set_alignment()

void timer_set_alignment	(	uint32_t	timer_peripheral,
		uint32_t	alignment
	)

Specify the counter alignment mode.

The mode can be edge aligned or centered.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	alignment	Unsigned int32. Alignment bits in 5,6: TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection

Definition at line 311 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_CMS_MASK.

◆ timer_set_break_lock()

void timer_set_break_lock	(	uint32_t	timer_peripheral,
		uint32_t	lock
	)

Set Lock Bits.

Set the lock bits for an advanced timer. Three levels of lock providing protection against software errors. Once written they cannot be changed until a timer reset has occurred.

Note: Not all timers support Break/Deadtime features

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base TIM1 or TIM8
[in]	lock	Unsigned int32. Lock specification TIM_BDTR_LOCK Timer Lock Values

Definition at line 1569 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_set_break_polarity_high()

void timer_set_break_polarity_high ( uint32_t timer_peripheral )

Activate Break when Input High.

Sets the break function to activate when the break input becomes high.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1428 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_BKP.

◆ timer_set_break_polarity_low()

void timer_set_break_polarity_low ( uint32_t timer_peripheral )

Activate Break when Input Low.

Sets the break function to activate when the break input becomes low.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1444 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_set_clock_division()

void timer_set_clock_division	(	uint32_t	timer_peripheral,
		uint32_t	clock_div
	)

Set Input Filter and Dead-time Clock Divider Ratio.

This forms the sampling clock for the input filters and the dead-time clock in the advanced timers 1 and 8, by division from the timer clock.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	clock_div	Unsigned int32. Clock Divider Ratio in bits 8,9: TIMx_CR1 CKD[1:0] Clock Division Ratio

Definition at line 263 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_CKD_CK_INT_MASK.

◆ timer_set_counter()

void timer_set_counter	(	uint32_t	timer_peripheral,
		uint32_t	count
	)

Set Counter.

Set the value of a timer's counter register contents.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	count	Unsigned int32. Counter value.

Definition at line 1640 of file timer_common_all.c.

References TIM_CNT.

◆ timer_set_deadtime()

void timer_set_deadtime	(	uint32_t	timer_peripheral,
		uint32_t	deadtime
	)

Set Deadtime.

The deadtime and sampling clock (DTSC) is set in the clock division ratio part of the timer mode settings. The deadtime count is an 8 bit value defined in terms of the number of DTSC cycles:

Bit 7 = 0, deadtime = bits(6:0)
Bits 7:6 = 10, deadtime = 2x(64+bits(5:0))
Bits 7:5 = 110, deadtime = 8x(32+bits(5:0))
Bits 7:5 = 111, deadtime = 16x(32+bits(5:0))

Note: Not all timers support Break/Deadtime features

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base TIM1 or TIM8
[in]	deadtime	Unsigned int32. Deadtime count specification as defined above.

Definition at line 1594 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_set_disabled_off_state_in_idle_mode()

void timer_set_disabled_off_state_in_idle_mode ( uint32_t timer_peripheral )

Disable Off-State in Idle Mode.

Disables the off-state in idle mode for the break function of an advanced timer. When the master output is disabled the output is also disabled.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1550 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_set_disabled_off_state_in_run_mode()

void timer_set_disabled_off_state_in_run_mode ( uint32_t timer_peripheral )

Disable Off-State in Run Mode.

Disables the off-state in run mode for the break function of an advanced timer in which the complementary outputs have been configured. It has no effect if no complementary output is present. When the capture-compare output is disabled, the output is also disabled.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1515 of file timer_common_all.c.

References TIM_BDTR.

◆ timer_set_dma_on_compare_event()

void timer_set_dma_on_compare_event ( uint32_t timer_peripheral )

Set Timer DMA Requests on Capture/Compare Events.

Capture/compare events will cause DMA requests to be generated.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 548 of file timer_common_all.c.

References TIM_CR2.

◆ timer_set_dma_on_update_event()

void timer_set_dma_on_update_event ( uint32_t timer_peripheral )

Set Timer DMA Requests on Update Events.

Update events will cause DMA requests to be generated.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 562 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_CCDS.

◆ timer_set_enabled_off_state_in_idle_mode()

void timer_set_enabled_off_state_in_idle_mode ( uint32_t timer_peripheral )

Enable Off-State in Idle Mode.

Enables the off-state in idle mode for the break function of an advanced timer. When the master output is disabled the output is set to its inactive level as defined by the output polarity.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1533 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_OSSI.

◆ timer_set_enabled_off_state_in_run_mode()

void timer_set_enabled_off_state_in_run_mode ( uint32_t timer_peripheral )

Enable Off-State in Run Mode.

Enables the off-state in run mode for the break function of an advanced timer in which the complementary outputs have been configured. It has no effect if no complementary output is present. When the capture-compare output is disabled while the complementary output is enabled, the output is set to its inactive level as defined by the output polarity.

Note: Not all timers support Break/Deadtime features

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8

Definition at line 1496 of file timer_common_all.c.

References TIM_BDTR, and TIM_BDTR_OSSR.

◆ timer_set_master_mode()

void timer_set_master_mode	(	uint32_t	timer_peripheral,
		uint32_t	mode
	)

Set the Master Mode.

This sets the Trigger Output TRGO for synchronizing with slave timers or passing as an internal trigger to the ADC or DAC.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	mode	Unsigned int32. Master Mode TIMx_CR2 MMS[6:4]: Master Mode Selection

Definition at line 533 of file timer_common_all.c.

References TIM_CR2.

◆ timer_set_mode()

void timer_set_mode	(	uint32_t	timer_peripheral,
		uint32_t	clock_div,
		uint32_t	alignment,
		uint32_t	direction
	)

Set the Timer Mode.

The modes are:

Clock divider ratio (to form the sampling clock for the input filters, and the dead-time clock in the advanced timers 1 and 8)
Edge/centre alignment
Count direction

The alignment and count direction are effective only for timers 1 to 5 and 8 while the clock divider ratio is effective for all timers except 6,7 The remaining timers are limited hardware timers which do not support these mode settings.

Note: : When center alignment mode is selected, count direction is controlled by hardware and cannot be written. The count direction setting has no effect in this case.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses (TIM1, TIM2 ... TIM5, TIM8)
[in]	clock_div	Unsigned int32. Clock Divider Ratio in bits 8,9: TIMx_CR1 CKD[1:0] Clock Division Ratio
[in]	alignment	Unsigned int32. Alignment bits in 5,6: TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
[in]	direction	Unsigned int32. Count direction in bit 4,: TIMx_CR1 DIR: Direction

Definition at line 237 of file timer_common_all.c.

References TIM_CR1, TIM_CR1_CKD_CK_INT_MASK, TIM_CR1_CMS_MASK, and TIM_CR1_DIR_DOWN.

◆ timer_set_oc_fast_mode()

void timer_set_oc_fast_mode	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Enable the Output Compare Fast Mode.

When this is enabled, the output compare signal is forced to the compare state by a trigger input, independently of the compare match. This speeds up the setting of the output compare to 3 clock cycles as opposed to at least 5 in the slow mode. This works in the PWM1 and PWM2 modes only.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)

Definition at line 775 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR1_OC1FE, TIM_CCMR1_OC2FE, TIM_CCMR2, TIM_CCMR2_OC3FE, TIM_CCMR2_OC4FE, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_idle_state_set()

void timer_set_oc_idle_state_set	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer set Output Compare Idle State High.

See also: Similar function suitable for multiple OC idle state settings timer_set_output_idle_state

Note: This setting is only valid for the advanced timers.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1235 of file timer_common_all.c.

References TIM_CR2, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_CR2_OIS2, TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_idle_state_unset()

void timer_set_oc_idle_state_unset	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Set Output Compare Idle State Low.

See also: Similar function suitable for multiple OC idle state settings timer_reset_output_idle_state

Note: This setting is only valid for the advanced timers.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1278 of file timer_common_all.c.

References TIM_CR2, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_mode()

void timer_set_oc_mode	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id,
		enum tim_oc_mode	oc_mode
	)

Timer Set Output Compare Mode.

Specifies how the comparator output will respond to a compare match. The mode can be:

Frozen - the output does not respond to a match.
Active - the output assumes the active state on the first match.
Inactive - the output assumes the inactive state on the first match.
Toggle - The output switches between active and inactive states on each match.
Force inactive. The output is forced low regardless of the compare state.
Force active. The output is forced high regardless of the compare state.
PWM1 - The output is active when the counter is less than the compare register contents and inactive otherwise.
PWM2 - The output is inactive when the counter is less than the compare register contents and active otherwise.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
[in]	oc_mode	enum tim_oc_mode. OC mode designators. TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, TIM_OCM_TOGGLE, TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, TIM_OCM_PWM1, TIM_OCM_PWM2

Definition at line 860 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR1_CC1S_OUT, TIM_CCMR1_CC2S_OUT, TIM_CCMR1_OC1M_ACTIVE, TIM_CCMR1_OC1M_FORCE_HIGH, TIM_CCMR1_OC1M_FORCE_LOW, TIM_CCMR1_OC1M_FROZEN, TIM_CCMR1_OC1M_INACTIVE, TIM_CCMR1_OC1M_PWM1, TIM_CCMR1_OC1M_PWM2, TIM_CCMR1_OC1M_TOGGLE, TIM_CCMR1_OC2M_ACTIVE, TIM_CCMR1_OC2M_FORCE_HIGH, TIM_CCMR1_OC2M_FORCE_LOW, TIM_CCMR1_OC2M_FROZEN, TIM_CCMR1_OC2M_INACTIVE, TIM_CCMR1_OC2M_PWM1, TIM_CCMR1_OC2M_PWM2, TIM_CCMR1_OC2M_TOGGLE, TIM_CCMR2, TIM_CCMR2_CC3S_OUT, TIM_CCMR2_CC4S_OUT, TIM_CCMR2_OC3M_ACTIVE, TIM_CCMR2_OC3M_FORCE_HIGH, TIM_CCMR2_OC3M_FORCE_LOW, TIM_CCMR2_OC3M_FROZEN, TIM_CCMR2_OC3M_INACTIVE, TIM_CCMR2_OC3M_PWM1, TIM_CCMR2_OC3M_PWM2, TIM_CCMR2_OC3M_TOGGLE, TIM_CCMR2_OC4M_ACTIVE, TIM_CCMR2_OC4M_FORCE_HIGH, TIM_CCMR2_OC4M_FORCE_LOW, TIM_CCMR2_OC4M_FROZEN, TIM_CCMR2_OC4M_INACTIVE, TIM_CCMR2_OC4M_PWM1, TIM_CCMR2_OC4M_PWM2, TIM_CCMR2_OC4M_TOGGLE, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, TIM_OC4, TIM_OCM_ACTIVE, TIM_OCM_FORCE_HIGH, TIM_OCM_FORCE_LOW, TIM_OCM_FROZEN, TIM_OCM_INACTIVE, TIM_OCM_PWM1, TIM_OCM_PWM2, and TIM_OCM_TOGGLE.

◆ timer_set_oc_polarity_high()

void timer_set_oc_polarity_high	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Set the Output Polarity High.

The polarity of the channel output is set active high.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1076 of file timer_common_all.c.

References TIM_CCER, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_polarity_low()

void timer_set_oc_polarity_low	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Set the Output Polarity Low.

The polarity of the channel output is set active low.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)

Definition at line 1115 of file timer_common_all.c.

References TIM_CCER, TIM_CCER_CC1NP, TIM_CCER_CC1P, TIM_CCER_CC2NP, TIM_CCER_CC2P, TIM_CCER_CC3NP, TIM_CCER_CC3P, TIM_CCER_CC4P, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_slow_mode()

void timer_set_oc_slow_mode	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id
	)

Timer Enable the Output Compare Slow Mode.

This disables the fast compare mode and the output compare depends on the counter and compare register values.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)

Definition at line 810 of file timer_common_all.c.

References TIM_CCMR1, TIM_CCMR2, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_oc_value()

void timer_set_oc_value	(	uint32_t	timer_peripheral,
		enum tim_oc_id	oc_id,
		uint32_t	value
	)

Timer Set Output Compare Value.

This is a convenience function to set the OC preload register value for loading to the compare register.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses (TIM9 .. TIM14 not yet supported here).
[in]	oc_id	enum tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
[in]	value	Unsigned int32. Compare value.

Definition at line 1319 of file timer_common_all.c.

References TIM_CCR1, TIM_CCR2, TIM_CCR3, TIM_CCR4, TIM_OC1, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, and TIM_OC4.

◆ timer_set_output_idle_state()

void timer_set_output_idle_state	(	uint32_t	timer_peripheral,
		uint32_t	outputs
	)

Set Timer Output Idle States High.

This determines the value of the timer output compare when it enters idle state.

See also: timer_set_oc_idle_state_set

Note: This setting is only valid for the advanced timers.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	outputs	Unsigned int32. Timer Output Idle State Controls TIMx_CR2_OIS: Force Output Idle State Control Values. If several settings are to be made, use the logical OR of the output control values.

Definition at line 468 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_OIS_MASK.

◆ timer_set_period()

void timer_set_period	(	uint32_t	timer_peripheral,
		uint32_t	period
	)

Timer Set Period.

Specify the timer period in the auto-reload register.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	period	Unsigned int32. Period in counter clock ticks.

Definition at line 683 of file timer_common_all.c.

References TIM_ARR.

◆ timer_set_prescaler()

void timer_set_prescaler	(	uint32_t	timer_peripheral,
		uint32_t	value
	)

Set the Value for the Timer Prescaler.

The timer clock is prescaled by the 16 bit scale value plus 1.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	value	Unsigned int32. Prescaler values 0...0xFFFF.

Definition at line 650 of file timer_common_all.c.

References TIM_PSC.

◆ timer_set_repetition_counter()

void timer_set_repetition_counter	(	uint32_t	timer_peripheral,
		uint32_t	value
	)

Set the Value for the Timer Repetition Counter.

A timer update event is generated only after the specified number of repeat count cycles have been completed.

Note: This setting is only valid for the advanced timers.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base Timer register base addresses
[in]	value	Unsigned int32. Repetition values 0...0xFF.

Definition at line 668 of file timer_common_all.c.

References TIM_RCR.

◆ timer_set_ti1_ch1()

void timer_set_ti1_ch1 ( uint32_t timer_peripheral )

Set Timer 1 Input to Channel 1.

The first timer capture input is taken from the timer input channel 1 only.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 517 of file timer_common_all.c.

References TIM_CR2.

◆ timer_set_ti1_ch123_xor()

void timer_set_ti1_ch123_xor ( uint32_t timer_peripheral )

Set Timer 1 Input to XOR of Three Channels.

The first timer capture input is formed from the XOR of the first three timer input channels 1, 2, 3.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 503 of file timer_common_all.c.

References TIM_CR2, and TIM_CR2_TI1S.

◆ timer_slave_set_extclockmode2()

void timer_slave_set_extclockmode2	(	uint32_t	timer_peripheral,
		enum tim_ecm2_state	state
	)

Set External Clock Mode 2.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	state	tim_ecm2_state. External Clock Mode 2 state

Definition at line 1874 of file timer_common_all.c.

References TIM_SMCR, and TIM_SMCR_ECE.

◆ timer_slave_set_filter()

void timer_slave_set_filter	(	uint32_t	timer_peripheral,
		enum tim_ic_filter	flt
	)

Set External Trigger Filter Parameters for Slave.

Set the input filter parameters for the external trigger, specifying:

the frequency of sampling from the Deadtime and Sampling clock (
See also
timer_set_clock_division)
the number of events that must occur before a transition is considered valid.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	flt	tim_ic_filter. Input Capture Filter identifier.

Definition at line 1804 of file timer_common_all.c.

References TIM_SMCR.

◆ timer_slave_set_mode()

void timer_slave_set_mode	(	uint32_t	timer_peripheral,
		uint8_t	mode
	)

Set Slave Mode.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	mode	Unsigned int8. Slave mode TIMx_SMCR SMS Slave mode selection

Definition at line 1848 of file timer_common_all.c.

References TIM_SMCR.

◆ timer_slave_set_polarity()

void timer_slave_set_polarity	(	uint32_t	timer_peripheral,
		enum tim_et_pol	pol
	)

Set External Trigger Polarity for Slave.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	pol	tim_et_pol. Slave External Trigger polarity.

Definition at line 1832 of file timer_common_all.c.

References TIM_SMCR, and TIM_SMCR_ETP.

◆ timer_slave_set_prescaler()

void timer_slave_set_prescaler	(	uint32_t	timer_peripheral,
		enum tim_ic_psc	psc
	)

Set External Trigger Prescaler for Slave.

Set the external trigger frequency division ratio.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	psc	tim_ic_psc. Input Capture sample clock prescaler.

Definition at line 1819 of file timer_common_all.c.

References TIM_SMCR.

◆ timer_slave_set_trigger()

void timer_slave_set_trigger	(	uint32_t	timer_peripheral,
		uint8_t	trigger
	)

Set Slave Trigger Source.

Parameters

[in]	timer_peripheral	Unsigned int32. Timer register address base
[in]	trigger	Unsigned int8. Slave trigger source TIMx_SMCR TS Trigger selection

Definition at line 1861 of file timer_common_all.c.

References TIM_SMCR.

◆ timer_update_on_any()

void timer_update_on_any ( uint32_t timer_peripheral )

Set the Timer to Generate Update IRQ or DMA on any Event.

The events which will generate an interrupt or DMA request can be

a counter underflow/overflow,
a forced update,
an event from the slave mode controller.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 382 of file timer_common_all.c.

References TIM_CR1.

◆ timer_update_on_overflow()

void timer_update_on_overflow ( uint32_t timer_peripheral )

Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events.

Parameters

[in] timer_peripheral Unsigned int32. Timer register address base Timer register base addresses

Definition at line 395 of file timer_common_all.c.

References TIM_CR1, and TIM_CR1_URS.

Functions

Detailed Description

Notes for All Timers

Basic TIMER handling API.

Function Documentation

◆ timer_clear_flag()

◆ timer_continuous_mode()

◆ timer_direction_down()

◆ timer_direction_up()

◆ timer_disable_break()

◆ timer_disable_break_automatic_output()

◆ timer_disable_break_main_output()

◆ timer_disable_compare_control_update_on_trigger()

◆ timer_disable_counter()

◆ timer_disable_irq()

◆ timer_disable_oc_clear()

◆ timer_disable_oc_output()

◆ timer_disable_oc_preload()

◆ timer_disable_preload()

◆ timer_disable_preload_complementry_enable_bits()

◆ timer_disable_update_event()

◆ timer_enable_break()

◆ timer_enable_break_automatic_output()

◆ timer_enable_break_main_output()

◆ timer_enable_compare_control_update_on_trigger()

◆ timer_enable_counter()

◆ timer_enable_irq()

◆ timer_enable_oc_clear()

◆ timer_enable_oc_output()

◆ timer_enable_oc_preload()

◆ timer_enable_preload()

◆ timer_enable_preload_complementry_enable_bits()

◆ timer_enable_update_event()

◆ timer_generate_event()

◆ timer_get_counter()

◆ timer_get_flag()

◆ timer_ic_disable()

◆ timer_ic_enable()

◆ timer_ic_set_filter()

◆ timer_ic_set_input()

◆ timer_ic_set_prescaler()

◆ timer_interrupt_source()

◆ timer_one_shot_mode()

◆ timer_reset_output_idle_state()

◆ timer_set_alignment()

◆ timer_set_break_lock()

◆ timer_set_break_polarity_high()

◆ timer_set_break_polarity_low()

◆ timer_set_clock_division()

◆ timer_set_counter()

◆ timer_set_deadtime()

◆ timer_set_disabled_off_state_in_idle_mode()

◆ timer_set_disabled_off_state_in_run_mode()

◆ timer_set_dma_on_compare_event()

◆ timer_set_dma_on_update_event()

◆ timer_set_enabled_off_state_in_idle_mode()

◆ timer_set_enabled_off_state_in_run_mode()

◆ timer_set_master_mode()

◆ timer_set_mode()

◆ timer_set_oc_fast_mode()

◆ timer_set_oc_idle_state_set()

◆ timer_set_oc_idle_state_unset()

◆ timer_set_oc_mode()

◆ timer_set_oc_polarity_high()

◆ timer_set_oc_polarity_low()

◆ timer_set_oc_slow_mode()

◆ timer_set_oc_value()

◆ timer_set_output_idle_state()

◆ timer_set_period()

◆ timer_set_prescaler()

◆ timer_set_repetition_counter()

◆ timer_set_ti1_ch1()

◆ timer_set_ti1_ch123_xor()

◆ timer_slave_set_extclockmode2()

◆ timer_slave_set_filter()

◆ timer_slave_set_mode()

◆ timer_slave_set_polarity()

◆ timer_slave_set_prescaler()

◆ timer_slave_set_trigger()

◆ timer_update_on_any()