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#define | RCC_D1CFGR_D1CPRE_BYP 0x0 |
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#define | RCC_D1CFGR_D1CPRE_DIV2 0x8 |
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#define | RCC_D1CFGR_D1CPRE_DIV4 0x9 |
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#define | RCC_D1CFGR_D1CPRE_DIV8 0xA |
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#define | RCC_D1CFGR_D1CPRE_DIV16 0xB |
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#define | RCC_D1CFGR_D1CPRE_DIV64 0xC |
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#define | RCC_D1CFGR_D1CPRE_DIV128 0xD |
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#define | RCC_D1CFGR_D1CPRE_DIV256 0xE |
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#define | RCC_D1CFGR_D1CPRE_DIV512 0xF |
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#define | RCC_D1CFGR_D1PPRE_BYP 0x0 |
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#define | RCC_D1CFGR_D1PPRE_DIV2 0x4 |
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#define | RCC_D1CFGR_D1PPRE_DIV4 0x5 |
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#define | RCC_D1CFGR_D1PPRE_DIV8 0x6 |
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#define | RCC_D1CFGR_D1PPRE_DIV16 0x7 |
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#define | RCC_D1CFGR_D1HPRE_BYP 0x0 |
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#define | RCC_D1CFGR_D1HPRE_DIV2 0x8 |
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#define | RCC_D1CFGR_D1HPRE_DIV4 0x9 |
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#define | RCC_D1CFGR_D1HPRE_DIV8 0xA |
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#define | RCC_D1CFGR_D1HPRE_DIV16 0xB |
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#define | RCC_D1CFGR_D1HPRE_DIV64 0xC |
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#define | RCC_D1CFGR_D1HPRE_DIV128 0xD |
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#define | RCC_D1CFGR_D1HPRE_DIV256 0xE |
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#define | RCC_D1CFGR_D1HPRE_DIV512 0xF |
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#define | RCC_D1CFGR_D1CPRE_SHIFT 8 |
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#define | RCC_D1CFGR_D1PPRE_SHIFT 4 |
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#define | RCC_D1CFGR_D1CPRE(cpre) (cpre << RCC_D1CFGR_D1CPRE_SHIFT) |
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#define | RCC_D1CFGR_D1PPRE(ppre) (ppre << RCC_D1CFGR_D1PPRE_SHIFT) |
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#define | RCC_D1CFGR_D1HPRE(hpre) (hpre) |
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