Defined Constants and Types for the STM32H7xx Reset and Clock Control More...
Data Structures | |
| struct | rcc_pll_config |
| PLL Configuration structure. More... | |
Macros | |
| #define | RCC_D1CCIPR_CKPERSEL_SHIFT 28 |
| #define | RCC_D1CCIPR_CKPERSEL_MASK 3 |
| #define | RCC_D2CCIP1R_SWPSEL_SHIFT 31 |
| #define | RCC_D2CCIP1R_FDCANSEL_SHIFT 28 |
| #define | RCC_D2CCIP1R_FDCANSEL_MASK 0x3 |
| #define | RCC_D2CCIP1R_DFSDM1SEL_SHIFT 24 |
| #define | RCC_D2CCIP1R_SPDIFSEL_SHIFT 20 |
| #define | RCC_D2CCIP1R_SPI45SEL_SHIFT 16 |
| #define | RCC_D2CCIP1R_SPI45SEL_MASK 0x7 |
| #define | RCC_D2CCIP1R_SPI123SEL_SHIFT 12 |
| #define | RCC_D2CCIP1R_SPI123SEL_MASK 0x7 |
| #define | RCC_D2CCIP1R_SAI23SEL_SHIFT 6 |
| #define | RCC_D2CCIP1R_SAISEL_MASK 0x7 |
| #define | RCC_D2CCIP2R_LPTIM1SEL_SHIFT 28 |
| #define | RCC_D2CCIP2R_CECSEL_SHIFT 22 |
| #define | RCC_D2CCIP2R_USBSEL_SHIFT 20 |
| #define | RCC_D2CCIP2R_I2C123SEL_SHIFT 12 |
| #define | RCC_D2CCIP2R_RNGSEL_MASK 0x3 |
| #define | RCC_D2CCIP2R_RNGSEL_SHIFT 8 |
| #define | RCC_D2CCIP2R_USART16SEL_SHIFT 3 |
| #define | RCC_D2CCIP2R_USART234578SEL_SHIFT 0 |
| #define | RCC_D2CCIP2R_USARTSEL_MASK 7 |
| #define | RCC_HSI_BASE_FREQUENCY 64000000UL |
| #define | _REG_BIT(base, bit) (((base) << 5) + (bit)) |
Enumerations | |
| enum | rcc_clock_source { RCC_CPUCLK , RCC_SYSCLK , RCC_PERCLK , RCC_SYSTICKCLK , RCC_HCLK3 , RCC_AHBCLK , RCC_APB1CLK , RCC_APB2CLK , RCC_APB3CLK , RCC_APB4CLK } |
| Enumerations for core system/bus clocks for user/driver/system access to base bus clocks not directly associated with a peripheral. More... | |
| enum | rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI , RCC_LSE , RCC_LSI } |
| enum | rcc_periph_clken { RCC_DMA1 = _REG_BIT(0xD8, 0) , RCC_DMA2 = _REG_BIT(0xD8, 1) , RCC_ADC12 = _REG_BIT(0xD8, 5) , RCC_ETH1MAC = _REG_BIT(0xD8, 15) , RCC_ETH1TX = _REG_BIT(0xD8, 16) , RCC_ETH1RX = _REG_BIT(0xD8, 17) , RCC_USB2OTGHSULPIEN = _REG_BIT(0xD8, 18) , RCC_USB1OTGHSEN = _REG_BIT(0xD8, 25) , RCC_USB1OTGHSULPIEN = _REG_BIT(0xD8, 26) , RCC_USB2OTGHSEN = _REG_BIT(0xD8, 27) , RCC_DCMI = _REG_BIT(0xDC, 0) , RCC_CRYP = _REG_BIT(0xDC, 4) , RCC_HASH = _REG_BIT(0xDC, 5) , RCC_RNG = _REG_BIT(0xDC, 6) , RCC_SDMMC2 = _REG_BIT(0xDC, 9) , RCC_SRAM1 = _REG_BIT(0xDC, 29) , RCC_SRAM2 = _REG_BIT(0xDC, 30) , RCC_SRAM3 = _REG_BIT(0xDC, 31) , RCC_MDMA = _REG_BIT(0xD4, 0) , RCC_DMA2D = _REG_BIT(0xD4, 4) , RCC_JPGDEC = _REG_BIT(0xD4, 5) , RCC_FMC = _REG_BIT(0xD4, 12) , RCC_QSPI = _REG_BIT(0xD4, 14) , RCC_SDMMC1 = _REG_BIT(0xD4, 16) , RCC_GPIOA = _REG_BIT(0xE0, 0) , RCC_GPIOB = _REG_BIT(0xE0, 1) , RCC_GPIOC = _REG_BIT(0xE0, 2) , RCC_GPIOD = _REG_BIT(0xE0, 3) , RCC_GPIOE = _REG_BIT(0xE0, 4) , RCC_GPIOF = _REG_BIT(0xE0, 5) , RCC_GPIOG = _REG_BIT(0xE0, 6) , RCC_GPIOH = _REG_BIT(0xE0, 7) , RCC_GPIOI = _REG_BIT(0xE0, 8) , RCC_GPIOJ = _REG_BIT(0xE0, 9) , RCC_GPIOK = _REG_BIT(0xE0, 10) , RCC_CRC = _REG_BIT(0xE0, 19) , RCC_BDMA = _REG_BIT(0xE0, 21) , RCC_ADC3 = _REG_BIT(0xE0, 24) , RCC_HSEM = _REG_BIT(0xE0, 25) , RCC_BKPSRAM = _REG_BIT(0xE0, 28) , RCC_TIM2 = _REG_BIT(0xE8, 0) , RCC_TIM3 = _REG_BIT(0xE8, 1) , RCC_TIM4 = _REG_BIT(0xE8, 2) , RCC_TIM5 = _REG_BIT(0xE8, 3) , RCC_TIM6 = _REG_BIT(0xE8, 4) , RCC_TIM7 = _REG_BIT(0xE8, 5) , RCC_TIM12 = _REG_BIT(0xE8, 6) , RCC_TIM13 = _REG_BIT(0xE8, 7) , RCC_TIM14 = _REG_BIT(0xE8, 8) , RCC_LPTIM1 = _REG_BIT(0xE8, 9) , RCC_SPI2 = _REG_BIT(0xE8, 14) , RCC_SPI3 = _REG_BIT(0xE8, 15) , RCC_SPDIFRX = _REG_BIT(0xE8, 16) , RCC_USART2 = _REG_BIT(0xE8, 17) , RCC_USART3 = _REG_BIT(0xE8, 18) , RCC_UART4 = _REG_BIT(0xE8, 19) , RCC_UART5 = _REG_BIT(0xE8, 20) , RCC_I2C1 = _REG_BIT(0xE8, 21) , RCC_I2C2 = _REG_BIT(0xE8, 22) , RCC_I2C3 = _REG_BIT(0xE8, 23) , RCC_CEC = _REG_BIT(0xE8, 27) , RCC_DAC = _REG_BIT(0xE8, 29) , RCC_UART7 = _REG_BIT(0xE8, 30) , RCC_UART8 = _REG_BIT(0xE8, 31) , RCC_CRS = _REG_BIT(0xEC, 1) , RCC_SWP = _REG_BIT(0xEC, 2) , RCC_OPAMP = _REG_BIT(0xEC, 4) , RCC_MDIO = _REG_BIT(0xEC, 5) , RCC_FDCAN = _REG_BIT(0xEC, 8) , RCC_TIM1 = _REG_BIT(0xF0, 0) , RCC_TIM8 = _REG_BIT(0xF0, 1) , RCC_USART1 = _REG_BIT(0xF0, 4) , RCC_USART6 = _REG_BIT(0xF0, 5) , RCC_SPI1 = _REG_BIT(0xF0, 12) , RCC_SPI4 = _REG_BIT(0xF0, 13) , RCC_TIM15 = _REG_BIT(0xF0, 16) , RCC_TIM16 = _REG_BIT(0xF0, 17) , RCC_TIM17 = _REG_BIT(0xF0, 18) , RCC_SPI5 = _REG_BIT(0xF0, 20) , RCC_SAI1 = _REG_BIT(0xF0, 22) , RCC_SAI2 = _REG_BIT(0xF0, 23) , RCC_SAI3 = _REG_BIT(0xF0, 24) , RCC_DFSDM = _REG_BIT(0xF0, 28) , RCC_HRTIM = _REG_BIT(0xF0, 29) , RCC_LTDCEN = _REG_BIT(0xE4, 3) , RCC_WWDG1EN = _REG_BIT(0xE4, 6) , RCC_SYSCFG = _REG_BIT(0xF4, 1) , RCC_LPUART1 = _REG_BIT(0xF4, 3) , RCC_SPI6 = _REG_BIT(0xF4, 5) , RCC_I2C4 = _REG_BIT(0xF4, 7) , RCC_LPTIM2 = _REG_BIT(0xF4, 9) , RCC_LPTIM3 = _REG_BIT(0xF4, 10) , RCC_LPTIM4 = _REG_BIT(0xF4, 11) , RCC_LPTIM5 = _REG_BIT(0xF4, 12) , RCC_COMP12 = _REG_BIT(0xF4, 14) , RCC_VREF = _REG_BIT(0xF4, 15) , RCC_RTCAPB = _REG_BIT(0xF4, 16) , RCC_SAI4 = _REG_BIT(0xF4, 21) } |
| enum | rcc_periph_rst { RST_DMA1 = _REG_BIT(0x80, 0) , RST_DMA2 = _REG_BIT(0x80, 1) , RST_ADC12 = _REG_BIT(0x80, 5) , RST_ETH1MAC = _REG_BIT(0x80, 15) , RST_USB1OTGRST = _REG_BIT(0x80, 25) , RST_USB2OTGRST = _REG_BIT(0x80, 27) , RST_DCMI = _REG_BIT(0xDC, 0) , RST_CRYP = _REG_BIT(0xDC, 4) , RST_HASH = _REG_BIT(0xDC, 5) , RST_RNG = _REG_BIT(0xDC, 6) , RST_SDMMC2 = _REG_BIT(0xDC, 9) , RST_MDMA = _REG_BIT(0x7C, 0) , RST_DMA2D = _REG_BIT(0x7C, 4) , RST_JPGDEC = _REG_BIT(0x7C, 5) , RST_FMC = _REG_BIT(0x7C, 12) , RST_QSPI = _REG_BIT(0x7C, 14) , RST_SDMMC1 = _REG_BIT(0x7C, 16) , RST_GPIOA = _REG_BIT(0x88, 0) , RST_GPIOB = _REG_BIT(0x88, 1) , RST_GPIOC = _REG_BIT(0x88, 2) , RST_GPIOD = _REG_BIT(0x88, 3) , RST_GPIOE = _REG_BIT(0x88, 4) , RST_GPIOF = _REG_BIT(0x88, 5) , RST_GPIOG = _REG_BIT(0x88, 6) , RST_GPIOH = _REG_BIT(0x88, 7) , RST_GPIOI = _REG_BIT(0x88, 8) , RST_GPIOJ = _REG_BIT(0x88, 9) , RST_GPIOK = _REG_BIT(0x88, 10) , RST_CRC = _REG_BIT(0x88, 19) , RST_BDMA = _REG_BIT(0x88, 21) , RST_ADC3 = _REG_BIT(0x88, 24) , RST_HSEM = _REG_BIT(0x88, 25) , RST_TIM2 = _REG_BIT(0x90, 0) , RST_TIM3 = _REG_BIT(0x90, 1) , RST_TIM4 = _REG_BIT(0x90, 2) , RST_TIM5 = _REG_BIT(0x90, 3) , RST_TIM6 = _REG_BIT(0x90, 4) , RST_TIM7 = _REG_BIT(0x90, 5) , RST_TIM12 = _REG_BIT(0x90, 6) , RST_TIM13 = _REG_BIT(0x90, 7) , RST_TIM14 = _REG_BIT(0x90, 8) , RST_LPTIM1 = _REG_BIT(0x90, 9) , RST_SPI2 = _REG_BIT(0x90, 14) , RST_SPI3 = _REG_BIT(0x90, 15) , RST_SPDIFRX = _REG_BIT(0x90, 16) , RST_USART2 = _REG_BIT(0x90, 17) , RST_USART3 = _REG_BIT(0x90, 18) , RST_UART4 = _REG_BIT(0x90, 19) , RST_UART5 = _REG_BIT(0x90, 20) , RST_I2C1 = _REG_BIT(0x90, 21) , RST_I2C2 = _REG_BIT(0x90, 22) , RST_I2C3 = _REG_BIT(0x90, 23) , RST_CEC = _REG_BIT(0x90, 27) , RST_DAC = _REG_BIT(0x90, 29) , RST_UART7 = _REG_BIT(0x90, 30) , RST_UART8 = _REG_BIT(0x90, 31) , RST_CRS = _REG_BIT(0x94, 1) , RST_SWP = _REG_BIT(0x94, 2) , RST_OPAMP = _REG_BIT(0x94, 4) , RST_MDIO = _REG_BIT(0x94, 5) , RST_FDCAN = _REG_BIT(0x94, 8) , RST_TIM1 = _REG_BIT(0x98, 0) , RST_TIM8 = _REG_BIT(0x98, 1) , RST_USART1 = _REG_BIT(0x98, 4) , RST_USART6 = _REG_BIT(0x98, 5) , RST_SPI1 = _REG_BIT(0x98, 12) , RST_SPI4 = _REG_BIT(0x98, 13) , RST_TIM15 = _REG_BIT(0x98, 16) , RST_TIM16 = _REG_BIT(0x98, 17) , RST_TIM17 = _REG_BIT(0x98, 18) , RST_SPI5 = _REG_BIT(0x98, 20) , RST_SAI1 = _REG_BIT(0x98, 22) , RST_SAI2 = _REG_BIT(0x98, 23) , RST_SAI3 = _REG_BIT(0x98, 24) , RST_DFSDM = _REG_BIT(0x98, 28) , RST_HRTIM = _REG_BIT(0x98, 29) , RST_LTDCRST = _REG_BIT(0x8C, 3) , RST_SYSCFG = _REG_BIT(0x9C, 1) , RST_LPUART1 = _REG_BIT(0x9C, 3) , RST_SPI6 = _REG_BIT(0x9C, 5) , RST_I2C4 = _REG_BIT(0x9C, 7) , RST_LPTIM2 = _REG_BIT(0x9C, 9) , RST_LPTIM3 = _REG_BIT(0x9C, 10) , RST_LPTIM4 = _REG_BIT(0x9C, 11) , RST_LPTIM5 = _REG_BIT(0x9C, 12) , RST_COMP12 = _REG_BIT(0x9C, 14) , RST_VREF = _REG_BIT(0x9C, 15) , RST_SAI4 = _REG_BIT(0x9C, 21) } |
Functions | |
| void | rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en) |
| RCC Enable Peripheral Clocks. More... | |
| void | rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en) |
| RCC Disable Peripheral Clocks. More... | |
| void | rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset) |
| RCC Reset Peripherals. More... | |
| void | rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset) |
| RCC Remove Reset on Peripherals. More... | |
| void | rcc_periph_clock_enable (enum rcc_periph_clken clken) |
| Enable Peripheral Clock in running mode. More... | |
| void | rcc_periph_clock_disable (enum rcc_periph_clken clken) |
| Disable Peripheral Clock in running mode. More... | |
| void | rcc_periph_reset_pulse (enum rcc_periph_rst rst) |
| Reset Peripheral, pulsed. More... | |
| void | rcc_periph_reset_hold (enum rcc_periph_rst rst) |
| Reset Peripheral, hold. More... | |
| void | rcc_periph_reset_release (enum rcc_periph_rst rst) |
| Reset Peripheral, release. More... | |
| void | rcc_set_mco (uint32_t mcosrc) |
| Select the source of Microcontroller Clock Output. More... | |
| void | rcc_osc_bypass_enable (enum rcc_osc osc) |
| RCC Enable Bypass. More... | |
| void | rcc_osc_bypass_disable (enum rcc_osc osc) |
| RCC Disable Bypass. More... | |
| bool | rcc_is_osc_ready (enum rcc_osc osc) |
| Is the given oscillator ready? More... | |
| void | rcc_wait_for_osc_ready (enum rcc_osc osc) |
| Wait for Oscillator Ready. More... | |
| uint16_t | rcc_get_div_from_hpre (uint8_t div_val) |
| This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More... | |
Detailed Description
Defined Constants and Types for the STM32H7xx Reset and Clock Control
- Version
- 1.0.0 LGPL License Terms libopencm3 License
Macro Definition Documentation
◆ _REG_BIT
◆ RCC_D1CCIPR_CKPERSEL_MASK
◆ RCC_D1CCIPR_CKPERSEL_SHIFT
◆ RCC_D2CCIP1R_DFSDM1SEL_SHIFT
◆ RCC_D2CCIP1R_FDCANSEL_MASK
◆ RCC_D2CCIP1R_FDCANSEL_SHIFT
◆ RCC_D2CCIP1R_SAI23SEL_SHIFT
◆ RCC_D2CCIP1R_SAISEL_MASK
◆ RCC_D2CCIP1R_SPDIFSEL_SHIFT
◆ RCC_D2CCIP1R_SPI123SEL_MASK
◆ RCC_D2CCIP1R_SPI123SEL_SHIFT
◆ RCC_D2CCIP1R_SPI45SEL_MASK
◆ RCC_D2CCIP1R_SPI45SEL_SHIFT
◆ RCC_D2CCIP1R_SWPSEL_SHIFT
◆ RCC_D2CCIP2R_CECSEL_SHIFT
◆ RCC_D2CCIP2R_I2C123SEL_SHIFT
◆ RCC_D2CCIP2R_LPTIM1SEL_SHIFT
◆ RCC_D2CCIP2R_RNGSEL_MASK
◆ RCC_D2CCIP2R_RNGSEL_SHIFT
◆ RCC_D2CCIP2R_USART16SEL_SHIFT
◆ RCC_D2CCIP2R_USART234578SEL_SHIFT
◆ RCC_D2CCIP2R_USARTSEL_MASK
◆ RCC_D2CCIP2R_USBSEL_SHIFT
◆ RCC_HSI_BASE_FREQUENCY
Enumeration Type Documentation
◆ rcc_clock_source
| enum rcc_clock_source |
◆ rcc_osc
| enum rcc_osc |
◆ rcc_periph_clken
| enum rcc_periph_clken |
◆ rcc_periph_rst
| enum rcc_periph_rst |
Function Documentation
◆ rcc_get_div_from_hpre()
| uint16_t rcc_get_div_from_hpre | ( | uint8_t | div_val | ) |
This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.
- Parameters
-
div_val Masked and shifted divider value from register (e.g. RCC_CFGR)
Definition at line 260 of file rcc_common_all.c.
◆ rcc_is_osc_ready()
| bool rcc_is_osc_ready | ( | enum rcc_osc | osc | ) |
Is the given oscillator ready?
- Parameters
-
osc Oscillator ID
- Returns
- true if the hardware indicates the oscillator is ready.
◆ rcc_osc_bypass_disable()
| void rcc_osc_bypass_disable | ( | enum rcc_osc | osc | ) |
RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.
- Note
- The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
- Parameters
-
[in] osc Oscillator ID. Only HSE and LSE have effect.
Definition at line 238 of file rcc_common_all.c.
◆ rcc_osc_bypass_enable()
| void rcc_osc_bypass_enable | ( | enum rcc_osc | osc | ) |
RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.
- Note
- The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
- Parameters
-
[in] osc Oscillator ID. Only HSE and LSE have effect.
Definition at line 208 of file rcc_common_all.c.
References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.
◆ rcc_periph_clock_disable()
| void rcc_periph_clock_disable | ( | enum rcc_periph_clken | clken | ) |
Disable Peripheral Clock in running mode.
Disable the clock on particular peripheral.
- Parameters
-
[in] clken rcc_periph_clken Peripheral RCC
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 139 of file rcc_common_all.c.
References _RCC_REG.
◆ rcc_periph_clock_enable()
| void rcc_periph_clock_enable | ( | enum rcc_periph_clken | clken | ) |
Enable Peripheral Clock in running mode.
Enable the clock on particular peripheral.
- Parameters
-
[in] clken rcc_periph_clken Peripheral RCC
For available constants, see rcc_periph_clken (RCC_UART1 for example)
Definition at line 127 of file rcc_common_all.c.
References _RCC_BIT, and _RCC_REG.
Referenced by pwr_set_vos_scale().
◆ rcc_periph_reset_hold()
| void rcc_periph_reset_hold | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, hold.
Reset particular peripheral, and hold in reset state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 166 of file rcc_common_all.c.
◆ rcc_periph_reset_pulse()
| void rcc_periph_reset_pulse | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, pulsed.
Reset particular peripheral, and restore to working state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 152 of file rcc_common_all.c.
◆ rcc_periph_reset_release()
| void rcc_periph_reset_release | ( | enum rcc_periph_rst | rst | ) |
Reset Peripheral, release.
Restore peripheral from reset state to working state.
- Parameters
-
[in] rst rcc_periph_rst Peripheral reset
For available constants, see rcc_periph_rst (RST_UART1 for example)
Definition at line 179 of file rcc_common_all.c.
References _RCC_REG.
◆ rcc_peripheral_clear_reset()
| void rcc_peripheral_clear_reset | ( | volatile uint32_t * | reg, |
| uint32_t | clear_reset | ||
| ) |
RCC Remove Reset on Peripherals.
Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
- rcc_periph_reset_pulse if you are only going to toggle reset anyway.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] clear_reset Unsigned int32. Logical OR of all resets to be removed: - If register is RCC_AHBRSTR, from rcc_ahbrstr_rst
- If register is RCC_APB1RSTR, from rcc_apb1rstr_rst
- If register is RCC_APB2RSTR, from rcc_apb2rstr_rst
Definition at line 111 of file rcc_common_all.c.
◆ rcc_peripheral_disable_clock()
| void rcc_peripheral_disable_clock | ( | volatile uint32_t * | reg, |
| uint32_t | en | ||
| ) |
RCC Disable Peripheral Clocks.
Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] en Unsigned int32. Logical OR of all enables to be used for disabling. - If register is RCC_AHBENR, from rcc_ahbenr_en
- If register is RCC_APB1ENR, from rcc_apb1enr_en
- If register is RCC_APB2ENR, from rcc_apb2enr_en
Definition at line 66 of file rcc_common_all.c.
◆ rcc_peripheral_enable_clock()
| void rcc_peripheral_enable_clock | ( | volatile uint32_t * | reg, |
| uint32_t | en | ||
| ) |
RCC Enable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] en Unsigned int32. Logical OR of all enables to be set - If register is RCC_AHBENR, from rcc_ahbenr_en
- If register is RCC_APB1ENR, from rcc_apb1enr_en
- If register is RCC_APB2ENR, from rcc_apb2enr_en
Definition at line 44 of file rcc_common_all.c.
◆ rcc_peripheral_reset()
| void rcc_peripheral_reset | ( | volatile uint32_t * | reg, |
| uint32_t | reset | ||
| ) |
RCC Reset Peripherals.
Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.
- See also
- rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
- rcc_periph_reset_pulse if you are only going to toggle reset anyway.
- Parameters
-
[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) [in] reset Unsigned int32. Logical OR of all resets. - If register is RCC_AHBRSTR, from rcc_ahbrstr_rst
- If register is RCC_APB1RSTR, from rcc_apb1rstr_rst
- If register is RCC_APB2RSTR, from rcc_apb2rstr_rst
Definition at line 88 of file rcc_common_all.c.
◆ rcc_set_mco()
| void rcc_set_mco | ( | uint32_t | mcosrc | ) |
Select the source of Microcontroller Clock Output.
Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1
- Parameters
-
[in] mcosrc the unshifted source bits
Definition at line 191 of file rcc_common_all.c.
References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.
◆ rcc_wait_for_osc_ready()
| void rcc_wait_for_osc_ready | ( | enum rcc_osc | osc | ) |
Wait for Oscillator Ready.
Block until the hardware indicates that the Oscillator is ready.
- Parameters
-
osc Oscillator ID
