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| #define | RCC_CR MMIO32(RCC_BASE + 0x000) |
| |
| #define | RCC_ICSCR MMIO32(RCC_BASE + 0x004) /* Y-devices only */ |
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| #define | RCC_HSICFGR MMIO32(RCC_BASE + 0x004) /* V-devices only */ |
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| #define | RCC_CRRCR MMIO32(RCC_BASE + 0x008) |
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| #define | RCC_CSICFGR MMIO32(RCC_BASE + 0x00C) /* V-devices only */ |
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| #define | RCC_CFGR MMIO32(RCC_BASE + 0x010) |
| |
| #define | RCC_D1CFGR MMIO32(RCC_BASE + 0x018) |
| |
| #define | RCC_D2CFGR MMIO32(RCC_BASE + 0x01C) |
| |
| #define | RCC_D3CFGR MMIO32(RCC_BASE + 0x020) |
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| #define | RCC_PLLCKSELR MMIO32(RCC_BASE + 0x028) |
| |
| #define | RCC_PLLCFGR MMIO32(RCC_BASE + 0x02C) |
| |
| #define | RCC_PLLDIVR(n) MMIO32(RCC_BASE + 0x030 + (0x08 * ((n) - 1))) |
| |
| #define | RCC_PLLFRACR(n) MMIO32(RCC_BASE + 0x030 + (0x08 * ((n) - 1))) |
| |
| #define | RCC_PLL1DIVR RCC_PLLDIVR(1) |
| |
| #define | RCC_PLL1FRACR RCC_PLLFRACR(1) |
| |
| #define | RCC_PLL2DIVR RCC_PLLDIVR(2) |
| |
| #define | RCC_PLL2FRACR RCC_PLLFRACR(2) |
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| #define | RCC_PLL3DIVR RCC_PLLDIVR(3) |
| |
| #define | RCC_PLL3FRACR RCC_PLLFRACR(3) |
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| #define | RCC_D1CCIPR MMIO32(RCC_BASE + 0x04C) |
| |
| #define | RCC_D2CCIP1R MMIO32(RCC_BASE + 0x050) |
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| #define | RCC_D2CCIP2R MMIO32(RCC_BASE + 0x054) |
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| #define | RCC_D3CCIPR MMIO32(RCC_BASE + 0x058) |
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| #define | RCC_AHB1RSTR MMIO32(RCC_BASE + 0x080) |
| |
| #define | RCC_AHB2RSTR MMIO32(RCC_BASE + 0x084) |
| |
| #define | RCC_AHB3RSTR MMIO32(RCC_BASE + 0x07C) |
| |
| #define | RCC_AHB4RSTR MMIO32(RCC_BASE + 0x088) |
| |
| #define | RCC_APB1LRSTR MMIO32(RCC_BASE + 0x090) |
| |
| #define | RCC_APB1HRSTR MMIO32(RCC_BASE + 0x094) |
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| #define | RCC_APB2RSTR MMIO32(RCC_BASE + 0x098) |
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| #define | RCC_APB3RSTR MMIO32(RCC_BASE + 0x08C) |
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| #define | RCC_APB4RSTR MMIO32(RCC_BASE + 0x09C) |
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| #define | RCC_AHB1ENR MMIO32(RCC_BASE + 0x0D8) |
| |
| #define | RCC_AHB2ENR MMIO32(RCC_BASE + 0x0DC) |
| |
| #define | RCC_AHB3ENR MMIO32(RCC_BASE + 0x0D4) |
| |
| #define | RCC_AHB4ENR MMIO32(RCC_BASE + 0x0E0) |
| |
| #define | RCC_APB1LENR MMIO32(RCC_BASE + 0x0E8) |
| |
| #define | RCC_APB1HENR MMIO32(RCC_BASE + 0x0EC) |
| |
| #define | RCC_APB2ENR MMIO32(RCC_BASE + 0x0F0) |
| |
| #define | RCC_APB3ENR MMIO32(RCC_BASE + 0x0E4) |
| |
| #define | RCC_APB4ENR MMIO32(RCC_BASE + 0x0F4) |
| |
| #define | RCC_AHB1LPENR MMIO32(RCC_BASE + 0x100) |
| |
| #define | RCC_AHB2LPENR MMIO32(RCC_BASE + 0x104) |
| |
| #define | RCC_AHB4LPENR MMIO32(RCC_BASE + 0x108) |
| |
| #define | RCC_APB1LLPENR MMIO32(RCC_BASE + 0x110) |
| |
| #define | RCC_APB1HLPENR MMIO32(RCC_BASE + 0x114) |
| |
| #define | RCC_APB2LPENR MMIO32(RCC_BASE + 0x118) |
| |
| #define | RCC_APB3LPENR MMIO32(RCC_BASE + 0x10C) |
| |
| #define | RCC_APB4LPENR MMIO32(RCC_BASE + 0x11C) |
| |
| #define | RCC_BDCR MMIO32(RCC_BASE + 0x70) |
| |
| #define | RCC_CSR MMIO32(RCC_BASE + 0x74) |
| |
| #define | RCC_SSCGR MMIO32(RCC_BASE + 0x80) |
| |
| #define | RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) |
| |
| #define | RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) |
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| #define | RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C) |
| |
| #define | RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90) |
| |
