Collaboration diagram for RCC_PLLCFGR Values:

Macros
#define	RCC_PLLCFGR_PLLRGE_1_2MHZ 0

#define	RCC_PLLCFGR_PLLRGE_2_4MHZ 1

#define	RCC_PLLCFGR_PLLRGE_4_8MHZ 2

#define	RCC_PLLCFGR_PLLRGE_8_16MHZ 3

#define	RCC_PLLCFGR_DIVR3EN BIT24

#define	RCC_PLLCFGR_DIVQ3EN BIT23

#define	RCC_PLLCFGR_DIVP3EN BIT22

#define	RCC_PLLCFGR_DIVR2EN BIT21

#define	RCC_PLLCFGR_DIVQ2EN BIT20

#define	RCC_PLLCFGR_DIVP2EN BIT19

#define	RCC_PLLCFGR_DIVR1EN BIT18

#define	RCC_PLLCFGR_DIVQ1EN BIT17

#define	RCC_PLLCFGR_DIVP1EN BIT16

#define	RCC_PLLCFGR_PLL3RGE_SHIFT 10

#define	RCC_PLLCFGR_PLL3VCO_WIDE 0 /* 192 - 836MHz base output. */

#define	RCC_PLLCFGR_PLL3VCO_MED BIT9 /* 150 - 420MHz base output. */

#define	RCC_PLLCFGR_PLL3FRACEN BIT8

#define	RCC_PLLCFGR_PLL2RGE_SHIFT 6

#define	RCC_PLLCFGR_PLL2VCO_WIDE 0 /* 192 - 836MHz base output. */

#define	RCC_PLLCFGR_PLL2VCO_MED BIT5 /* 150 - 420MHz base output. */

#define	RCC_PLLCFGR_PLL2FRACEN BIT4

#define	RCC_PLLCFGR_PLL1RGE_SHIFT 2

#define	RCC_PLLCFGR_PLL1VCO_WIDE 0 /* 192 - 836MHz base output. */

#define	RCC_PLLCFGR_PLL1VCO_MED BIT1 /* 150 - 420MHz base output. */

#define	RCC_PLLCFGR_PLL1FRACEN BIT0

Detailed Description

Macro Definition Documentation

◆ RCC_PLLCFGR_DIVP1EN

#define RCC_PLLCFGR_DIVP1EN BIT16

Definition at line 279 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVP2EN

#define RCC_PLLCFGR_DIVP2EN BIT19

Definition at line 276 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVP3EN

#define RCC_PLLCFGR_DIVP3EN BIT22

Definition at line 273 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVQ1EN

#define RCC_PLLCFGR_DIVQ1EN BIT17

Definition at line 278 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVQ2EN

#define RCC_PLLCFGR_DIVQ2EN BIT20

Definition at line 275 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVQ3EN

#define RCC_PLLCFGR_DIVQ3EN BIT23

Definition at line 272 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVR1EN

#define RCC_PLLCFGR_DIVR1EN BIT18

Definition at line 277 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVR2EN

#define RCC_PLLCFGR_DIVR2EN BIT21

Definition at line 274 of file h7/rcc.h.

◆ RCC_PLLCFGR_DIVR3EN

#define RCC_PLLCFGR_DIVR3EN BIT24

Definition at line 271 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL1FRACEN

#define RCC_PLLCFGR_PLL1FRACEN BIT0

Definition at line 291 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL1RGE_SHIFT

#define RCC_PLLCFGR_PLL1RGE_SHIFT 2

Definition at line 288 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL1VCO_MED

#define RCC_PLLCFGR_PLL1VCO_MED BIT1 /* 150 - 420MHz base output. */

Definition at line 290 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL1VCO_WIDE

#define RCC_PLLCFGR_PLL1VCO_WIDE 0 /* 192 - 836MHz base output. */

Definition at line 289 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL2FRACEN

#define RCC_PLLCFGR_PLL2FRACEN BIT4

Definition at line 287 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL2RGE_SHIFT

#define RCC_PLLCFGR_PLL2RGE_SHIFT 6

Definition at line 284 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL2VCO_MED

#define RCC_PLLCFGR_PLL2VCO_MED BIT5 /* 150 - 420MHz base output. */

Definition at line 286 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL2VCO_WIDE

#define RCC_PLLCFGR_PLL2VCO_WIDE 0 /* 192 - 836MHz base output. */

Definition at line 285 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL3FRACEN

#define RCC_PLLCFGR_PLL3FRACEN BIT8

Definition at line 283 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL3RGE_SHIFT

#define RCC_PLLCFGR_PLL3RGE_SHIFT 10

Definition at line 280 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL3VCO_MED

#define RCC_PLLCFGR_PLL3VCO_MED BIT9 /* 150 - 420MHz base output. */

Definition at line 282 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLL3VCO_WIDE

#define RCC_PLLCFGR_PLL3VCO_WIDE 0 /* 192 - 836MHz base output. */

Definition at line 281 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLLRGE_1_2MHZ

#define RCC_PLLCFGR_PLLRGE_1_2MHZ 0

Definition at line 266 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLLRGE_2_4MHZ

#define RCC_PLLCFGR_PLLRGE_2_4MHZ 1

Definition at line 267 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLLRGE_4_8MHZ

#define RCC_PLLCFGR_PLLRGE_4_8MHZ 2

Definition at line 268 of file h7/rcc.h.

◆ RCC_PLLCFGR_PLLRGE_8_16MHZ

#define RCC_PLLCFGR_PLLRGE_8_16MHZ 3

Definition at line 269 of file h7/rcc.h.

Macros