|
#define | RCC_D2CCIP1R_SWPSEL_PCLK 0x0 |
|
#define | RCC_D2CCIP1R_SWPSEL_HSI 0x1 |
|
#define | RCC_D2CCIP1R_FDCANSEL_HSE 0x0 |
|
#define | RCC_D2CCIP1R_FDCANSEL_PLL1Q 0x1 |
|
#define | RCC_D2CCIP1R_FDCANSEL_PLL2Q 0x2 |
|
#define | RCC_D2CCIP1R_DFSDM1SEL_PCLK2 0x0 |
|
#define | RCC_D2CCIP1R_DFSDM1SEL_SYSCLK 0x1 |
|
#define | RCC_D2CCIP1R_SPDIFSEL_PLL1Q 0x0 |
|
#define | RCC_D2CCIP1R_SPDIFSEL_PLL2R 0x1 |
|
#define | RCC_D2CCIP1R_SPDIFSEL_PLL3R 0x2 |
|
#define | RCC_D2CCIP1R_SPDIFSEL_HSI 0x3 |
|
#define | RCC_D2CCIP1R_SPI45SEL_APB4 0x0 |
|
#define | RCC_D2CCIP1R_SPI45SEL_PLL2Q 0x1 |
|
#define | RCC_D2CCIP1R_SPI45SEL_PLL3Q 0x2 |
|
#define | RCC_D2CCIP1R_SPI45SEL_HSI 0x3 |
|
#define | RCC_D2CCIP1R_SPI45SEL_CSI 0x4 |
|
#define | RCC_D2CCIP1R_SPI45SEL_HSE 0x5 |
|
#define | RCC_D2CCIP1R_SPI123SEL_PLL1Q 0x0 |
|
#define | RCC_D2CCIP1R_SPI123SEL_PLL2P 0x1 |
|
#define | RCC_D2CCIP1R_SPI123SEL_PLL3P 0x2 |
|
#define | RCC_D2CCIP1R_SPI123SEL_I2SCKIN 0x3 |
|
#define | RCC_D2CCIP1R_SPI123SEL_PERCK 0x4 |
|
#define | RCC_D2CCIP1R_SAISEL_PLL1Q 0x0 |
|
#define | RCC_D2CCIP1R_SAISEL_PLL2P 0x1 |
|
#define | RCC_D2CCIP1R_SAISEL_PLL3P 0x2 |
|
#define | RCC_D2CCIP1R_SAISEL_I2SCKIN 0x3 |
|
#define | RCC_D2CCIP1R_SAISEL_PERCK 0x4 |
|